JPH0340469A - Manufacture of mesa type semiconductor device - Google Patents
Manufacture of mesa type semiconductor deviceInfo
- Publication number
- JPH0340469A JPH0340469A JP17623889A JP17623889A JPH0340469A JP H0340469 A JPH0340469 A JP H0340469A JP 17623889 A JP17623889 A JP 17623889A JP 17623889 A JP17623889 A JP 17623889A JP H0340469 A JPH0340469 A JP H0340469A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- mask
- semiconductor substrate
- film
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- JVJQPDTXIALXOG-UHFFFAOYSA-N nitryl fluoride Chemical compound [O-][N+](F)=O JVJQPDTXIALXOG-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 102000030938 small GTPase Human genes 0.000 description 1
- 108060007624 small GTPase Proteins 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Thyristors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、メサ型半導体装置の製造方法に関し、特に、
半導体基板表面から内部にかけて開口を設置することに
よりメサ部を形成するメサ型半導体装置例えばゲート・
ターン・オフ・サイリスタ（Ｇａｔｅ Ｔｕｒｎ ｏｆ
ｆ ＴｈｙｒｉｓｔｏｒここからはＧ、Ｔ。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a mesa-type semiconductor device, and in particular,
A mesa-type semiconductor device, in which a mesa portion is formed by installing an opening from the surface of a semiconductor substrate to the inside, such as a gate
Gate Turn of Thyristor
f Thyristor G, T from here.
０と記載する）に好適する。0)).
（従来の技術）
半導体装置では、接合端部を半導体基板表面に露出させ
るプレイナ型に対して、接合端部を半導体基板の露出面
に導出していわゆるヘベル面を形成して耐圧特性を改善
したりするメサ型も多用されている。メサ構造を備える
半導体装置としては、−例としてセンターゲート方式の
Ｇ、Ｔ、○があり、その構造を第１図の断面図に示した
。(Prior art) In semiconductor devices, in contrast to the planar type in which the bonding end is exposed on the surface of the semiconductor substrate, the bonding end is guided to the exposed surface of the semiconductor substrate to form a so-called hevel surface to improve withstand voltage characteristics. Mesa-type structures are also frequently used. Examples of semiconductor devices having a mesa structure include center gate type G, T, and ○, the structure of which is shown in the cross-sectional view of FIG.
このエミッタ領域の構造も小型のＧ、Ｔ、○では、メサ
型でなくいわゆるプレイナ構造が採用されているのに対
して、例えば２５００ Ｖ〜４５００ Ｖの大電圧の耐
圧特性が必要な型即ち大型ではメサ型が採用されている
。The structure of this emitter region is also a so-called planar structure instead of a mesa type in the small G, T, and ○, whereas in the case of a large type that requires high voltage withstand characteristics of, for example, 2500 V to 4500 V. In this case, a mesa type is adopted.
求められる耐圧特性が例えば２５００ Ｖ〜４５００
Ｖの大型Ｇ、Ｔ、○では、表面濃度がほぼ１０”／ｃｃ
のＮ−シリコン半導体基板１の両面からＢを導入して、
表面濃度が１０ ／ｃｃ程度の２層２を設け、その
一方を陽極として動作させ、他方にはＰなどエミッタ領
域３・・・を形成してＰＮＰＮの４層構造とし、この２
層２をゲート層として機能させるが一般的な構造である
。従って、半導体基板１の層間には、当然ＰＮ接合が存
在する。また、この各メサ型エミッタ領域３・・・には
銅、モリブデン及びタングステンなどからなる導電材料
（図示せず）を圧接配置して夫々の導通を図っている。For example, the required voltage resistance is 2500 V to 4500 V.
For large G, T, and ○ of V, the surface concentration is approximately 10"/cc
B is introduced from both sides of the N-silicon semiconductor substrate 1,
Two layers 2 with a surface concentration of about 10/cc are provided, one of which operates as an anode, and an emitter region 3 of P etc. formed on the other to form a four-layer structure of PNPN.
This is a common structure in which layer 2 functions as a gate layer. Therefore, a PN junction naturally exists between the layers of the semiconductor substrate 1. Further, a conductive material (not shown) made of copper, molybdenum, tungsten, or the like is placed in pressure contact with each of the mesa-type emitter regions 3 . . . to achieve electrical continuity.
メサ型エミッタ領域３の形成に当たっては（複数のメサ
部形成を単一の部分の説明で代表させる）、第２図にあ
るように（第１図と同一の部品には同じ番号を付けた）
シリコン半導体基板１には、マスクとして機能する酸化
珪素被膜４を被覆後、公知のＰ Ｅ Ｐ （Ｐｈｏｔｏ
Ｅｎｇｒａｖｉｎｇ Ｐｒｏｃｅｓｓ）を行う。即ち
、レジスト層５を被着してからの露光・現像更に食刻工
程により開口６を設けてから、レジスト層５を剥離して
開口６に露出した半導体基板１を酸化珪素被膜４をマス
クとして食刻する。In forming the mesa-type emitter region 3, as shown in Fig. 2 (the formation of multiple mesas is represented by the explanation of a single part) (the same parts as in Fig. 1 are given the same numbers).
After coating the silicon semiconductor substrate 1 with a silicon oxide film 4 that functions as a mask, a known PEP (Photo
Engraving Process). That is, after depositing the resist layer 5, exposing, developing, and etching to form an opening 6, the resist layer 5 is peeled off and the semiconductor substrate 1 exposed in the opening 6 is exposed using the silicon oxide film 4 as a mask. engrave.
この工程は、半導体基板１に形成したエミッタ領域３
（Ｎりとベース領域（Ｐ層）６間に形成されたＰＮ接合
７が露出するまで実施する０食刻工程の深さは、接合の
位置にもよるが２０〜３０ｐに及ぶ。This process involves emitter region 3 formed on semiconductor substrate 1.
The depth of the zero etching step, which is performed until the PN junction 7 formed between the N layer and the base region (P layer) 6 is exposed, ranges from 20 to 30 p, depending on the position of the junction.
（発明が解決しようとする課題）
この工程により形成したメサ構造では、第２図に明らか
なように、メサ面は半導体基板１の表面とほぼ９０°と
切立っており、その後の取扱いによって簡単にこの部分
が欠けてしまう。この現像は、ステンレスピンセットの
ように硬い物質によってだけでなく、樹脂を被覆したピ
ンセットや治具類でもぶつかると欠ける。この欠けが発
生した場合、接合にまでに達するとリークを引起こす外
に、欠は即ちシリコン屑によって他の部分にキズを付は
リークや短絡の原因になる。(Problem to be Solved by the Invention) In the mesa structure formed by this process, as is clear from FIG. This part is missing. This development is chipped not only by hard materials such as stainless steel tweezers, but also by collisions with resin-coated tweezers and jigs. If this chipping occurs, not only will it cause a leak if it reaches the junction, but the chipping will also cause damage to other parts due to silicon chips, causing leaks and short circuits.
本発明は、このような事情により威されたもので、メサ
面の欠けの発生を防止すると共に、ピンホールの少ない
メサ食刻工程によりメサ型半導体装置の製造工程を提供
することを目的とするものである。The present invention has been made under these circumstances, and an object of the present invention is to prevent the occurrence of chipping on the mesa surface and provide a manufacturing process for mesa-type semiconductor devices using a mesa etching process with fewer pinholes. It is something.
（８題を解決するための手段）
半導体基板の保有する導電型と反対の不純物を導入して
ＰＮ接合を形成する工程と、この半導体基板にマスクと
なる被膜を被覆する工程と、この被膜の所定の位置を除
去して開口を形成する工程と、マスクとして機能する被
膜の開口付近を露出させてレジスト層を被着する工程と
、露出した半導体基板をＰＮ接合に達するまで食刻する
と共にマスクとして機能する被膜の一部をσ鍔口内に突
出させる工程と、前記レジスト層を利用してｅｚマスク
として機能する被膜の突
出した部分を除去すると共に半導体基板の一部を露出し
かつ前記接合端を露出する工程と、開口を所定の深さま
で食刻しかつ露出した半導体基板の一部を丸める工程に
、本発明に係わるメサ型半導体装置の製造方法の特徴が
ある。(Means for solving the 8 problems) A process of forming a PN junction by introducing an impurity opposite to the conductivity type possessed by the semiconductor substrate, a process of coating this semiconductor substrate with a film to serve as a mask, and a process of coating this film as a mask. A process of removing a predetermined position to form an opening, a process of exposing the vicinity of the opening of the film that functions as a mask and depositing a resist layer, and etching the exposed semiconductor substrate until it reaches the PN junction and removing the mask. a step of protruding a part of the film that functions as an ez mask into the σ rim opening, and removing the protruding part of the film that functions as an ez mask using the resist layer, exposing a part of the semiconductor substrate, and removing the bonding edge. The method for manufacturing a mesa-type semiconductor device according to the present invention is characterized by the step of exposing the semiconductor substrate and the step of etching the opening to a predetermined depth and rounding the exposed part of the semiconductor substrate.
（作 用）
本発明に関するメサ型半導体装置の製造方法では、ＰＮ
接合を形成した半導体基板を酸化珪素などをマスクとす
るメサ食刻工程後、マスクを後退させてメサ面の端を露
出させて更に食刻工程を施して丸める。このマスクを後
退させるには、予めレジストパターンを形成してメサ面
の食刻工程時にマスクに発生しているピンホールを覆っ
ているので、不要な食刻を抑制する点にも有効である。(Function) In the method for manufacturing a mesa semiconductor device according to the present invention, PN
After the semiconductor substrate on which the junction has been formed is subjected to a mesa etching process using silicon oxide or the like as a mask, the mask is retreated to expose the end of the mesa surface, and a further etching process is performed to round it. In order to retract this mask, a resist pattern is formed in advance to cover pinholes generated in the mask during the etching process of the mesa surface, which is also effective in suppressing unnecessary etching.
（実施例）
第３図乃至第６図を参照して本発明に係わる一実施例を
センターゲート型Ｇ、Ｔ、Ｏにより説明する。比抵抗が
１００Ω０表面濃度が１０１３／ｃｃ程度のＮ−型のシ
リコン半導体基板１０の両表面から反対導電型のＢを７
０〜８０即導入拡散して表面濃度が約１０ ／ｃｃ
のベース領域１１を形成し、その−方を陽極として動作
させ、他方には深さ１０μｍ程度表面ａ度１０ ／
ｃｃのエミッタ領域１２・・・を形威する。この結果Ｎ
Ｐ層からなる半導体基板が構成され、エミッタ領域１２
とベース領域１１間にはＰＮ接合１３が形成され、ベー
ス領域１１にはゲート（図示せず）を設置する。エミッ
タ領域１２・・・をメサ状に形成した断面図は第１図に
明らかにしたが、センターゲート構造は、本発明に関係
がないので説明を割愛するが、以下の説明では、単一の
エミッタ領域を食刻工程により形成する例により行う。(Embodiment) An embodiment of the present invention will be described using center gate types G, T, and O with reference to FIGS. 3 to 6. B of the opposite conductivity type is applied from both surfaces of an N- type silicon semiconductor substrate 10 with a specific resistance of 100Ω and a surface concentration of about 1013/cc.
0 to 80 Immediately introduced and diffused to a surface concentration of approximately 10/cc
A base region 11 is formed, one of which operates as an anode, and the other has a surface with a depth of about 10 μm 10/10 μm.
The emitter region 12 of cc is formed. This result N
A semiconductor substrate consisting of a P layer is constructed, and an emitter region 12
A PN junction 13 is formed between the base region 11 and the base region 11, and a gate (not shown) is provided in the base region 11. A cross-sectional view of the emitter region 12 formed in a mesa shape is shown in FIG. The emitter region is formed by an etching process.
第３図にあるように半導体基板ＩＯの表面に熱酸化法ま
たはＣＶ Ｄ （Ｃｈｅｎ＋１ｃａｌ Ｖａｐｏｕｒ
Ｄｅｐｏｓｉｔｉｏｎ）法によりマスクとして機能する
酸化被膜１４を約１．２μ国被着する。次にＰＥＰ工程
工程−ジスト層を利用して所定の位置の酸化膜１４に開
口１５を形成後レジスト層を剥離する（第４図参照）０
次に第２のＰＥＰ工程工程数て新レジスト層１６を酸化
被膜１４の端部付近を除いて形成する（第５図参照）。As shown in FIG. 3, the surface of the semiconductor substrate IO is coated with a thermal oxidation method or CV
An oxide film 14 serving as a mask is deposited to a thickness of approximately 1.2 μm by a method (deposition). Next, the PEP process step - After forming an opening 15 in the oxide film 14 at a predetermined position using a resist layer, the resist layer is peeled off (see Figure 4).
Next, in a second PEP step, a new resist layer 16 is formed except for the vicinity of the ends of the oxide film 14 (see FIG. 5).
ここで、フッ硝酸系のシリコン食刻液により開口１５を
２５−〜３〇−食刻してエミッタ領域１２とベース領域
ｌ１間に形成されたＰＮ接合１３を露出してメサ面を形
成するが、被食刻物の食刻速度差により酸化被膜１４が
開口１５内に張出す形となる（第６図参照）。Here, the opening 15 is etched 25 to 30 times using a fluoro-nitric acid based silicon etching solution to expose the PN junction 13 formed between the emitter region 12 and the base region l1 and form a mesa surface. The oxide film 14 protrudes into the opening 15 due to the difference in etching speed of the material to be etched (see FIG. 6).
更に、 ＮＨ，により酸化被膜１４をレジストＭ１６を
マスクとして再び食刻して張出部分を除去してエミッタ
領域１２の角部Ａを露出させ（この工程後は第２図と同
様なので割愛する）、更に、フッ硝酸系のシリコン食刻
液を用いて角部Ａを含むメサ面を約１μｍ除去する第２
の食刻を行う（第７図参照）。このように、第２のＰＥ
Ｐ工程工程数置した新しジストＭＪ１６は、メサの端が
露出するように内側の位置に予め設計する。Furthermore, the oxide film 14 is etched again with NH using the resist M16 as a mask to remove the overhanging portion and expose the corner A of the emitter region 12 (the steps after this step are the same as those in FIG. 2, so they are omitted). Then, a second process was performed in which approximately 1 μm of the mesa surface including the corner A was removed using a fluoro-nitric acid silicone etching solution.
(See Figure 7). In this way, the second PE
The new resist MJ16, which has been installed several times in the P process, is designed in advance at an inner position so that the end of the mesa is exposed.
また、第２の食刻工程は深さ１μｍ程度と浅いので、食
刻速度の遅いものが適当であり、また食刻マスクの酸化
被膜１４が実質的に食刻されない方が良い。この等方性
食刻手段にＣＤＥ方式［マグネトロン管により発生させ
たプラズマから離れた場所に移した基（ラジカルＲａｄ
ｉｃａｌ）によりほぼ等方性食刻する方式コを利用する
と上記の要求を十分溝たすことになる。Further, since the second etching step is shallow, about 1 μm in depth, a slow etching speed is appropriate, and it is better that the oxide film 14 of the etching mask is not substantially etched. This isotropic etching means uses the CDE method [radical
Using a method of substantially isotropic etching with ical) satisfies the above requirements.
なお、Ｇ、Ｔ、Ｏ用のメサ構造として完成させるには、
第２図に示すように、突出したＰＮ接合を覆う酸化物層
にパッシベイション（Ｐａ５ｓｉｖ−ａｔｉｏｎ）層と
してポリイミド層を重ねて配置し、ここに設置した開口
を介してゲート用電極を設置する。また、突出したメサ
部の頂面にはこの酸化物層とポリイミド層を延長させ、
その大部分を除去して得られる窓にＡｌ１またはＡＱ金
合金Ａｌ２−３ｉ−Ｃｕ、 ＡＱ−８ｉなど）を堆積
してエミッタ電極を形成する。In addition, to complete the mesa structure for G, T, and O,
As shown in Figure 2, a polyimide layer is placed on top of the oxide layer covering the protruding PN junction as a passivation layer, and a gate electrode is placed through the opening provided here. . In addition, this oxide layer and polyimide layer are extended on the top surface of the protruding mesa part,
Most of the metal is removed and an emitter electrode is formed by depositing Al1 or an AQ gold alloy (Al2-3i-Cu, AQ-8i, etc.) in the window obtained.
この突出部の高さは約３０−に形成し、 Ｎ−型シリコ
ン半導体基板表面から導入拡散する不純物としてはＢや
Ｇａが利用でき、エミッタ領域用不純物は通常Ｐを使用
する。The height of this protruding portion is formed to be about 30 cm. B or Ga can be used as the impurity introduced and diffused from the surface of the N- type silicon semiconductor substrate, and P is usually used as the impurity for the emitter region.
また、上記実施例では、半導体基板の材質をシリコン単
結晶としたが、Ｇ ａ Ａ ｓなどの■−■族化合物か
らなる半導体基板、も使用できることを付記する。Further, in the above embodiments, the material of the semiconductor substrate is silicon single crystal, but it should be noted that a semiconductor substrate made of a ■-■ group compound such as GaAs can also be used.
このように、本発明による製造方法では、メサ端の欠け
が減少する外に、二回のＰＥＰ工程によりレジスト層が
重ねられマスクとして機能する酸化被膜には、ピンホー
ルの形成される頻度が減少するので、半導体素子のいわ
ゆるフィールド被膜としても機能する際にリーク電流を
極端に減らすことが可能になった。即ち、従来の製造方
法では、リーク不良率が約２５％であったものが、本発
明では僅か５％以下に減少した。As described above, in the manufacturing method according to the present invention, not only the chipping at the mesa edge is reduced, but also the frequency of pinholes being formed in the oxide film that is overlapped with the resist layer and functioning as a mask by the two-time PEP process is reduced. Therefore, it has become possible to drastically reduce leakage current when it also functions as a so-called field coating for semiconductor devices. That is, in the conventional manufacturing method, the leak failure rate was about 25%, but in the present invention, it was reduced to only 5% or less.
更にピンホールの発生に伴う配線や電極における短絡事
故発生率は従来はぼ１５％であったものが、本発明方法
によると２％以下となり結果的には、半導体素子の信頼
性の向上をもたらすものである。Furthermore, the incidence of short-circuit accidents in wiring and electrodes due to the occurrence of pinholes was approximately 15% in the past, but with the method of the present invention, this has been reduced to less than 2%, resulting in improved reliability of semiconductor devices. It is something.
第１図はセンターゲート方式Ｇ、Ｔ、Ｏのメサ状カソー
ド領域の断面図、第２図はその製造工程を示す断面図、
第３図乃至第６図は本発明に係わる一実施例の製造工程
を示す断面図である。
１０：Ｎ型半導体基板、 １１：ベース領域、１２：
エミッタ領域、 １３：ＰＮ接合。
１４：酸化被膜、 １５：開口、１６：レジス
ト、 Ａ：角部。
第
１
図
第
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図FIG. 1 is a cross-sectional view of the mesa-shaped cathode region of the center gate type G, T, and O, and FIG. 2 is a cross-sectional view showing the manufacturing process thereof.
3 to 6 are cross-sectional views showing the manufacturing process of one embodiment of the present invention. 10: N-type semiconductor substrate, 11: base region, 12:
Emitter region, 13: PN junction. 14: Oxide film, 15: Opening, 16: Resist, A: Corner. Fig. 1 Fig. Fig. Fig. Fig. Fig. 1
Claims (1)
ＰＮ接合を形成する工程と、この半導体基板にマスクと
なる被膜を被覆する工程と、この被膜の所定の位置を除
去して開口を形成する工程と、マスクとして機能する被
膜の開口付近を露出させてレジスト層を被着する工程と
、露出した半導体基板をＰＮ接合に達するまで食刻して
マスクとして機能する被膜の一部を開口内に突出させる
工程と、前記レジスト層を利用してマスクとして機能す
る被膜の突出した部分を除去すると共にこれに対応する
半導体基板の一部を露出しかつ接合端を露出する工程と
、開口を所定の深さまで食刻しかつ露出した半導体基板
の一部を丸める工程を含むことを特徴とするメサ型半導
体装置の製造方法。A step of forming a PN junction by introducing an impurity opposite to the conductivity type possessed by the semiconductor substrate, a step of coating this semiconductor substrate with a film that serves as a mask, and a step of removing a predetermined position of this film to form an opening. a process of exposing the vicinity of the opening of the film that functions as a mask and depositing a resist layer; and a process of etching the exposed semiconductor substrate until it reaches the PN junction and etching a part of the film that functions as a mask into the opening. a step of removing the protruding portion of the film functioning as a mask using the resist layer, exposing a corresponding part of the semiconductor substrate and exposing the bonding edge, and forming an opening in a predetermined manner. 1. A method for manufacturing a mesa-type semiconductor device, comprising the steps of etching the semiconductor substrate to a depth of .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17623889A JPH0340469A (en) | 1989-07-07 | 1989-07-07 | Manufacture of mesa type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17623889A JPH0340469A (en) | 1989-07-07 | 1989-07-07 | Manufacture of mesa type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0340469A true JPH0340469A (en) | 1991-02-21 |
Family
ID=16010055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17623889A Pending JPH0340469A (en) | 1989-07-07 | 1989-07-07 | Manufacture of mesa type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0340469A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017103336A (en) * | 2015-12-01 | 2017-06-08 | 株式会社東芝 | Manufacturing method and manufacturing apparatus of semiconductor device |
-
1989
- 1989-07-07 JP JP17623889A patent/JPH0340469A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017103336A (en) * | 2015-12-01 | 2017-06-08 | 株式会社東芝 | Manufacturing method and manufacturing apparatus of semiconductor device |
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