JPS5830170A - Compound semiconductor element and forming method of its electrode - Google Patents

Compound semiconductor element and forming method of its electrode

Info

Publication number
JPS5830170A
JPS5830170A JP56127331A JP12733181A JPS5830170A JP S5830170 A JPS5830170 A JP S5830170A JP 56127331 A JP56127331 A JP 56127331A JP 12733181 A JP12733181 A JP 12733181A JP S5830170 A JPS5830170 A JP S5830170A
Authority
JP
Japan
Prior art keywords
layer
electrode
compound semiconductor
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56127331A
Other languages
Japanese (ja)
Inventor
Masaaki Sakata
雅昭 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stanley Electric Co Ltd
Original Assignee
Stanley Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stanley Electric Co Ltd filed Critical Stanley Electric Co Ltd
Priority to JP56127331A priority Critical patent/JPS5830170A/en
Publication of JPS5830170A publication Critical patent/JPS5830170A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To obtain the electrode with good reproducibility, when the electrode is provided in the compound semiconductor including Al, by forming the three layer structure of the electrode comprising a Ti layer which is provided on the substrate, a layer including a metal which is ohmic-contacted with the Ti layer, and an Au layer. CONSTITUTION:On the P type GaAs substrate 1, a P type GaAlAs region 2 and an N type GaAlAs region 3 are laminated and grown by a liquid phase epitaxial growth. The Ti layer 7 which is to become a protecting film at the time of chemical etching, the mixed metal layer 8 of Ge and Ni which is excellently ohmic-contacted by the diffusion at the later heat treatment, and the Au layer 9 which is readily bonded to lead wire are laminated and deposited on the layer 3. Then a heat sensitive film 10 having a fine pattern is provided on a layer 9. At first, the exposed part of the layer 9 is etched away, then the layer 8 is etched away by using a mixed liquid of KI-I2. Thereafter, the layer 7 is plasma- etched by using a gas such as CF4, the film 10 is removed, and an electrode 5 such as Au-Zn is deposited on the back surface of the substrate 1. Thereafter, the heat treatment is performed. Thus the electrode having the excellent three layer structure is obtained on the surface of the substrate 1.

Description

【発明の詳細な説明】 本発明はアル(=ラムを含む化金物半導体素子およびこ
の素子の電極形成法に係り、とくにktを含む化合物半
導体素子の選択的な領域に電極を形成する方法Kllす
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a compound semiconductor device containing Al(=Ram) and a method for forming electrodes of this device, and particularly relates to a method for forming electrodes in selective regions of a compound semiconductor device containing kt. It is something.

周知のように発光ダイオード、トランジスタ、レーザー
、光検出器などの素子には、GaAs、GaAtAs 
、 GaAsPm GaP或いはCd8. ZmS  
などの化合物半導体材料が使用されており、その半導体
材料の応用分野も増々広がってきているのが現状である
As is well known, elements such as light emitting diodes, transistors, lasers, and photodetectors use GaAs and GaAtAs.
, GaAsPm GaP or Cd8. ZmS
Currently, compound semiconductor materials such as the following are being used, and the fields of application of these semiconductor materials are expanding rapidly.

これらの化合物半導体材料は、単元素の半導体材料であ
る81などに比し、物理的性質が素子製作遇1で複雑に
変化すゐ丸め、電極形成の方法を含めて素子製作工S%
単純ではなく高変の技術を要する場合が多い。とくにG
aAtAsK代表されるようなklを含む化合物半導体
材料においては、牛導体表間が不安定で製作工寝中の熱
処理や化学処理の段階で変化しやすく、オー建ツク接触
の九めの電極形成が行ないにくいなどの欠点を有してい
丸。従って、他の化合物半導体の場合本そうであるが、
とくにAtを含む化合物半導体材料を用いた素子の電極
形成には種々の材料、技術、方法が開発されている。し
かしながらなお工程が複雑であるとか、性能、歩留シな
どに問題点が多く残っているのが現状である。この従来
法の電極形成法の欠点、問題点をGaAtAs発光ダイ
オードの電極形成法を例にとって具体的に説−する。
Compared to single-element semiconductor materials such as 81, these compound semiconductor materials have physical properties that change in a complicated manner depending on the device manufacturing process1, and the device manufacturing process, including the method of electrode formation, is difficult.
It is not simple and often requires highly variable techniques. Especially G
In compound semiconductor materials containing Kl, such as aAtAsK, the surface of the conductor is unstable and easily changes during heat treatment and chemical treatment during manufacturing, making it difficult to form the ninth electrode in contact with the metal. It has drawbacks such as being difficult to carry out. Therefore, as is the case with other compound semiconductors,
In particular, various materials, techniques, and methods have been developed for forming electrodes of devices using compound semiconductor materials containing At. However, the current situation is that the process is complicated, and many problems remain in terms of performance, yield, etc. The disadvantages and problems of this conventional method for forming electrodes will be specifically explained using a method for forming electrodes of a GaAtAs light emitting diode as an example.

第1図闇は従来のGaAtAs発光ダイオードの断面構
造の一例である。この図において社、ダイオードはp 
ill GaAtAm結晶基板1の上に液相成長法など
で得られたpHlGaAtAs領域2、n @ GaA
tAs領域3が積層されたpm接合となっている。素子
の電極としては裏面の全面にオーミック電極5が、まえ
表面にはStO,などの絶縁膜6に所定の形状、大きさ
を4つ窓があけられ選劉的にオーミック電極4が形成さ
れている。
The dark side in FIG. 1 is an example of a cross-sectional structure of a conventional GaAtAs light emitting diode. In this diagram, the diode is p
pHlGaAtAs region 2,n@GaA obtained by liquid phase growth method etc. on ill GaAtAm crystal substrate 1
The tAs region 3 is stacked to form a pm junction. As the electrodes of the element, an ohmic electrode 5 is formed on the entire back surface, and on the front surface, four windows of a predetermined shape and size are formed in an insulating film 6 such as StO, and ohmic electrodes 4 are selectively formed. There is.

このような電極構造は通常次のような方法によって得ら
れる。即ち、pnii合が形成された基板の全面に81
0.などの絶縁膜6をCV D (ch@m1aalv
apor d@pe畠1tlom )法などで付着被覆
する。
Such an electrode structure is usually obtained by the following method. That is, 81
0. CV D (ch@m1aalv
Adhesive coating is performed using the apor d@pehatake1tlom method or the like.

しかる螢、この絶縁lI6に感光膜を塗布し通常の写真
蝕刻法によって所定の形状、サイズをもつ電極形成用の
窓をあける。その後電極用金属を真空蒸着法などKより
全面蒸着し、再び感光膜塗布。
Then, a photoresist film is applied to the insulating film 6, and a window having a predetermined shape and size for forming an electrode is formed by a conventional photolithography method. After that, the metal for the electrode is deposited on the entire surface using K using the vacuum evaporation method, and then the photoresist film is applied again.

写真蝕刻法によって電極領域4をマスクして化学エツチ
ングなどの処理によって第1図(a)の断面構造を得る
。裏面のオーミック電極は全面に形成されるので上記の
ような工1は不要である。これらに電極のGa AtA
−結晶への付着力、安定性、オーミック接触性を高める
ためO熱処理工程がつけ加わるOが普通である。
The electrode region 4 is masked by photolithography, and the cross-sectional structure shown in FIG. 1(a) is obtained by processing such as chemical etching. Since the ohmic electrode on the back surface is formed on the entire surface, Step 1 as described above is not necessary. These electrodes are made of GaAtA.
- O is usually added with an O heat treatment process to improve adhesion to the crystal, stability, and ohmic contact.

このような従来の電極形成法における欠点、問題点を列
挙すると次のようなものである。
The drawbacks and problems of such conventional electrode forming methods are listed below.

イ)  81(hなどの絶縁IR6はCVD法などの熱
的過程での形成によるので、熱的歪および結晶との物理
的性質の違いがかなシある仁とによる応力歪が結晶との
境界面に発生し中すい。とくに窓周辺部においては結晶
、絶縁物、オーミック電極金属とが互いKm触すること
となり複鯵な歪が発生する。これらの不必要な歪は、と
くに歪に対して敏感な化合物半導体結晶からなる素子の
特性に悪影響を及ぼし、歩留り、寿命等の信頼性が低下
してい友。
b) Insulation IR6 such as 81(h) is formed by a thermal process such as CVD, so there may be slight differences in thermal strain and physical properties with the crystal. Especially around the window, crystals, insulators, and ohmic electrode metal come into contact with each other, causing multiple strains.These unnecessary strains are particularly sensitive to strain. This adversely affects the characteristics of devices made of compound semiconductor crystals, reducing reliability such as yield and lifespan.

口) 選択的なオー電ツク電極形成のための絶縁膜の窓
あけは薬品を用いた化学的処理によってなされる。絶縁
膜を溶解し結晶を溶解しない薬品で6つ九としてもムt
を含む結晶の場合には薬品に触れ丸窓の中の結晶表面は
活性化されやすく、ま九酸化されやすい性質がある九め
、後のオーミック電極が付着形成されても接触抵抗が大
きくなったりバラついたシしゃすく、良好なオーミック
接触がとれにくいといった結果を生じていた。
(1) Opening windows in the insulating film for selectively forming electrical electrodes is done by chemical treatment using chemicals. Chemicals that dissolve the insulating film but do not dissolve the crystals are useless.
In the case of a crystal containing a chemical, the crystal surface inside the round window is easily activated and easily oxidized, and even if an ohmic electrode is attached and formed later, the contact resistance may become large. This resulted in uneven contact and difficulty in establishing good ohmic contact.

ハ)この化合物半導体素子が発光ダイオードであつ友場
金上部が光取出し面となる。従って発光面積に対する電
極面積の占める割合は効率などダイオードの発光特性を
左右するものとなるから電極面積は可能な限シ小さくか
つ形状、サイズの精度の良いことが要求される。これを
いい換えれば、電極4の窓からはみだし絶縁膜6の上を
覆っている領域部分は不必要というよシ問題となる領域
である。写真蝕刻法によってこのはみだし部分を極力な
くすようなマスクパターンを用い化学エツチングをした
場合、マスク合せfll&およびずれ、サイドエツチン
グ現象、貴意性などが関係しパターンがずれエツチング
液が窓の端部の方で結晶に達する場合が往々にして存在
していた。電極(たとえば金)などの化学エツチング液
けAtを含む化合物中導体なども容易にエツチングする
ため素子特性や歩留)が低下すゐ場合が多かっ九。
c) When this compound semiconductor element is a light emitting diode, the upper part of the metal becomes a light extraction surface. Therefore, since the ratio of the electrode area to the light emitting area affects the light emitting characteristics of the diode such as efficiency, the electrode area is required to be as small as possible and to have good precision in shape and size. In other words, the area protruding from the window of the electrode 4 and covering the insulating film 6 is unnecessary and is a problematic area. When chemical etching is performed using a mask pattern that minimizes this protruding part by photo-etching, mask alignment, misalignment, side etching phenomenon, etching sensitivity, etc. are involved, causing the pattern to shift and the etching solution to move toward the edge of the window. There were often cases where crystals were reached. Chemical etching solutions such as electrodes (for example, gold) also easily etch conductors in compounds containing At, resulting in deterioration in device characteristics and yield.

二)素子上部の電極形成の丸めの工程数は、上記した種
々の欠点ないし問題点があるに屯拘らず一比較的多いの
で素子の;スト高につながっていた。
2) The number of rounding steps for forming electrodes on the upper part of the device is relatively large, despite the various drawbacks and problems mentioned above, which leads to an increase in the strike height of the device.

また別な方法として次に示すような簡単な方法で発光ダ
イオードの電極を形成する方法もある。
Another method is to form the electrodes of the light emitting diode using a simple method as shown below.

第1図(b)がそれKよって得られ九発光ダイオードの
断面構造例である。各領域1.2,5.4は第1図(a
) Kおける各領域1〜4と同じである。第1図(b)
 K示した構造においては形状のみを考えれば絶Il&
膜がなく発光ダイオードとしては好都合な構造である。
FIG. 1(b) is an example of the cross-sectional structure of a nine-light emitting diode obtained by this method. Each area 1.2, 5.4 is shown in Figure 1 (a
) Same as each area 1 to 4 in K. Figure 1(b)
In the structure shown, if only the shape is considered, it is impossible to
It has no film and has a convenient structure as a light emitting diode.

これを得ゐ九めには、上面に電極金属を全面に付着させ
写真蝕刻法および化学エツチングによって電極4を残そ
うとして本前述し九ようKl極金IIOエツチング液は
Atを含む化合物半導体をもエツチングしてしオうので
用いられず、金属マスクを用いる。すなわち、  Mo
などの金属薄板に所定の形状の孔をあけたものをマスク
とし、これを半導体基板に密着させた状態でその上部か
ら電極用金属を真空蒸着法などの方法で蒸着させ第1図
(b)のような構造の素子を得るのである。
To obtain this, in order to leave the electrode 4 by depositing the electrode metal on the entire surface of the upper surface by photolithography and chemical etching, the Kl electrode metal IIO etching solution also contains At-containing compound semiconductors as described above. Since it is etched, it is not used, and a metal mask is used. That is, Mo
A mask is made of a thin metal plate with holes of a predetermined shape, and with this mask in close contact with the semiconductor substrate, electrode metal is deposited from above using a method such as vacuum evaporation, as shown in Figure 1(b). This results in an element with a structure like this.

この方法はWjI的には簡単なのであるが、中はり次の
ような欠点が存在していた。
Although this method is simple in WJI terms, it has the following drawbacks.

金属板マスクにおける孔の加工には限界があって黴細な
形状、サイズの孔は作れず、従って写真蝕刻法などでは
可能な精度の良い形状、サイズをもつ電極は得られない
のである。またマスクラ半導体基板に密着させるといっ
て奄重ね合わせるわけであるから、どうしてもある程度
の間隙を生じ、しかも蒸着時におけるマスクの熱膨張、
振動等があって、蒸着した電極領域4端部においてずれ
やぼけが生じやすく電極O形状、サイズの再現性に乏し
くなるのである。
There is a limit to the processing of holes in a metal plate mask, and holes with a fine shape and size cannot be made, so it is not possible to obtain electrodes with the precise shape and size that is possible with photolithography. In addition, since the mask layer is placed in close contact with the semiconductor substrate, it is overlapped with each other, so a certain amount of gap inevitably occurs, and thermal expansion of the mask during vapor deposition occurs.
Due to vibrations and the like, shifts and blurring tend to occur at the ends of the deposited electrode region 4, resulting in poor reproducibility of the shape and size of the electrode O.

このように従来の電極形成法には種々の問題点かあシ、
素子製作上の性能、精度、歩留シ、再現性に大きな障害
となっていた。
As described above, there are various problems with conventional electrode formation methods.
This was a major obstacle to performance, precision, yield, and reproducibility in device manufacturing.

本発明は上記の諸欠点、問題点を鱗決或いは回避すると
とKよって、ムtを含む化合物半導体素子およびこの半
導体素子に精度良くかつ再現性の良い電極を選択的に形
成する方法を提供することを目的とするものである。
The present invention aims to eliminate or avoid the above-mentioned drawbacks and problems, and therefore provides a compound semiconductor device containing Mut and a method for selectively forming electrodes on this semiconductor device with high precision and good reproducibility. The purpose is to

以下、本発明に係るGaAjA−発光ダイオードの電極
形成法を実施例によシ詳細Kl!明する。
Hereinafter, the method for forming electrodes of a GaAjA-light emitting diode according to the present invention will be explained in detail using examples. I will clarify.

第2図(a) 〜(f)は本発11によるGaAt&@
発光ダイオードの電極形成の丸めの工程例である。
Figure 2 (a) to (f) are GaAt&@ by this invention 11.
This is an example of a rounding process for forming electrodes of a light emitting diode.

(a)  第2図(a) KはpHGaAzA−結晶基
板1の上に液相成長法などkよりてpillGaAtム
ー領域2及びn 31 GaAjAs領域6が形成され
たpn接合を有する半導体基板を示しである。
(a) FIG. 2 (a) K indicates a semiconductor substrate having a pn junction in which a pill GaAt mu region 2 and an n 31 GaAjAs region 6 are formed on a pHGaAzA-crystal substrate 1 by a liquid phase growth method or the like. be.

(b)  これに対しn ml GaAjAs領域6の
全面に3層からなる金属層を真空蒸着法あるいはスパッ
タリングなどの方法で付着させる(第2図(b)参照)
(b) On the other hand, a metal layer consisting of three layers is deposited on the entire surface of the n ml GaAjAs region 6 by a method such as vacuum evaporation or sputtering (see FIG. 2(b)).
.

壕ず第1層7はTI金層薄膜である。この層は次に述べ
る化学エツチングの際の保護膜として用いられるものな
ので且つ半導体との境界面に歪を発生させないよう可能
な限り薄いことが望ましい。
The trench first layer 7 is a TI gold layer thin film. This layer is used as a protective film during the chemical etching described below, and is preferably as thin as possible so as not to cause strain at the interface with the semiconductor.

実験の結果平均数百〜数千Aの厚みがあれば充分であり
、l 1m以上の厚みは歪あ纂いは第2層8の金属によ
るオー建ツク形成効果の点から反って障害となることが
判った。この第1層7の上KG・およびNlの混合金属
からなる薄い金属層を第2層8として全面に付着させる
。この第2層8はn型GaAtAs領域3に対しオーミ
ック接触が得られるGoが含まれており螢の熱処理過程
で第1層7およびn型GaAtAs表面に拡散して良好
なオーミック接触を形成させる役目を果す。この際Ni
はポールアンプを押さえる役目をなす。この目的さえ果
せればとのG・、Nlといった混合金属でなくともよい
。上記と同様に歪の点から厚みは数百〜数千Aあれば充
分でl 1m以上の厚みは反って障害となる。なおjl
lK形成される第3層9に用いられる金属はAt+であ
る。ム1を用いる理由はり一ドIIOポンディングなど
11OリードIIO取出しを容易にするためである。そ
0*+は数7wff1あれば充分である。
As a result of experiments, a thickness of several hundred to several thousand amps on average is sufficient, and a thickness of 1 m or more causes distortion or warping due to the effect of forming an oval structure by the metal of the second layer 8, which may cause problems. It turned out that. On this first layer 7, a thin metal layer made of a mixed metal of KG and Nl is deposited as a second layer 8 over the entire surface. This second layer 8 contains Go, which provides ohmic contact with the n-type GaAtAs region 3, and serves to diffuse into the first layer 7 and the n-type GaAtAs surface during the heat treatment process to form a good ohmic contact. fulfill. At this time, Ni
serves to hold down the pole amplifier. It is not necessary to use mixed metals such as G and Nl as long as this purpose can be achieved. Similarly to the above, from the viewpoint of distortion, a thickness of several hundred to several thousand amps is sufficient, and a thickness of 1 m or more will warp and cause trouble. In addition, jl
The metal used for the third layer 9 formed is At+. The reason why the system 1 is used is to facilitate the extraction of the 11O lead IIO, such as by one lead IIO bonding. The number 7wff1 is sufficient for so0*+.

このように本発明においてはそれぞれ作用効果の異なる
金属薄層が3層積層される電極金属構成になっているの
がlIligIである。しかしながらその3層は薄膜で
あること、また、後で熱処理することなどから実際的に
は亙いの境界面は明確ではないと考えられる。またこの
3層は、蒸着源を変えるとかスパッタリングの放電電極
を変えるなどの方法をとれば同一容器内で同一工程で得
ることができる。
As described above, in the present invention, lIligI has an electrode metal structure in which three thin metal layers each having a different function and effect are laminated. However, since the three layers are thin films and are heat-treated later, it is considered that the boundaries between the three layers are not clear in practice. Moreover, these three layers can be obtained in the same container and in the same process by changing the vapor deposition source or changing the sputtering discharge electrode.

(c)  このAtKからなる第3層9上に感光膜を塗
布し通常の写真蝕刻法によ)所定の形状、サイズをもつ
感光膜10を残す(第2図(C)参照)。写真蝕刻法を
用いることにより極めて微細で精整なパターンをもつ感
光膜10が形成される。
(c) A photoresist film is coated on the third layer 9 made of AtK and a photoresist film 10 having a predetermined shape and size is left (see FIG. 2(C)). By using the photolithography method, a photoresist film 10 having an extremely fine and precise pattern is formed.

(d)  次にKl −I、混合液などの化学エツチン
グ液に上記工程を経た基板を浸漬する。感光膜10のあ
る部分を残してエツチングが進むが、この混合液FiT
lからなる第1層7をエツチングするがエツチング速度
が違いのて第2層8tでエツチングされるとエツチング
が停止する。この工sllの断面図を第2図(d)に示
した。
(d) Next, the substrate that has undergone the above steps is immersed in a chemical etching solution such as Kl-I or a mixed solution. Etching proceeds leaving a certain part of the photoresist film 10, but this mixed solution FiT
The first layer 7 consisting of 1 is etched, but due to the difference in etching speed, the etching stops when the second layer 8t is etched. A cross-sectional view of this SLL is shown in FIG. 2(d).

(・)上記工程を終つぇ基板を感光膜1oを残存きせ九
ままで、容器内に入れCF4あるいはCP’、十〇1な
どのガスを導入してプラズマエツチングを行う。この方
法をとれば感光膜1oが存在する部分を残して第1層7
であるTi膜がプラズマエツチングされGaAtA−結
晶面に運し六段階でエツチングが停止する。
(-) After completing the above steps, the substrate is placed in a container with the photoresist film 1o remaining intact, and a gas such as CF4, CP', or 101 is introduced to perform plasma etching. If this method is used, the first layer 7 is
The Ti film is plasma-etched and transferred to the GaAtA-crystal plane, and the etching stops at the sixth stage.

本発明のように化学エツチング(d)とプラズマエツチ
ング(@ンとを併用することにょシサイドエッチングが
殆どなく初めの感光1110の形状、サイズ通りの電極
領域を残して他の不必要な領域の三種類の金属層が除去
されることになるのである。
By using a combination of chemical etching (d) and plasma etching (@) as in the present invention, there is almost no side etching, leaving the electrode area according to the shape and size of the initial photosensitive layer 1110, and removing other unnecessary areas. Three types of metal layers will be removed.

(fl  次KJl光1110 を除去Lllfiop
型GaAtAs結晶基板1にオー建ツク電極金属(例え
ばAu −Zn、Au −B・など)を付着させN、或
いは均ガスなどの雰囲気ガス中で約400〜5oocの
温度で熱処理する。この熱処理によってn1ll、p型
いずれのGaAlAs結晶に対しても再現性のよ−良好
なオーミンク接触が安定して得も、れるのである。
(fl Next KJl light 1110 removed Lllfiop
An oak electrode metal (for example, Au--Zn, Au--B, etc.) is attached to the type GaAtAs crystal substrate 1 and heat-treated at a temperature of about 400 to 50 oC in an atmospheric gas such as N or homogeneous gas. By this heat treatment, it is possible to stably obtain ohmink contact with good reproducibility for both n1ll and p-type GaAlAs crystals.

以上、本発明をGaAtAs発光ダイオードの電極形成
法を実施例として述べた。本発明によってGaAtAs
結晶などAtを含む化合物半導体基板上に、化合物半導
体結晶に接する儒K Tl薄膜を配してしか4とのTl
薄膜とAu薄膜とでオーインク接触を可能ならしめる金
属を含んだ薄膜をサンドイッチ状に挾んだ3層構造の電
極膜を全面に形成する方法と、写真蝕刻法を用込九化学
エツチングJ:、 7”) X マエッチングとを併用
する方法をとることによって、化学エツチングをTi膜
で停止させて化学薬品がAtを含む化合物半導体に接触
させない方法をとることができ(従ってklを含む化合
物半導体表面の活性化、酸化が避けられオーミック接触
も良くなルミ極の形成工種の再現性が向上する)、Ti
膜をプラズマエツチングで除去することによりGaAt
Am結晶を侵蝕することなく、ま良すイドエツチング本
なりので極めて微細な形状、サイズの電極でも高精度で
、再現性よく得られるのである。まえ本発明にあっては
、第1図(a)の説明で述べたような絶縁膜の形成を行
なわないため、工種が簡単となり絶縁膜形成時の熱的歪
や物理的性質の違いから来る応力歪を半導体素子に与え
ないですむのである。上記実施例はGaAtAs結晶を
基板とするものであったが、化合物半導体の中にAtが
含まれていると、既述したように化学薬品に対し結晶表
面の性質が敏感になるので、Atを含む化合物半導体に
本発明は充分な効果を発揮する。上記実施例はm fi
l GaAtAs結晶に対する選択的な電極形成法とし
て述べているが、表面側がp[GaAtA−の場合には
、3層構造の電極の真中の層にオーインク接触が形成で
きる。例えばAu −Zn、Au−Be薄層であれば良
く場合によってはTi層とAu−Zn等の層(tたFi
Au −Ba層)の2層構造であれば同様な効果が達成
できゐ。
The present invention has been described above using a method for forming electrodes of a GaAtAs light emitting diode as an example. According to the present invention, GaAtAs
Only by disposing a Tl thin film in contact with the compound semiconductor crystal on a compound semiconductor substrate containing At, such as a crystal, can Tl with 4.
A method of forming an electrode film with a three-layer structure on the entire surface in which a thin film containing a metal that enables O-ink contact between a thin film and an Au thin film is sandwiched, and a photo-etching method is used. 7") By using a method in combination with X-ma etching, it is possible to stop the chemical etching at the Ti film and prevent the chemical agent from coming into contact with the compound semiconductor containing At (therefore, the surface of the compound semiconductor containing Kl can be taken). Activation and oxidation are avoided and ohmic contact is also improved, improving the reproducibility of the forming process of the lumin electrode), Ti
By removing the film by plasma etching, GaAt
Since it is an ideal etching method that does not corrode the Am crystal, even electrodes with extremely fine shapes and sizes can be obtained with high precision and good reproducibility. First, in the present invention, since the insulating film is not formed as described in the explanation of FIG. There is no need to apply stress strain to the semiconductor element. The above embodiment used GaAtAs crystal as the substrate, but if At is contained in the compound semiconductor, the crystal surface becomes sensitive to chemicals as mentioned above, so At is not used as the substrate. The present invention exhibits sufficient effects on compound semiconductors containing The above embodiment is m fi
Although this is described as a selective electrode formation method for a GaAtAs crystal, when the surface side is p[GaAtA-, an O-ink contact can be formed in the middle layer of a three-layer electrode. For example, a thin layer of Au-Zn or Au-Be may be sufficient.
A similar effect can be achieved with a two-layer structure (Au--Ba layer).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(1)は、従来法によるGaAtA−発光ダイオ
ードの断面図、第1図(b)は、従来法である金属マス
クを用いて得られるGaAtAs発光ダイオードの断面
図。 第2図(a) 〜(f)は、本発W#によるGmAtA
s発光ダイオードの電極形成1根を示す図である。 1− p ill GaAtA−結晶基板; 2 =・
p fil GaAtAs領域; 3− !I I# 
GaAtAa II斌; 7−・・第1層; 8 、、
。 第2層;9・・・第3層;10・・・感光膜。 特許出願人:スタンレー電気株式会社 代理人:弁理士海津保三 同   :弁理士 平 山 −幸 第2図
FIG. 1(1) is a cross-sectional view of a GaAtA light-emitting diode obtained by a conventional method, and FIG. 1(b) is a cross-sectional view of a GaAtAs light-emitting diode obtained by a conventional method using a metal mask. Figures 2(a) to (f) show GmAtA using the original W#.
FIG. 2 is a diagram showing one base of electrode formation of a light emitting diode. 1-pill GaAtA-crystal substrate; 2 =・
p fil GaAtAs region; 3-! I I#
GaAtAa II; 7-...first layer; 8,,
. 2nd layer; 9...Third layer; 10...Photosensitive film. Patent applicant: Stanley Electric Co., Ltd. Agent: Patent attorney Yasushi Kaizu: Patent attorney Hirayama - Sachi Figure 2

Claims (1)

【特許請求の範囲】 1)  klを含む化合物半導体の電極の金属層として
、上記化合物半導体に接する何に11層を配し、該T1
層と、オー建ツク接触を可能ならしめる金属を含む層と
、Au層との実質的に3層構造になされていることを特
徴とするAtを含む化金物半導体素子。 2)  ktを含む化合物半導体の電極の金属層として
、上記化合物半導体に接する側にTIを形成ししかる後
にオー建ツク接触を可能ならしめる金属を含む層を形成
しさらにAm層を形成し、以て実質的に3層構造とする
とともに、上記電極を所定の形状に加工する処理工程と
して化学エツチングを行い、しかる螢にプラズマエツチ
ングを行うことを特徴とするklを含む化合物半導体の
電極形成法。
[Scope of Claims] 1) As a metal layer of the electrode of the compound semiconductor containing kl, 11 layers are disposed on anything in contact with the compound semiconductor, and the T1
What is claimed is: 1. A metal compound semiconductor device containing At, which has a substantially three-layer structure consisting of an Au layer, an Au layer, a layer containing a metal that enables an over-the-wall contact, and an Au layer. 2) As a metal layer of the electrode of the compound semiconductor containing kt, TI is formed on the side in contact with the compound semiconductor, and then a layer containing a metal that enables an over-the-wall contact is formed, and an Am layer is further formed, and the following steps are carried out. A method for forming an electrode of a compound semiconductor containing kl, characterized in that the electrode is formed into a substantially three-layer structure, chemical etching is performed as a treatment step for processing the electrode into a predetermined shape, and then plasma etching is performed.
JP56127331A 1981-08-15 1981-08-15 Compound semiconductor element and forming method of its electrode Pending JPS5830170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56127331A JPS5830170A (en) 1981-08-15 1981-08-15 Compound semiconductor element and forming method of its electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56127331A JPS5830170A (en) 1981-08-15 1981-08-15 Compound semiconductor element and forming method of its electrode

Publications (1)

Publication Number Publication Date
JPS5830170A true JPS5830170A (en) 1983-02-22

Family

ID=14957272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56127331A Pending JPS5830170A (en) 1981-08-15 1981-08-15 Compound semiconductor element and forming method of its electrode

Country Status (1)

Country Link
JP (1) JPS5830170A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220967A (en) * 1983-05-21 1984-12-12 テレフンケン・エレクトロニク・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Alloy electrode for n-type conductive gaalas semiconductor material with high aluminum content
JPS61131480A (en) * 1984-11-29 1986-06-19 Sanyo Electric Co Ltd N type gaas and n type gaalas ohmic electrode
JPS62162327A (en) * 1985-12-23 1987-07-18 Sharp Corp Electrode forming method for iii-v compound semiconductor element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5042786A (en) * 1973-05-18 1975-04-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5042786A (en) * 1973-05-18 1975-04-18

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220967A (en) * 1983-05-21 1984-12-12 テレフンケン・エレクトロニク・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Alloy electrode for n-type conductive gaalas semiconductor material with high aluminum content
JPS61131480A (en) * 1984-11-29 1986-06-19 Sanyo Electric Co Ltd N type gaas and n type gaalas ohmic electrode
JPS62162327A (en) * 1985-12-23 1987-07-18 Sharp Corp Electrode forming method for iii-v compound semiconductor element

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