KR100291824B1 - Method for forming fine contact hole of semiconductor device - Google Patents

Method for forming fine contact hole of semiconductor device Download PDF

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KR100291824B1
KR100291824B1 KR1019940032799A KR19940032799A KR100291824B1 KR 100291824 B1 KR100291824 B1 KR 100291824B1 KR 1019940032799 A KR1019940032799 A KR 1019940032799A KR 19940032799 A KR19940032799 A KR 19940032799A KR 100291824 B1 KR100291824 B1 KR 100291824B1
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forming
contact hole
layer
conductive layer
gate electrode
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KR1019940032799A
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Korean (ko)
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KR960026288A (en
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최양규
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to prevent a short-circuit phenomenon between a conductive layer and a well by forming a pad as a conductive material. CONSTITUTION: An isolation layer(13) is formed on a semiconductor substrate(11). A dopant junction region(15) is formed thereon. A gate oxide layer(17) and a gate electrode(19) are formed thereon. An interlayer dielectric(21) is formed on the gate electrode(19). An oxide layer spacer(23) is formed on a sidewall of the gate electrode(19). The first polysilicon silicon layer(25) is formed on a whole surface of the above structure. A photo-resist layer is formed on the whole surface. The photo-resist layer is etched by using plasma. The first polysilicon layer(25) is etched by the photo-resist layer as an etch barrier. A pad of the first polysilicon layer(25) is formed between the gate electrodes(19) by removing the photo-resist layer. The first oxide layer(29) is formed on the whole surface. The first contact hole(31) is formed by using the first contact mask. The second polysilicon layer(33) is formed on the pad of the first polysilicon layer(25). The second oxide layer(35) is formed on the whole surface. The second contact hole(37) is formed by using the second contact mask. The third polysilicon layer(39) is formed by the second contact hole(37).

Description

[발명의 명칭][Name of invention]

반도체소자의 미세콘택홀 형성방법Micro contact hole formation method of semiconductor device

[발명의 상세한 설명]Detailed description of the invention

본 발명은 반도체소자의 미세콘택홀 형성방법에 관한 것으로, 특히 고집적화된 반도체소자에 미세콘택홀을 형성하는데 있어서, 콘택시키는 도전층과 웰(well)이 형성된 반도체기판이 단락되는 것을 방지하기 위하여 도전체로 형성된 패드를 형성함으로써 반도체소자의 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micro contact hole in a semiconductor device. In particular, in forming a micro contact hole in a highly integrated semiconductor device, a conductive layer for contact and a semiconductor substrate on which a well is formed are prevented from being shorted. The present invention relates to a technique for improving the reliability of semiconductor devices by forming pads formed of a sieve.

종래에는 반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트전극을 형성하고 전체구조상부를 평탄화시키는 하부절연층을 형성한다. 그리고, 자기정렬적인 공정으로 또는 마스크를 이용한 식각공정으로 콘택홀을 형성한다. 그러나, 정렬오차가 발생하여 콘택홀이 미스얼라인(misalign)되는 경우도 있다. 미스얼라인이 발생하는 경우는 상기 소자 분리절연막이 식각되고 상기 불순물 접합영역을 벗어나 웰이 형성된 반도체기판이 노출되기도 한다. 그로인하여, 반도체소자 동작시 접합누설전류가 다량 발생하여 반도체소자의 특성을 저하시킴으로써 반도체소자의 신뢰성을 저하시키는 문제점이 있다.Conventionally, a device isolation insulating film, an impurity junction region and a gate electrode are formed on a semiconductor substrate, and a lower insulating layer is formed to planarize the entire structure. Then, the contact holes are formed by a self-aligned process or by an etching process using a mask. However, there is a case where an alignment error occurs and the contact holes are misaligned. When a misalignment occurs, the device isolation insulating layer may be etched and the semiconductor substrate may be exposed beyond the impurity junction region. As a result, a large amount of junction leakage current occurs during operation of the semiconductor device, thereby deteriorating the characteristics of the semiconductor device, thereby lowering the reliability of the semiconductor device.

제1도는 종래기술에 의하여 형성된 반도체소자를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device formed by the prior art.

제1도를 참조하면, 반도체기판(41) 상부에 소자분리산화막(43)을 형성한다. 그리고, 불순물 접합영역(45)을 형성한다. 그리고, 상기 반도체기판(41)의 활성영역에 게이트산화막(47) 및 게이트전극(49)을 형성한다. 그리고, 상기 게이트전극(49)의 측벽에 산화막 스페이서(51)를 형성한다. 그리고, 전체표면상부를 평탄화시키는 산화막(53)을 형성한다. 그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 반도체기판(41)의 예정된 부분을 노출시키는 콘택홀(55)을 형성한다. 이때, 상기 콘택홀(55)은 상기 불순물 접합영역(45)을 벗어나 상기 소자분리산화막(43)을 식각하고 웰이 형성된 반도체기판(41)을 노출시키도록 형성된 것이다. 그로인하여, 상기 반도체기판(41)은 손상된다. 그리고, 상기 콘택홀을 통하여 상기 반도체기판(41)에 접속시켜 다결정실리콘막(57)을 형성한다. 여기서, 소자 동작시 접합누설전류가 발생한다.Referring to FIG. 1, an isolation oxide layer 43 is formed on the semiconductor substrate 41. Then, the impurity junction region 45 is formed. A gate oxide film 47 and a gate electrode 49 are formed in the active region of the semiconductor substrate 41. An oxide spacer 51 is formed on sidewalls of the gate electrode 49. Then, an oxide film 53 is formed to planarize the entire upper surface portion. In addition, a contact hole 55 exposing a predetermined portion of the semiconductor substrate 41 is formed by an etching process using a contact mask (not shown). In this case, the contact hole 55 is formed to etch the device isolation oxide layer 43 away from the impurity junction region 45 and to expose the semiconductor substrate 41 on which the well is formed. As a result, the semiconductor substrate 41 is damaged. The polysilicon film 57 is formed by connecting to the semiconductor substrate 41 through the contact hole. Here, a junction leakage current is generated during operation of the device.

따라서, 본 발명은 종래기술의 문제점을 해결하기위하여, 상기 반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트전극을 순차적으로 형성하고 전체표면상부에 일정두께 도전층을 형성한 다음, 식각공정으로 상기 게이트전극의 측벽과 상기 게이트전극 간에 상기 도전층으로 형성된 패드를 형성하고 전체표면상부에 하부절연층을 형성한 다음, 콘택마스크를 이용하여 콘택마스크를 형성함으로써 반도체기판에 직접 접속되지 않게 하여 누설전류의 발생을 방지할 수 있어 반도체소자의 신뢰성을 향상시키는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the device isolation insulating film, the impurity junction region, and the gate electrode are sequentially formed on the semiconductor substrate, and a predetermined thickness conductive layer is formed on the entire surface of the semiconductor substrate. A pad formed of the conductive layer is formed between the sidewall of the gate electrode and the gate electrode, and a lower insulating layer is formed on the entire surface, and then a contact mask is formed using a contact mask to prevent direct contact with the semiconductor substrate. The purpose of the present invention is to improve the reliability of semiconductor devices by preventing the generation of current.

이상의 목적을 달성하기위한 본 발명의 특징은, 반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트전극을 순차적으로 형성하는 공정과, 상기 게이트전극의 측벽에 절연막 스페이서를 형성하는 공정과, 전체표면상부에 일정두께 제1도전층을 형성하는 공정과, 전체표면상부에 감광막을 두껍게 형성하는 공정과, 상기 감광막을 상기 제1도전층이 노출되도록 전면식각하는 공정과, 상기 남아있는 감광막을 식각장벽으로하여 상기 제1도전층을 전면식각하는 공정과, 상기 남아있는 감광막을 제거함으로써 상기 게이트전극 간에만 제1도전층패드를 형성하는 공정과, 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 제1도전층패드를 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 제1도전층패드에 접속되도록 제2도전층을 형성하는 공정을 포함하는 반도체소자의 미세콘택홀 형성방법에 있어서, 상기 제1도전 다결정실리콘으로 형성된 것과, 상기 감광막의 전면식각은 산소분위기의 플라즈마를 이용하여 실시하는 것과, 상기 제2도전층은 다결정실리콘으로 형성된 것이다.Features of the present invention for achieving the above object is a step of sequentially forming a device isolation insulating film, an impurity junction region and a gate electrode on the semiconductor substrate, forming an insulating film spacer on the sidewall of the gate electrode, the entire surface Forming a first conductive layer with a predetermined thickness thereon; forming a thick photosensitive film on the entire surface; etching the entire photosensitive film to expose the first conductive layer; and etching the remaining photosensitive film. Forming a first conductive layer pad only between the gate electrodes by removing the remaining photoresist, and forming a lower insulating layer to planarize the entire upper surface of the first conductive layer. And forming a contact hole exposing the first conductive layer pad by an etching process using a contact mask, and forming the contact hole. In the method for forming a micro contact hole of a semiconductor device comprising the step of forming a second conductive layer so as to be connected to the first conductive layer pad, the first conductive polycrystalline silicon is formed, the front surface etching of the photosensitive film is oxygen atmosphere And the second conductive layer is formed of polycrystalline silicon.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2(a)도 내지 제2(d)도는 본 발명의 실시예에 따른 반도체소자의 미세콘택홀 형성공정을 도시한 단면도이다.2 (a) to 2 (d) are cross-sectional views illustrating a process of forming a micro contact hole in a semiconductor device according to an embodiment of the present invention.

제2(a)도를 참조하면, 반도체기판(11) 상부에 소자분리산화막(13)을 형성한다. 그리고, 불순물 접합영역(15)을 형성한다. 그리고, 게이트산화막(17) 및 게이트전극(19)를 형성한다. 그리고, 상기 게이트전극(19)의 상부에 층간절연막(21)을 형성한다. 그리고, 상기 게이트전극(19)의 측벽에 산화막 스페이서(23)를 형성한다. 여기서, 상기 소자분리산화막(13)은 비활성영역에 형성된다. 그리고, 상기 게이트전극(19)은 활성영역에 형성된다. 그 다음에, 전체표면상부에 일정두께 제1다결정실리콘막(25)을 형성한다. 그리고 전체표면상부에 감광막(27)을 두껍게 형성한다.Referring to FIG. 2 (a), the device isolation oxide layer 13 is formed on the semiconductor substrate 11. Then, the impurity junction region 15 is formed. The gate oxide film 17 and the gate electrode 19 are formed. An interlayer insulating film 21 is formed on the gate electrode 19. An oxide spacer 23 is formed on sidewalls of the gate electrode 19. Here, the device isolation oxide layer 13 is formed in an inactive region. The gate electrode 19 is formed in the active region. Next, a first thickness polycrystalline silicon film 25 is formed on the entire surface. Then, a thick photosensitive film 27 is formed on the entire surface.

제2(b)도를 참조하면, 상기 감광막(27)을 전면식각한다. 이때, 전면식각은 산소분위기의 플라즈마를 이용하여 실시한다. 그리고, 상기 제1다결정실리콘막이 노출될 때까지 실시한다. 여기서, 상기 감광막(27)은 상기 게이트전극(19)의 측면에만 형성된다.Referring to FIG. 2B, the photoresist layer 27 is etched entirely. At this time, the front surface etching is performed using a plasma of an oxygen atmosphere. Then, the process is performed until the first polysilicon film is exposed. Here, the photosensitive film 27 is formed only on the side surface of the gate electrode 19.

제2(c)도를 참조하면, 상기 감광막(27)을 식각장벽으로하여 상기 제1다결정실리콘막(25)을 전면식각한다. 그리고, 상기 감광막(27)을 제거한다. 그로인하여, 상기 게이트전극(19) 간에 제1다결정실리콘막(25)패드가 형성된다.Referring to FIG. 2C, the first polysilicon layer 25 is etched by using the photoresist layer 27 as an etch barrier. Then, the photosensitive film 27 is removed. As a result, a first polysilicon layer 25 pad is formed between the gate electrodes 19.

제2(d)도를 참조하면, 전체표면상부를 평 탄화시키는 제1산화막(29)을 형성한다 그리고, 제1콘택마스크(도시안됨)을 이용하여 제1콘택홀(31)을 형성한다 이때, 상기 제1다결정실리콘막(25)패드가 노출된다. 그 다음에, 상기 제1콘택홀(31)을 통하여 상기 제1다결정실리콘막(25)패드에 제2다결정실리콘막(33)을 형성한다. 그리고, 전체표면상부를 평탄화시키는 제2산화막(35)을 형성한다. 그리고, 제2콘택마스크(도시안됨)를 이용하여 상기 제1다결정실리콘막(25)패드를 노출시키는 제2콘택홀(37)을 형성한다. 그리고, 상기 제2콘택홀(37)을 통하여 제3다결정실리콘막(39)을 형성함으로써 콘택을 형성한다.Referring to FIG. 2 (d), a first oxide layer 29 is formed to planarize the entire upper surface, and a first contact hole 31 is formed using a first contact mask (not shown). The pad of the first polysilicon film 25 is exposed. Next, a second polysilicon film 33 is formed on the pad of the first polysilicon film 25 through the first contact hole 31. A second oxide film 35 is formed to planarize the entire upper surface portion. A second contact hole 37 exposing the pad of the first polysilicon layer 25 is formed using a second contact mask (not shown). A contact is formed by forming a third polysilicon film 39 through the second contact hole 37.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 미세콘택홀 형성방법은, 반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트전극을 순차적으로 형성하고 상기 게이트전극의 측면에 사이만 도전층을 형성한 다음, 후공정에서 콘택홀을 형성하고 제2도전층을 콘택시킨 다음, 소자동작할 때, 콘택 미스얼라인이 발생된 상태에서도 접합누설전류의 유출을 방지할 수 있어 반도체소자의 신뢰성을 향상시킬 수 있는 잇점이 있다.As described above, in the method for forming a micro contact hole of a semiconductor device according to the present invention, a device isolation insulating film, an impurity junction region, and a gate electrode are sequentially formed on a semiconductor substrate, and a conductive layer is formed only between side surfaces of the gate electrode. Then, in the subsequent process, contact holes are formed and the second conductive layer is contacted. When the device operates, the leakage leakage current can be prevented even when contact misalignment is generated, thereby improving the reliability of the semiconductor device. There is an advantage to this.

[도면의 간단한 설명][Brief Description of Drawings]

제1도는 종래기술에 의하여 형성된 반도체소자의 미세콘택홀을 도시한 단면도.1 is a cross-sectional view showing a fine contact hole of a semiconductor device formed by the prior art.

제2(a)도 내지 제2(d)도는 본 발명의 실시예에 따른 반도체소자의 미세콘택홀 형성방법을 도시한 단면도.2 (a) to 2 (d) are cross-sectional views illustrating a method for forming a micro contact hole in a semiconductor device according to an embodiment of the present invention.

* 도면에 주요부분에 대한 도면설명* Description of the main parts of the drawings

11,41 : 반도체기판 13,43 : 소자분리산화막11,41: semiconductor substrate 13,43: device isolation oxide film

15,45 : 불순물 접합영역 17,47 : 게이트산화막15,45 impurity junction region 17,47 gate oxide film

19,49 : 게이트전극 21 : 층간절연막19, 49 gate electrode 21 interlayer insulating film

23,51 : 산화막 스페이서 25 : 제1다결정실리콘막23,51: oxide film spacer 25: first polycrystalline silicon film

27 : 감광막 29 : 제1산화막27: photosensitive film 29: first oxide film

31 : 제1콘택홀 33 : 제2다결정실리콘막31: first contact hole 33: second polysilicon film

35 : 제2산화막 37 : 제2콘택홀35: second oxide film 37: second contact hole

39 : 제3다결정실리콘막 53 : 산화막39: third polysilicon film 53: oxide film

55 : 콘택홀 57 : 다결정실리콘막55 contact hole 57 polysilicon film

Claims (4)

반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트전극을 순차적으로 형성하는 공정과, 상기 게이트전극의 측벽에 절연막 스페이서를 형성하는 공정과, 전체표면상부에 일정두께 제1도전층을 형성하는 공정과, 전체표면상부에 감광막을 두껍게 형성하는 공정과, 상기 감광막을 상기 제1도전층이 노출되도록 전면식각하는 공정과, 상기 남아있는 감광막을 식각장벽으로하여 상기 제1도전층을 전면식각하는 공정과, 상기 남아있는 감광막을 제거함으로써 상기 게이트전극 간에만 제1도전층패드를 형성하는 공정과, 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 제1도전층패드를 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 제1도전층패드에 접속되도록 제2도전층을 형성하는 공정을 포함하는 반도체소자의 미세콘택홀 형성방법.Forming a device isolation insulating film, an impurity junction region, and a gate electrode sequentially on the semiconductor substrate; forming an insulating film spacer on the sidewall of the gate electrode; and forming a first conductive layer on the entire surface of the semiconductor substrate. And, forming a thick photoresist film over the entire surface, etching the entire photoresist film to expose the first conductive layer, and etching the entire first conductive layer using the remaining photoresist film as an etch barrier. And removing the remaining photoresist film to form a first conductive layer pad only between the gate electrodes, forming a lower insulating layer to planarize the entire upper surface, and an etching process using a contact mask. Forming a contact hole exposing the conductive layer pad and connecting the first conductive layer pad to the first conductive layer pad through the contact hole; Forming fine contact hole, a semiconductor device including a step of forming a layer. 제1항에 있어서, 상기 제1도전층은 다결정실리콘으로 형성되는 것을 특징으로 하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the first conductive layer is formed of polycrystalline silicon. 제1항에 있어서, 상기 감광막의 전면식각은 산소분위기의 플라즈마를 이용하여 실시하는 것을 특징으로하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the entire surface of the photoresist is etched using a plasma in an oxygen atmosphere. 상기 제2도전층은 다결정실리콘으로 형성된 것을 특징으로하는 반도체소자의 미세콘택홀 형성방법.The second conductive layer is a method for forming a fine contact hole of a semiconductor device, characterized in that formed of polycrystalline silicon.
KR1019940032799A 1994-12-05 1994-12-05 Method for forming fine contact hole of semiconductor device KR100291824B1 (en)

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