JPH0340463A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0340463A JPH0340463A JP1060989A JP6098989A JPH0340463A JP H0340463 A JPH0340463 A JP H0340463A JP 1060989 A JP1060989 A JP 1060989A JP 6098989 A JP6098989 A JP 6098989A JP H0340463 A JPH0340463 A JP H0340463A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- film
- well
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 12
- 150000002500 ions Chemical class 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229910052796 boron Inorganic materials 0.000 description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置及びその製造方法に係り、特に高
集積化する必要の有るメモリに好適な半導体装置および
その製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same suitable for a memory that needs to be highly integrated.
従来のＬＳＩに使用されているＮＭＯＳＦＥＴ間又はＮ
ＭＯＳＦＥＴとＰＭＯ５ＦＥＴ間の素子間分離法として
は１日経エレクトロニクス別冊マイクロデバイセズ特集
１．５〜１μｍ時代のＶＬＳＩＬＳＩ製造技術−７２〜
Ｐ７５されている様ＬＯＧＯ３（ＬｏｃａｌＯｘｉｄａ
ｔｉｏｎ ｏｆ ５ｉｌｉｃｏｎ）法により行われてい
る。Between NMOSFETs used in conventional LSI or N
Regarding the isolation method between MOSFET and PMO5FET, see Nikkei Electronics Special Issue Micro Devices Special Issue 1.5-1μm era VLSILSI manufacturing technology-72-
LOGO3 (LocalOxida)
tion of 5 ilicon) method.
そして、単にＬＯＣＯ５法により分離した状態ではＳｉ
ｎｇ−８ｉ 界面に反転層が発生してしまう。When separated simply by the LOCO5 method, Si
An inversion layer is generated at the ng-8i interface.
この反転層を防止するためにはチャネルストッパとして
ＬＯＧＯＳ酸化する前にチャネルストッパ領域にボロン
をイオン打ち込みし、５ｉＯｚ−Ｓｉ界面で反転しない
ようにする。In order to prevent this inversion layer, boron ions are implanted into the channel stopper region before LOGOS oxidation to prevent inversion at the 5iOz-Si interface.
上記従来技術においては、チャネルストッパとして打込
まれるＰ形不純物（一般にはボロンを使用する）が選択
酸化中に拡散し、ＮＭＯＳＦＥＴの活性領域（即ち、ゲ
ート領域）の不純物濃度を上昇させてしまう。この結果
、メモリセルに使用するＮＭＯＳＦＥＴのようにゲート
幅の狭い素子ではしきい値電圧ＶＴが上昇してしまう、
いわゆる、狭チャネル効果が生ずる。In the prior art described above, the P-type impurity (generally boron is used) implanted as a channel stopper diffuses during selective oxidation, increasing the impurity concentration in the active region (ie, gate region) of the NMOSFET. As a result, the threshold voltage VT increases in devices with narrow gate widths, such as NMOSFETs used in memory cells.
A so-called narrow channel effect occurs.
従来の技術を使用するとこのような狭チャネル効果はゲ
ート幅２．０μｍ以下で発生しだし、ゲート幅１．５μ
ｍ以下ではしきい値電圧Ｖｒが２倍に上昇してしまい、
メモリセル面積の縮少化に対し、著しく障害となってい
る。When conventional technology is used, such narrow channel effects begin to occur with gate widths of 2.0 μm or less, and with gate widths of 1.5 μm or less,
m or less, the threshold voltage Vr increases twice,
This is a significant obstacle to reducing the area of memory cells.
本発明はＬＳＩの高集積化（メモリセルの縮少化）を実
現するため、狭チャネル効果の発生しない分離領域を有
する半導体装置を実現するものである。The present invention is intended to realize a semiconductor device having an isolation region in which no narrow channel effect occurs, in order to achieve high integration of LSI (miniaturization of memory cells).
上記目的を達成するために、本発明は、半導体基板上に
形成された複数の半導体素子と、上記半導体素子を各々
分離する分離領域とを有し、上記分離領域の表面には絶
縁膜が形成され上記分離領域内で、かつ上記絶縁膜との
界面から１．０ μｍの深さにおいて、不純物濃度が
５Ｘ１０１２Ｉ乃至ｌＸ１０１７備″″３であることを
特徴とする。In order to achieve the above object, the present invention includes a plurality of semiconductor elements formed on a semiconductor substrate, and an isolation region that separates the semiconductor elements, and an insulating film is formed on the surface of the isolation region. In the isolation region and at a depth of 1.0 .mu.m from the interface with the insulating film, the impurity concentration is 5.times.10.sup.12I to 1.times.10.sup.17.times.3.
まず、狭チャネル効果の発生するメカニズムを詳細に説
明する。説明にはＮＭＯＳＦＥＴとＰＭＯ５ＦＥＴの間
の分離を例にとる。現在、第２図（ａ）に示すように、
Ｐウェル、Ｎウェルの形成は自己整合技術を使用するた
めＰウェルの酸化膜１２を薄く、Ｎウェルの酸化膜１３
を厚くした状態でＰウェルイオン打込み１１を行う、そ
して、熱処理をした後ＳｉａＮ４ｍを形成し、活性領域
（素子が形成される領域）にレジスト及び５ｉａＮｉｌ
［が残るようにホトリソグラフィ技術及び、ドライエッ
チ技術により形成する（第２図（ｂ）’）、この状態で
ボロンをＮウェル領域には打込まれず、Ｐウェルのチャ
ネルストッパ領域のみに打込まれる様にする。First, the mechanism by which the narrow channel effect occurs will be explained in detail. The explanation uses the separation between an NMOSFET and a PMO5FET as an example. Currently, as shown in Figure 2(a),
Since the formation of the P-well and N-well uses self-alignment technology, the oxide film 12 of the P-well is thinned, and the oxide film 13 of the N-well is thinned.
P-well ion implantation 11 is performed with the P-well ion implanted in a thick state, and after heat treatment, SiaN 4m is formed, and resist and 5iaNil are formed in the active region (region where elements are formed).
In this state, boron is not implanted into the N-well region, but only into the channel stopper region of the P-well. I will make it possible for you to do so.
この条件を満たすためにはボロンの打込エネルギを低く
する必要がある。このためボロンはＳｉ表面の薄い領域
に打ち込まれる。この後、レジストを除去し、５ｉａＮ
ａ膜をマスクとして選択酸化を行い、分離領域を形成す
る。この時、ボロンは酸化膜に取込まれやすい性質を持
っているため、ボロンは酸化膜中にとり込まれ、Ｓｉ−
酸化膜界面のボロン濃度は下がってしまう、一方、チャ
ネルストッパーとして、寄生Ｖｔを確保するためにはＳ
ｉ−酸化膜界面の濃度は１×１０１８以上とする必要が
ある。このため、チャネルストッパ用不純物のボロンの
打込量は酸化膜に取り込まれる量を見込んで決定される
。即ち、多量のボロンを打込む必要がある。したがって
第１図（ｂ）に示すようにＳｉ−酸化膜界面ではボロン
濃度がＩｌＸ１０１ＢＱ’−”であるのに深さ０．６μ
ｍ附近では１０ｔ７国−８と一桁も高い濃度となってし
まう、不純物分布は深さ方向に示したが、横方向も同様
の分布をしており、活性領域での不純物濃度は１×１０
１７０″″３以上になっていることが分かる。このよう
な機構により従来の形成方法でゲート幅の狭いＮＭＯＳ
ＦＥＴを作製するとしきい値電圧ＶＴの高いＮＭＯＳＦ
ＥＴとなってしまう。In order to satisfy this condition, it is necessary to lower the boron implantation energy. For this purpose, boron is implanted into a thin region of the Si surface. After this, the resist was removed and 5iaN
Selective oxidation is performed using the a film as a mask to form isolation regions. At this time, since boron has the property of being easily incorporated into the oxide film, boron is incorporated into the oxide film and the Si-
The boron concentration at the oxide film interface decreases, and on the other hand, as a channel stopper, S
The concentration at the i-oxide film interface needs to be 1×10 18 or more. Therefore, the amount of boron implanted as an impurity for the channel stopper is determined in consideration of the amount incorporated into the oxide film. That is, it is necessary to implant a large amount of boron. Therefore, as shown in Fig. 1(b), although the boron concentration at the Si-oxide film interface is IlX101BQ'-'', the depth is 0.6μ.
The impurity distribution is shown in the depth direction, but the distribution is similar in the lateral direction, and the impurity concentration in the active region is 1×10.
It can be seen that the value is 170″″3 or more. Due to this mechanism, NMOS with narrow gate width can be fabricated using conventional formation methods.
NMOSF with high threshold voltage VT when fabricating FET
It becomes ET.
一般にサブμｍ以下の技術により作られるメモリ素子で
は、メモリセルに使用されるＭＯＳＦＥＴの幅は１．０
μｍ前後、又は、それ以下となる。このため活性領域の
濃度がｌＸ１０”ａｍ″″３以上となる。In general, in memory devices manufactured using sub-μm technology, the width of the MOSFET used in the memory cell is 1.0
It is around μm or less. Therefore, the concentration of the active region becomes 1×10"am""3 or more.
活性領域の不純物濃度が１×１０１７ｃ！１″″３の場
合、ゲート酸化膜厚１００人としてもしきい値電圧が１
．０８Ｖ となり高速化は計れない。信頼性も含めてト
ンネル電流の発生しないゲート酸化膜は８０人であるか
ら−、活性領域の不純物は１×１０１７０ｍ ” ”と
ならなければならない。また、不純物が５Ｘ １０１１
ｓａｍ″″３以下となるとアイソレーション領域でパン
チスルーが発生してしまう。このため、深さ１μｍ（横
子行にも、はぼ同様の分布となる）の位置で不純物濃度
が５ Ｘ １０ Ｌ１５ａｒｍ−”以上で工×１０１７
ｃｓ−”以下としなければならないことが分かる。The impurity concentration in the active region is 1×1017c! In the case of 1""3, the threshold voltage is 1 even if the gate oxide film thickness is 100.
．． 08V, so speeding up cannot be measured. Including reliability, since the gate oxide film that does not generate tunnel current is 80 m, the impurity in the active region must be 1 x 10170 m. Also, impurities are 5X 1011
If sam"" is less than 3, punch-through will occur in the isolation region. Therefore, if the impurity concentration is 5 x 10 L15 arm-'' or more at a depth of 1 μm (the distribution is similar to that in the horizontal row),
It can be seen that it must be less than or equal to "cs-".
本発明ではどのような狭チャネルのメカニズム゛をもと
に狭チャネル効果の発生しない、狭チャネルＮＭＯ８Ｆ
ＥＴを有することを特徴としている。すなわち、選択酸
化後においても、分離領域のｐウェル下のボロン濃度（
−殻内にはＰ型不純物であればよい）を少なくとも界面
から、深さ１μｍの範囲でｌＸ １０１７ａａ−’以下
にするようにした構造を特徴としている。形成方法とし
ては、従来のようにＳｉ表面附近にＰ型不純物を打込ん
だ後、選択酸化するのではなく、選択酸化後にＳ ｉ
０ｚ−Ｓｉ界面が形成される深さにあらかじめＰ型不純
物を打込んだ後、選択酸化する。そうすれば第１図（ｂ
）に示すように、酸化膜中に取り込まれるＰ型不純物は
少なくなり、打込むＰ型不純物量も少なくてすむ、この
結果、拡散により横方向に拡がる不純物濃度は少なくな
り、狭チャネル効果は発生しない、このように、本発明
を使用すると、狭チャネル効果のない狭いチャネル幅を
有したＮＭＯＳＦＥＴを形成することができ、高集積の
ＬＳＩを実現可能となる。In the present invention, the narrow channel NMO8F, which does not cause the narrow channel effect, is based on the narrow channel mechanism.
It is characterized by having ET. In other words, even after selective oxidation, the boron concentration (
The structure is characterized in that the amount of P-type impurity in the shell is less than lX 1017aa-' within a depth of 1 μm from at least the interface. The formation method is not to implant P-type impurities near the Si surface and then perform selective oxidation as in the conventional method, but to selectively oxidize the Si
After p-type impurities are implanted in advance at a depth where the 0z-Si interface will be formed, selective oxidation is performed. Then, Figure 1 (b)
), the amount of P-type impurity incorporated into the oxide film is reduced, and the amount of P-type impurity implanted is also reduced.As a result, the impurity concentration that spreads laterally due to diffusion is reduced, and the narrow channel effect occurs. As described above, by using the present invention, it is possible to form an NMOSFET having a narrow channel width without the narrow channel effect, and it becomes possible to realize a highly integrated LSI.
［実施例１コ
Ｐ基板９上に第２図（ａ）に示すように従来と同様の方
法によりＰウェル、Ｎウェル領域を形成する。その後、
熱処理し、１２，１３の５ｉｆｔ膜を除却した後５ｉＯ
ｚ膜１８及びＳｉ３Ｎ４膜１９を形成する第３図（ａ）
、その後、ホトリソグラフィ技術、及び、ドライエツチ
ングを使用し、チャネルストッパーを形成する領域の５
ｉｓＮ４膜１９を除却した後、Ｐ型不純物をイオンを打
込む２１、この時、この不純物が後で形成される５ｉＯ
ｘ−３ｉの界面に打込まれるように打込エネルギを調節
する第３図（ａ）（本実施例においてはイオン種ボロン
打込エネルギ１００ｋａＶ）。次に第３図（ｂ）に示す
ように、ＰＭＯＳＦＥＴが形成される領域、及びＰウェ
ル領域をホトレジストで被覆した状態で５ｉａＮａ１９
をドライエツチングする。[Example 1] As shown in FIG. 2(a), P-well and N-well regions are formed on a P-substrate 9 by a method similar to the conventional method. after that,
After heat treatment and removal of the 5ift films of 12 and 13, 5iO
FIG. 3(a) showing the formation of the Z film 18 and the Si3N4 film 19
, then use photolithography technique and dry etching to form the channel stopper.
After removing the isN4 film 19, ions of P-type impurity are implanted 21, and at this time, this impurity is used as the 5iO that will be formed later.
FIG. 3(a) adjusts the implantation energy so that it is implanted into the interface of x-3i (in this example, the implantation energy of boron ion species is 100 kaV). Next, as shown in FIG. 3(b), the area where the PMOSFET is formed and the P-well area are covered with photoresist, and the
Dry etching.
その後、レジストを除却後、５ｉａＮ４膜をマスクとし
て分離領域２３を選択酸化する（第３図（Ｃ））。その
後は従来と同様のプロセスでＮＭＯＳＦＥＴ及び、ＰＭ
ＯＳＦＥＴを形成し第１図（ａ）の状態を形成し、素子
を形成することができる。Thereafter, after removing the resist, the isolation region 23 is selectively oxidized using the 5iaN4 film as a mask (FIG. 3(C)). After that, the NMOSFET and PM
By forming an OSFET and forming the state shown in FIG. 1(a), an element can be formed.
［実施例２］
従来の方法では第２図（ｂ）でＰ型不純物としてボロン
を使用していた。しかし、第２図（ｂ）でＰ型不純物と
して、酸化膜に取り込まれすらい、カリウム、又は、イ
ンジウムを使用する。その後の素子の作製方法は従来と
同様として、第１図（ａ）を作製する。そうすることに
より、選択酸化の段階で不純物が酸化膜中に取り込れず
Ｓｉ巾に押し出して行くため、第１図（ｂ、 ）の本発
明の分布と同様にすることができる。[Example 2] In the conventional method, boron was used as the P-type impurity in FIG. 2(b). However, in FIG. 2(b), potassium or indium is used as the P-type impurity since it is incorporated into the oxide film. The subsequent manufacturing method of the device is the same as the conventional method, and the device shown in FIG. 1(a) is manufactured. By doing so, impurities are not incorporated into the oxide film at the stage of selective oxidation but are pushed out to the Si width, so that the distribution can be similar to the distribution of the present invention shown in FIG. 1(b, ).
［実施例３］
実施例１、及び実施例２では選択酸化膜の下のみに高濃
度Ｐ領域を形成したが、第４図に示すように高濃度Ｐ領
域２４をＮＭＯＳＦＥＴの形成されるＰウェル領域に形
成してもよい。ただし、この場合ＮＭＯＳＦＥＴの基板
バイアス係数は大きくなる。[Example 3] In Examples 1 and 2, the high concentration P region was formed only under the selective oxide film, but as shown in FIG. It may be formed in a region. However, in this case, the substrate bias coefficient of the NMOSFET becomes large.
［実施例４］
実施例１では第３図（ｂ）で示した様にチャネルストッ
パ領域になる部分のみレジスト２０を除去し、同一領域
の５ｉａＮ４膜１９を除去した。そして、さらにＰＭＯ
８の分離領域の５ｉａＮａ膜１９を除去したが、この工
程においてホトリソグラフィの合せ余裕により先の５ｉ
ａＮａ膜１９を除去した領域で再度除去する領域が生じ
、この再度除去工程の加わる領域で５ｉＯｚ膜１８が除
去されＳｉ表面までが荒れてしまう。この欠点を防ぐた
め次のような方法で本発明を実施することができた。[Example 4] In Example 1, as shown in FIG. 3(b), the resist 20 was removed only in the portion that would become the channel stopper region, and the 5iaN4 film 19 in the same area was removed. And further PMO
Although the 5iaNa film 19 in the separation region No. 8 was removed, due to the alignment margin of photolithography in this step, the previous 5i Na film 19 was removed.
In the region where the aNa film 19 has been removed, there is a region to be removed again, and in this region where the removal process is applied again, the 5iOz film 18 is removed and even the Si surface becomes rough. In order to avoid this drawback, the present invention could be implemented in the following manner.
第２図（ａ）に示すように、Ｐ基板９上にＰウェル２、
Ｎウェル３を形成し、熱処理した後５ｉ０２膜１２，１
３を除去する。その後、Ｓｉ表面上にＳｉｎｇ膜１８．
５ｉａＮａｌＢ１１９．５ｉｎｓ膜（例えばＨＬＤｌｉ
ｌ）２５を順次形成する＠ （ＳｘＯｓ＋膜２５の原
２５、後でＢイオン打込みをする時のマスクとするため
１５００Å以上とする）この後第６図（ａ）に示す様に
、ホトリソグラフィの技術によりｎＮ０５ＦＥＴ、 ｐ
ＭＯｓＦＥＴの活性領域を残して分離領域のＳｉｎｇＬ
膜２５．５ｉａＮａ膜１９を除去する６次に、第６図（
ｂ）に示す様にレジスト１５を塗布した後、チャネルス
トッパーを形成する領域のレジスト１５を除去する。な
お、ｎＭＯｓＦＥＴすなわち、Ｐウェルにレジストを除
去した領域が拡がってもよい。この状態でＢイオンを所
定の領域２１に打込む、その後、従来のＣＭＯ３ＦＩＩ
ＩＴ製造工程により作製すれば第１図（ａ）とすること
ができる。As shown in FIG. 2(a), a P well 2 is placed on a P substrate 9,
After forming the N well 3 and performing heat treatment, the 5i02 film 12,1
Remove 3. Thereafter, a Sing film 18.
5iaNalB119.5ins membrane (e.g. HLDli
l) Sequentially forming layers 25@ (The original 25 of the SxOs+ film 25 should have a thickness of 1500 Å or more in order to serve as a mask for B ion implantation later) After this, as shown in FIG. 6(a), photolithography is performed. Technology nN05FET, p
SingL in the isolation region leaving the active region of MOsFET
6 Next, the film 25.5iaNa film 19 is removed (Fig.
After applying the resist 15 as shown in b), the resist 15 in the region where the channel stopper is to be formed is removed. Note that the region where the resist is removed may be expanded to the nMOSFET, that is, the P well. In this state, B ions are implanted into a predetermined region 21, and then conventional CMO3FII
If it is manufactured by an IT manufacturing process, it can be made as shown in FIG. 1(a).
実施例１．実施例２及び実施例３共にＣＭＯＳＦＥＴを
例にしたが、本発明はＢｉＣＭＯ５，ＮＭＯ５ＦＥＴ又
は、これらを使用したＳＲＡＭ、ＤＲＡＭ、およびロッ
ジツク等に適用可能であることは明らかである。Example 1. Although a CMOSFET is used as an example in both Examples 2 and 3, it is clear that the present invention is applicable to BiCMO5, NMO5FETs, or SRAMs, DRAMs, lodges, etc. using these.
本発明においては、ゲート幅を狭くしても、活性領域の
不純物濃度が上昇しない、したがって、第５図に示すよ
うに、従来の場合においてはゲート幅が１．５μｍ附近
から狭′い領域でしきい値電圧が急に上昇しているのに
対し、本発明の場合ではゲート幅を狭くしても急なしき
い値電圧の上昇はない、このため、半導体記憶装置等に
使用するＮＭＯ８ＦＥＴのゲニト幅を狭くすることがで
き、高集積の半導体記憶装置を実現することができる。In the present invention, even if the gate width is narrowed, the impurity concentration in the active region does not increase. Therefore, as shown in FIG. In contrast to the sudden rise in threshold voltage, in the case of the present invention, there is no sudden rise in threshold voltage even if the gate width is narrowed. The width can be reduced, and a highly integrated semiconductor memory device can be realized.
この効果は半導体ＬＳＩ全体に対して同様に生・するこ
とは明らかである。It is clear that this effect is produced similarly for the entire semiconductor LSI.
第１図（ａ）は、本発明の一実施例の装置断面図、第１
図（ｂ）は、第１図（ａ）中のＡＡ’線上の不純物濃度
の分布図、第２図（ａ）および第２図（ｂ）は、従来の
製造法を示す図、第３図（ａ）乃至第３図（ｂ）は、本
発明の製造法を示す図、第４図は１本発明の他の実施例
の装置断面図、第５図は、ゲート幅としきい値電圧の関
係を示す図、第６図は本発明の実施例４を説明するため
の装置断面図である。
１・・・チャネルストッパ、２・・・Ｐウェル、３・・
・Ｎウェル、４・・・Ｎ十領域、５・・・Ｐ◆領領域６
・・・多結晶Ｓｉゲート、７・・・電極配線、８・・・
Ｓ ｉ Ｏｘ膜＝９゜１０・・・Ｐ基板、１１・・・Ｐ
型イオン打込、１２・・・Ｐウェルの酸化膜、１３・・
・Ｎウェルの酸化膜、１４・・・Ｓ ｉ ａＮａ［Ｉｓ
（，１５・・・レジスト、１６・・・チャネルストッパ
用（Ｐ型）イオン打込、１７・・・チャネルストッパ打
込領域、１８・・・５ｉＯｚ膜、１９・・・５ｉａＮ番
膜。
２０・・・レジスト、
２１・・・チャネルス
トッパ領域、
２２・・・レジスト、
２３・・・分離領域、
帛
図 （ｄ−）
Δ
Ａ′
嵩
図（ｂ）
ｓＬｏｔ−ｓ、、ｌｑらのＨｉ’！（、ｇｍ）高２図（
ａ、）
窮２図（ｂ）
高３図（旧
第３日（ｂ）
寓３区（０
第４日
高５日
は−トＴ晶
（Ｐ−Ｔｎ）
手
続
補
正
書（方式）
％式％
半導体装置及びその製造方法
補正をする者
’Ｉ’−１’Ｉトノ関１ｉ ＃乳ｉ’ｒｒｌｘｌｆ
ｉ人Ｒ＋８＋ ＋５１ｏ＋ Ｋ 式’ｊ ＋ｔ ８製
作
所
代
理
人
？ｔｉ
正の対象
明細書の図面の簡単な説明の欄FIG. 1(a) is a cross-sectional view of a device according to an embodiment of the present invention.
Figure (b) is a distribution diagram of the impurity concentration on line AA' in Figure 1 (a), Figures 2 (a) and 2 (b) are diagrams showing the conventional manufacturing method, and Figure 3 3(a) to 3(b) are diagrams showing the manufacturing method of the present invention, FIG. 4 is a sectional view of a device according to another embodiment of the present invention, and FIG. 5 is a diagram showing the gate width and threshold voltage. FIG. 6, which is a diagram showing the relationship, is a sectional view of the device for explaining Embodiment 4 of the present invention. 1...Channel stopper, 2...P well, 3...
・N well, 4...N ten areas, 5...P◆territory area 6
... Polycrystalline Si gate, 7... Electrode wiring, 8...
S i Ox film = 9° 10...P substrate, 11...P
Type ion implantation, 12... P-well oxide film, 13...
・N-well oxide film, 14...S iaNa[Is
(, 15... Resist, 16... Channel stopper (P type) ion implantation, 17... Channel stopper implantation region, 18... 5 iOz film, 19... 5iaN film. 20. ...Resist, 21...Channel stopper region, 22...Resist, 23...Isolation region, Schematic diagram (d-) ΔA' Bulk diagram (b) Hi'! of sLot-s,, lq et al. (, gm) 2nd year high school figure (
a,) 2nd grade (b) 3rd grade high school (former 3rd day (b) 3rd grade (0 4th day high school 5th day - TOT crystal (P-Tn) Procedural amendment (method) % formula % Person who corrects semiconductor devices and their manufacturing methods 'I'-1'I Tono Seki 1i #Mi'rrlxlf
i person R+8+ +51o+ K formula'j +t 8 factory agent? ti Field for brief description of drawings in the correct subject specification
Claims (1)
記半導体素子を各々分離する分離領域とを有し、上記分
離領域の表面には絶縁膜が形成され 上記分離領域内で、かつ上記絶縁膜との界面から１．０
μｍの深さにおいて、不純物濃度が５×１０＾１＾５乃
至１×１０＾１＾７ｃｍ＾−＾３であることを特徴とす
る半導体装置。 ２、上記分離領域がＰ型ウェルであることを特徴とする
請求項１記載の半導体装置。 ３、半導体基板に形成された複数のＮＭＯＳＦＥＴ間、
及び、ＮＭＯＳＦＥＴ−ＰＭＯＳＦＥＴ間のＰウェルの
分離領域において、絶縁膜−半導体界面から１．０μｍ
深さの半導体領域でＰ型不純物濃度が５×１０＾１＾５
から１×１０＾１＾７ｃｍ＾−＾３の範囲であることを
特徴とした半導体装置。 ４、特許請求の範囲第３項におけるＰウェルの分離領域
となる半導体中にＰ型不純物を０．１μｍ〜０．６μｍ
の飛程となる条件でイオン打込みした後、分離領域を選
択酸化することを特徴とした半導体装置の製造方法。 ５、特許請求の範囲第４項におけるＰ型不純物をＧａあ
るいはＩｎとしたことを特徴とする半導体装置の製造方
法。 ６、特許請求の範囲第３項記載の半導体装置を集積化し
たことを特徴とする記憶装置。 ７、ゲート幅が１．５μｍ以下でありかつしきい値電圧
が０〜１．０Ｖの範囲であるＮＭＯＳＦＥＴを含むこと
を特徴とした半導体装置。 ８、ゲート幅が１．５μｍ以下でしきい値電圧が０〜１
．０Ｖ（７）ＮＭＯＳＦＥＴと、ゲート幅１．５μｍ以
上でしきい値電圧が−１．０〜１．０ＶのＮＭＯＳＦＥ
Ｔとを含むことを特徴とする半導体装置。 ９、ＮＭＯＳＦＥＴが形成される半導体基板内のＰウェ
ル領域に分離領域に選択酸化膜が半導体中に形成される
深さにＰ型不純物を他の領域よりも高濃度としておくこ
とを特徴とした半導体装置。[Claims] 1. A plurality of semiconductor elements formed on a semiconductor substrate, and an isolation region that separates the semiconductor elements, and an insulating film is formed on the surface of the isolation region. 1.0 within and from the interface with the insulating film
A semiconductor device characterized in that the impurity concentration is 5×10^1^5 to 1×10^1^7 cm^-^3 at a depth of μm. 2. The semiconductor device according to claim 1, wherein the isolation region is a P-type well. 3. Between multiple NMOSFETs formed on a semiconductor substrate,
and 1.0 μm from the insulating film-semiconductor interface in the P-well isolation region between NMOSFET and PMOSFET.
P-type impurity concentration in the semiconductor region at a depth of 5×10^1^5
1 x 10^1^7 cm^-^3. 4. Adding P-type impurities to a thickness of 0.1 μm to 0.6 μm in the semiconductor serving as the isolation region of the P well in Claim 3
1. A method for manufacturing a semiconductor device, which comprises selectively oxidizing an isolation region after ion implantation under conditions that achieve a range of . 5. A method for manufacturing a semiconductor device, characterized in that the P-type impurity in claim 4 is Ga or In. 6. A memory device characterized by integrating the semiconductor device according to claim 3. 7. A semiconductor device comprising an NMOSFET with a gate width of 1.5 μm or less and a threshold voltage in the range of 0 to 1.0V. 8. Gate width is 1.5 μm or less and threshold voltage is 0 to 1
．． 0V (7) NMOSFET and NMOSFE with a gate width of 1.5 μm or more and a threshold voltage of -1.0 to 1.0V
A semiconductor device comprising: T. 9. A semiconductor characterized in that a selective oxide film is formed in a P-well region in a semiconductor substrate in which an NMOSFET is formed and a selective oxide film is formed in the semiconductor at a higher concentration than in other regions. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1060989A JPH0340463A (en) | 1989-03-15 | 1989-03-15 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1060989A JPH0340463A (en) | 1989-03-15 | 1989-03-15 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0340463A true JPH0340463A (en) | 1991-02-21 |
Family
ID=13158355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1060989A Pending JPH0340463A (en) | 1989-03-15 | 1989-03-15 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0340463A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5766970A (en) * | 1992-02-25 | 1998-06-16 | Samsung Electronics Co., Ltd. | Method of manufacturing a twin well semiconductor device with improved planarity |
| US5856215A (en) * | 1995-08-25 | 1999-01-05 | Hyundai Electronics Industries Co., Ltd. | Method of fabricating a CMOS transistor |
| JP2007131308A (en) * | 2005-11-08 | 2007-05-31 | Hokkaido Seikan Kogyo Kk | Container apparatus for delivering fertilizer |
-
1989
- 1989-03-15 JP JP1060989A patent/JPH0340463A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5766970A (en) * | 1992-02-25 | 1998-06-16 | Samsung Electronics Co., Ltd. | Method of manufacturing a twin well semiconductor device with improved planarity |
| US5856215A (en) * | 1995-08-25 | 1999-01-05 | Hyundai Electronics Industries Co., Ltd. | Method of fabricating a CMOS transistor |
| JP2007131308A (en) * | 2005-11-08 | 2007-05-31 | Hokkaido Seikan Kogyo Kk | Container apparatus for delivering fertilizer |
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