JPH0324736U - - Google Patents

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Publication number
JPH0324736U
JPH0324736U JP8427889U JP8427889U JPH0324736U JP H0324736 U JPH0324736 U JP H0324736U JP 8427889 U JP8427889 U JP 8427889U JP 8427889 U JP8427889 U JP 8427889U JP H0324736 U JPH0324736 U JP H0324736U
Authority
JP
Japan
Prior art keywords
unit
digital multiplexing
channel
detection circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8427889U
Other languages
Japanese (ja)
Other versions
JPH083078Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8427889U priority Critical patent/JPH083078Y2/en
Publication of JPH0324736U publication Critical patent/JPH0324736U/ja
Application granted granted Critical
Publication of JPH083078Y2 publication Critical patent/JPH083078Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路ブロツク
図である。 １……デジタル多重化ユニツト、２……チヤネ
ルユニツト、１１……Ｄ型フリツプフロツプ（Ｄ
ＦＦ）、１２……ユニツト抜け検出回路（ＤＴｃ
）、１３……メモリ読出しクロツク断検出回路（
ＤＴｃｋ）、１４……オアゲート（ＯＲ）、２１
……パルス検出回路（ＤＴｐ）、２２……メモリ
回路（ＭＥＭ）。 FIG. 1 is a circuit block diagram showing one embodiment of the present invention. 1...Digital multiplexing unit, 2...Channel unit, 11...D flip-flop (D
FF), 12... Unit disconnection detection circuit (DTc
), 13...Memory read clock disconnection detection circuit (
DTck), 14...OR Gate (OR), 21
...Pulse detection circuit (DTp), 22...Memory circuit (MEM).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デジタル多重化ユニツトとチヤネルユニツトを
有するデジタル多重化装置において、前記チヤネ
ルユニツトにメモリ読出しクロツク断又はユニツ
ト抜けのいずれかが発生したときこれを検出する
検出回路と、この検出回路の出力を入力とするオ
アゲートと、このオアゲートの出力によりセツト
されて異常の発生したチヤネルのデータをＡＩＳ
にして出力するＤ型フリツプフロツプとを備える
ことを特徴とするデジタル多重化装置におけるＡ
ＩＳ送出回路。 A digital multiplexing device having a digital multiplexing unit and a channel unit includes a detection circuit that detects when either a memory read clock disconnection or a unit omission occurs in the channel unit, and the output of this detection circuit is input. The OR gate and the data of the channel where the error occurred due to the output of this OR gate are set to AIS.
A in a digital multiplexing device characterized by comprising a D-type flip-flop that outputs
IS sending circuit.
JP8427889U 1989-07-17 1989-07-17 AIS transmission circuit in digital multiplexer Expired - Fee Related JPH083078Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8427889U JPH083078Y2 (en) 1989-07-17 1989-07-17 AIS transmission circuit in digital multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8427889U JPH083078Y2 (en) 1989-07-17 1989-07-17 AIS transmission circuit in digital multiplexer

Publications (2)

Publication Number Publication Date
JPH0324736U true JPH0324736U (en) 1991-03-14
JPH083078Y2 JPH083078Y2 (en) 1996-01-29

Family

ID=31632633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8427889U Expired - Fee Related JPH083078Y2 (en) 1989-07-17 1989-07-17 AIS transmission circuit in digital multiplexer

Country Status (1)

Country Link
JP (1) JPH083078Y2 (en)

Also Published As

Publication number Publication date
JPH083078Y2 (en) 1996-01-29

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