JPS60110898U - Buzzer drive circuit - Google Patents

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、及び第２図はそれぞれ従来のブザー駆動回路を
示すブロック図、第３図は本考案の一実施例を示すブロ
ック図、第４図は上記実施例に於ける各部の信号波形を
示す図である。 １１・・・ＣＰＵ、　　１２・・・外部出力回路、１３
，１４・・・オア回路、１５・・・ブザー。1 and 2 are block diagrams showing conventional buzzer drive circuits, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 shows signal waveforms at various parts in the above embodiment. FIG. 11...CPU, 12...External output circuit, 13
, 14...OR circuit, 15...buzzer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] １本のブザー出力端子を有してなるＣＰＵと、このＣＰ
Ｕにバス接続され、ＣＰＵの制御の下にインターラブド
信号を出力する外部出力回路と、上記ブザー出力端子の
出力信号により駆動されるブザーとを有してなる電子機
器に於いて、上記ＣＰＵのブザー出力端子の信号と上記
外部出力回路のインターラブド信号とを受けて、インタ
ーラブド信号がアクティブ状態にある時のみ、上記ブザ
ーの端子間に、上記ブザー出力端子の信号変化に同期し
た互いに逆位相をなす駆動信号を供給し、上記インター
ラブド信号がノンアクティブ状態にある時に、上記ブザ
ーの端子間に、同電位の信号を供給する論理回路を設け
てなることを特徴とするブザー駆動回路。A CPU having one buzzer output terminal, and this CPU
In an electronic device comprising an external output circuit that is connected to the U via a bus and outputs an interwoven signal under the control of the CPU, and a buzzer that is driven by the output signal of the buzzer output terminal, In response to the signal of the buzzer output terminal and the interlaced signal of the external output circuit, only when the interlaced signal is in the active state, the terminals of the buzzer are connected at opposite phases to each other in synchronization with the change in the signal of the buzzer output terminal. 1. A buzzer drive circuit, comprising: a logic circuit that supplies a drive signal having the same potential, and supplies a signal of the same potential between terminals of the buzzer when the interlaced signal is in a non-active state.