JPS6013591U - display control circuit - Google Patents
display control circuitInfo
- Publication number
- JPS6013591U JPS6013591U JP10485183U JP10485183U JPS6013591U JP S6013591 U JPS6013591 U JP S6013591U JP 10485183 U JP10485183 U JP 10485183U JP 10485183 U JP10485183 U JP 10485183U JP S6013591 U JPS6013591 U JP S6013591U
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- display control
- control circuit
- display section
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示すもので、第１図は回路構
成図、第２図ａ、 ｂは第１図における出カパツファ
部の回路接続状態を示す図である。
１・・・・・・メモリ、２・・・・・・表示バッファ、
３・・・・・・セグメントデコーダ、４．〜４ｎ、
８．〜８１０・・・・・・バッファ、６・・・・・・デ
ジット信号デコーダ、１４・・・・・・フリップフロッ
プ。The drawings show one embodiment of the present invention, and FIG. 1 is a circuit diagram, and FIGS. 2a and 2b are diagrams showing the circuit connection state of the output puffer section in FIG. 1. 1...Memory, 2...Display buffer,
3...Segment decoder, 4. ~4n,
8. ~810...Buffer, 6...Digital signal decoder, 14...Flip-flop.
Claims (1)
、状態表示部への状態信号をゲート制御するゲート回路
と、上記デコーダ及びゲート回路に共通使用され表示部
への表示制御信号を出力する出力端子と、上記デコーダ
の出力端の一つに接続され、外部回路の接続状態に応じ
て上記デコーダあるいは上記ゲート回路の一方を動作状
態に切換える動作モード設定手段とを具備したことを特
徴とする表示制御回路。A decoder that generates a digit signal to the digital display section, a gate circuit that gate-controls the status signal to the status display section, and an output terminal that is commonly used by the decoder and gate circuit and outputs a display control signal to the display section. , a display control circuit comprising operation mode setting means connected to one of the output terminals of the decoder and for switching either the decoder or the gate circuit to an operating state depending on a connection state of an external circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10485183U JPS6013591U (en) | 1983-07-06 | 1983-07-06 | display control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10485183U JPS6013591U (en) | 1983-07-06 | 1983-07-06 | display control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6013591U true JPS6013591U (en) | 1985-01-29 |
Family
ID=30246023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10485183U Pending JPS6013591U (en) | 1983-07-06 | 1983-07-06 | display control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6013591U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6296996U (en) * | 1985-12-03 | 1987-06-20 |
-
1983
- 1983-07-06 JP JP10485183U patent/JPS6013591U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6296996U (en) * | 1985-12-03 | 1987-06-20 | ||
| JPH0123677Y2 (en) * | 1985-12-03 | 1989-07-19 |
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