JPH03218036A - Semiconductor element mounting board - Google Patents
Semiconductor element mounting boardInfo
- Publication number
- JPH03218036A JPH03218036A JP2013414A JP1341490A JPH03218036A JP H03218036 A JPH03218036 A JP H03218036A JP 2013414 A JP2013414 A JP 2013414A JP 1341490 A JP1341490 A JP 1341490A JP H03218036 A JPH03218036 A JP H03218036A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bumps
- terminals
- substrate
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 230000008018 melting Effects 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 25
- 238000007747 plating Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＩＣチップ等の半導体素子が実装される半導
体素子実装用基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element mounting substrate on which a semiconductor element such as an IC chip is mounted.
ＩＣ等の半導体素子を基板上に実装する場合に、半導体
素子の電極パッド上に凸状のバンプを形成し、このバン
プを基板上に形成されている電極端子上に直接接続する
ことが行われている。When mounting a semiconductor element such as an IC on a substrate, a convex bump is formed on the electrode pad of the semiconductor element, and this bump is directly connected to the electrode terminal formed on the substrate. ing.
基板上の電極端子は、従来、平坦に形成されていた。こ
のため、半導体素子上のバンプを基板上の電極端子に正
確に位置合せしなければ、バンプ材料が電極端子の周辺
部にはみ出し、隣接する電極端子同士を短絡させるおそ
れがあった。Conventionally, electrode terminals on a substrate have been formed flat. For this reason, unless the bumps on the semiconductor element are accurately aligned with the electrode terminals on the substrate, there is a risk that the bump material will protrude to the periphery of the electrode terminals, causing a short circuit between adjacent electrode terminals.
また、半導体素子の集積度が高くなるほど、基板上に形
成される電極端子のサイズ及びピッチ間隔は小さくなる
。このため、高集積化が進むほどバンプと電極端子とを
非常に高い精度で位置合せする必要が生ずる。Furthermore, the higher the degree of integration of semiconductor elements, the smaller the size and pitch of the electrode terminals formed on the substrate. Therefore, as the degree of integration increases, it becomes necessary to align bumps and electrode terminals with extremely high precision.
しかし、そのような高い精度での位置合せには、それな
りの時間が必要であり、実装に要する時間が長くなると
共に、高精度で高価な位置合せ装置を必要とする。この
ため、実装コストが高いものとなっていた。However, alignment with such high precision requires a certain amount of time, increases the time required for implementation, and requires a highly accurate and expensive alignment device. For this reason, the implementation cost has been high.
そこで、上述の事情に鑑み、本発明は実装に要する時間
を短縮すると共に、実装コストを低減することを目的と
している。Therefore, in view of the above-mentioned circumstances, the present invention aims to shorten the time required for implementation and reduce the implementation cost.
上述の目的を達成するため、本発明による半導体素子実
装用基板においては、基板上の電極端子に半導体素子上
のバンプの少なくとも頂部を受容する凹部が形成されて
おり、この電極端子の表面のうち少なくとも凹部がバン
プよりも低融点の金属層により覆われていることを特徴
としている。In order to achieve the above object, in the substrate for mounting a semiconductor element according to the present invention, a recess is formed in the electrode terminal on the substrate to receive at least the top of the bump on the semiconductor element, and a recess is formed in the electrode terminal on the substrate. It is characterized in that at least the recessed portion is covered with a metal layer having a lower melting point than the bump.
このようにすることにより、大まかな位置合せ後に電極
端子の表面の低融点金属層を溶融させると、低融点金属
の表面張力により半導体素子上のバンプが基板上の電極
端子の凹部内に誘導され、バンプと電極端子とが正確に
位置合せされる。By doing this, when the low melting point metal layer on the surface of the electrode terminal is melted after rough alignment, the bumps on the semiconductor element are guided into the recesses of the electrode terminal on the substrate due to the surface tension of the low melting point metal. , the bump and electrode terminal are accurately aligned.
以下、本発明の実施例について第１図及び第２図を参照
しつつ、説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
しており、第２図は実装後の状態を示している。FIG. 1 shows a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminals, and FIG. 2 shows the state after mounting.
図示したように、半導体素子１にはその表面から突出し
て複数のバンプ２が形成されている。As shown in the figure, a plurality of bumps 2 are formed on the semiconductor element 1 so as to protrude from the surface thereof.
他方、半導体素子１が実装される基板３には、半導体素
子１上のバンプに対応して複数の電極端子５が形成され
ている。この電極端子５はその表面にバンプ２の少なく
とも頂部を受容する凹部４を有している。電極端子５は
、例えば次のようにして形成される。まず、基板３の電
極端子５が形成される部分に窪みを形成する。この窪み
は半導体素子１上に形成されているバンプ２の少なくと
も頂部（図では下端部）を受容し得る程度の大きさに形
成される。そして、この窪みに選択的にメッキを施すな
どして電極端子５が形成される。このようにして形成さ
れた電極端子５は、その表面にバンプ２の少なくとも頂
部を受容する凹部４を有することとなる。電極端子５の
表面のうち少なくとも四部４は、バンプ２及び電極端子
５よりも融点が低い金属（例えば、Ａ ｕ ／ ２ ０
％Ｓｎ，Ｐｂ／４０％Ｉｎ）からなる金属層６により覆
われている。金属層６は、真空蒸着等の方法により形成
される。なお、この凹部４の最も深い位置（最も低い位
置）に電極端子５の中心が一致していることが好ましい
。On the other hand, a plurality of electrode terminals 5 are formed on the substrate 3 on which the semiconductor element 1 is mounted, corresponding to the bumps on the semiconductor element 1. The electrode terminal 5 has a recess 4 on its surface for receiving at least the top of the bump 2. The electrode terminal 5 is formed, for example, as follows. First, a depression is formed in a portion of the substrate 3 where the electrode terminal 5 is to be formed. This depression is formed in a size large enough to receive at least the top (lower end in the figure) of the bump 2 formed on the semiconductor element 1. Then, the electrode terminal 5 is formed by selectively plating the depression. The electrode terminal 5 thus formed has a recess 4 on its surface that receives at least the top of the bump 2. At least four parts 4 of the surface of the electrode terminal 5 are made of a metal having a lower melting point than the bumps 2 and the electrode terminal 5 (for example, A u / 2 0
%Sn, Pb/40%In). The metal layer 6 is formed by a method such as vacuum deposition. Note that it is preferable that the center of the electrode terminal 5 coincides with the deepest position (lowest position) of the recess 4.
このように形成された基板３に対して、半導体素子１を
実装する場合、半導体素子１上のバンプ２と基板３上の
電極端子５との位置合せが図示しない位置合せ装置によ
り行われるが、この位置合せは、第１図に示したように
、バンプ２の一部が金属層６に当接する程度の大まかな
位置合せで足りる。なぜなら、この位置合せの後に基板
３を加熱して金属層６だけを溶融させると、溶融した金
属層材料はその表面張力により収縮する。このとき、バ
ンプ２の頂部が金属層６に当接していれば第２図に示し
たように、バンプ２は該表面張力により凹部４内に誘導
され、電極端子５に対して正確に位置合せされるからで
ある。なお、この表面張力はバンプ２が形成されている
半導体素子１上の電極パッド（図示せず）と基板３上の
電極端子５との間で、金属層材料の表面積をできるだけ
小さくするように働く。したがって、この表面張力によ
り半導体素子１上の各電極パッドと基板３上の各電極端
子５との総合的な位置ズレが最小となるように、半導体
素子１は基板３に対して位置合せされる。このようにし
て正確な位置合せが行われた後、さらに基板３を加熱し
てバンプ２を溶融し、バンプ２と電極端子５とを互いに
接続してもよいし、バンプ２は溶融させず溶融した金属
層材料により接続することとしてもよい。When mounting the semiconductor element 1 on the substrate 3 formed in this way, the bumps 2 on the semiconductor element 1 and the electrode terminals 5 on the substrate 3 are aligned by an alignment device (not shown). As shown in FIG. 1, this alignment only needs to be so rough that a portion of the bump 2 comes into contact with the metal layer 6. This is because, when the substrate 3 is heated to melt only the metal layer 6 after this alignment, the molten metal layer material contracts due to its surface tension. At this time, if the top of the bump 2 is in contact with the metal layer 6, the bump 2 will be guided into the recess 4 by the surface tension and accurately aligned with the electrode terminal 5, as shown in FIG. This is because it will be done. Note that this surface tension acts to minimize the surface area of the metal layer material between the electrode pad (not shown) on the semiconductor element 1 on which the bump 2 is formed and the electrode terminal 5 on the substrate 3. . Therefore, due to this surface tension, the semiconductor element 1 is aligned with the substrate 3 so that the overall positional deviation between each electrode pad on the semiconductor element 1 and each electrode terminal 5 on the substrate 3 is minimized. . After accurate alignment is performed in this way, the bumps 2 may be further heated to melt the bumps 2 and the bumps 2 and the electrode terminals 5 may be connected to each other, or the bumps 2 may be melted without being melted. The connection may be made using a metal layer material.
半導体素子１上に形成されるバンプ２のサイズを直径８
０μｍ１高さ約３０μｍとし、また、基板３上の電極端
子５のサイズを直径１００μｍとし、金属層６を電極端
子５の上面全体に形成して、半導体素子１を基板３に実
装した。この場合に、実装後のバンプ２と電極端子５の
位置ズレを±１０μｍ以内に納めるために、位置合せ装
置に要求される位置合せ精度は±５０μｍであった。The size of the bump 2 formed on the semiconductor element 1 is 8 in diameter.
The semiconductor element 1 was mounted on the substrate 3 by forming the metal layer 6 over the entire upper surface of the electrode terminal 5. In this case, in order to keep the positional deviation between the bump 2 and the electrode terminal 5 after mounting within ±10 μm, the alignment accuracy required of the alignment device was ±50 μm.
これに対して、上述の例と同寸法の平坦な電極端子が形
成された従来の基板に、上述した例と同じ半導体素子を
実装したところ、位置合せ装置に同様に要求される精度
は±１０μｍであった。この結果を下表に示す。On the other hand, when the same semiconductor element as in the above example was mounted on a conventional substrate on which flat electrode terminals with the same dimensions as in the above example were formed, the accuracy required for the alignment device was ±10 μm. Met. The results are shown in the table below.
以上説明したように、本発明によれば従来のように高精
度で高価な位置合せ装置を必要とせず、比較的安価な位
置合せ装置を用いることができる。As described above, according to the present invention, a relatively inexpensive alignment device can be used instead of requiring a highly accurate and expensive alignment device as in the prior art.
また、位置合せ装置による位置合せは、大まかなもので
足りるので、位置合せ装置による精密な位置合せを必要
としていた従来に比し、位置合せ装置による位置合せに
必要とされる時間が短くなる。Furthermore, since only rough alignment is required by the alignment device, the time required for alignment by the alignment device is shorter than in the past, which required precise alignment by the alignment device.
したがって、実装に要する時間及びコストを低減するこ
とができる。Therefore, the time and cost required for implementation can be reduced.
第１図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
した図、第２図はそれらの実装後の状態を示した図であ
る。
１・・・半導体素子、２・・・バンプ、３・・・基板、
４・・・凹部，５・・・電極端子、６・・・金属層。FIG. 1 is a diagram showing a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminal, and FIG. 2 is a diagram showing the state after mounting them. 1... Semiconductor element, 2... Bump, 3... Substrate,
4... Concave portion, 5... Electrode terminal, 6... Metal layer.
Claims (1)
って、 前記バンプが接続される電極端子を有しており、前記電
極端子の表面には前記バンプの少なくとも頂部を受容す
る凹部が形成され、前記電極端子の表面のうち少なくと
も前記凹部は前記バンプよりも低融点の金属層により覆
われていることを特徴とする半導体素子実装用基板。[Scope of Claims] A substrate on which a semiconductor element having bumps on the surface is mounted, comprising an electrode terminal to which the bump is connected, and the surface of the electrode terminal receives at least the top of the bump. 1. A substrate for mounting a semiconductor element, wherein a recess is formed, and at least the recess on the surface of the electrode terminal is covered with a metal layer having a lower melting point than the bump.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013414A JPH03218036A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
| AU69823/91A AU637874B2 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| CA002034700A CA2034700A1 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| KR1019910001105A KR950001368B1 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
| EP91100821A EP0439137A2 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
| US07/644,846 US5196726A (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device having particular terminal and bump structure |
| US07/993,006 US5298460A (en) | 1990-01-23 | 1992-12-18 | Substrate for packaging a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013414A JPH03218036A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218036A true JPH03218036A (en) | 1991-09-25 |
Family
ID=11832477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013414A Pending JPH03218036A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218036A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008244180A (en) * | 2007-03-28 | 2008-10-09 | Kyocera Corp | Mounting structure and manufacturing method therefor |
| JP2008277393A (en) * | 2007-04-26 | 2008-11-13 | Kyocera Corp | Mounting structure and its manufacturing method |
-
1990
- 1990-01-23 JP JP2013414A patent/JPH03218036A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008244180A (en) * | 2007-03-28 | 2008-10-09 | Kyocera Corp | Mounting structure and manufacturing method therefor |
| JP2008277393A (en) * | 2007-04-26 | 2008-11-13 | Kyocera Corp | Mounting structure and its manufacturing method |
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