JPH03218038A - Mounting method of semiconductor element - Google Patents

Mounting method of semiconductor element

Info

Publication number
JPH03218038A
JPH03218038A JP2013416A JP1341690A JPH03218038A JP H03218038 A JPH03218038 A JP H03218038A JP 2013416 A JP2013416 A JP 2013416A JP 1341690 A JP1341690 A JP 1341690A JP H03218038 A JPH03218038 A JP H03218038A
Authority
JP
Japan
Prior art keywords
semiconductor element
bumps
mounting
board
mounting board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013416A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2013416A priority Critical patent/JPH03218038A/en
Priority to CA002034700A priority patent/CA2034700A1/en
Priority to AU69823/91A priority patent/AU637874B2/en
Priority to EP91100821A priority patent/EP0439137A2/en
Priority to KR1019910001105A priority patent/KR950001368B1/en
Priority to US07/644,846 priority patent/US5196726A/en
Publication of JPH03218038A publication Critical patent/JPH03218038A/en
Priority to US07/993,006 priority patent/US5298460A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the time and the cost necessary for mounting by forming, on electrode terminals, recessed parts accepting the tip parts of bumps, arranging low melting metal at the central part, heating a board, and jetting cooling gas thereon. CONSTITUTION:A plurality of bumps 2 are formed on a semiconductor element 1, and a plurality of electrode terminals 5 are formed on a mounting board 3 so as to correspond with the bumps 2. On the surfaces of the terminals 5, recessed parts 4 accepting at least the tip parts of the bumps 2 are formed so as to become deep gradually from the outer periphery toward the center part at which the depth becomes maximum. The center part 5a of the terminal 5 is formed by using metal whose melting point is lower than the metal forming the outer peripheral part 5b. At the time of mounting the element 1, the board 3 is heated, and cooling gas is jetted on the surface of the board 3. Hence, the bumps 2 can be highly precisely aligned with the terminals 5 only by pressing the element 1 against the board 3 after rough alignment. Further, only the metal at the center part 5a can be melted, so that highly precise alignment is enabled in a short time and at a low cost.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣチップ等の半導体素子の表面に突出して
形成されたバンプを実装基板上の電極端子に直接接続（
フェースダウンボンディング）して半導体素子を実装基
板上に実装する方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for directly connecting bumps formed protruding from the surface of a semiconductor element such as an IC chip to electrode terminals on a mounting board.
The present invention relates to a method of mounting a semiconductor element on a mounting substrate using face-down bonding.

〔従来の技術〕[Conventional technology]

ＩＣチップ等の半導体素子を実装基板上に実装する場合
に、半導体素子の電極パッド上に凸状のバンプを形成し
、このバンプを実装基板上に形成されている電極端子上
に直接接続することが行われている。When mounting a semiconductor element such as an IC chip on a mounting board, a convex bump is formed on the electrode pad of the semiconductor element, and this bump is directly connected to the electrode terminal formed on the mounting board. is being carried out.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

実装基板上の電極端子は、従来、平坦に形成されていた
。このため、半導体素子上のバンプを実装基板上の電極
端子に正確に位置合せしなければ、バンプ材料や予備ハ
ンダが電極端子の周辺部にはみ出し、隣接する電極端子
同士を短絡させるおそれがあった。Conventionally, electrode terminals on a mounting board have been formed flat. For this reason, if the bumps on the semiconductor element were not accurately aligned with the electrode terminals on the mounting board, there was a risk that the bump material and preliminary solder would protrude around the electrode terminals, causing short-circuits between adjacent electrode terminals. .

また、半導体素子の集積度が高くなるほど、実装基板上
に形成される電極端子のサイズ及びピッチ間隔は小さく
なる。このため、高集積化が進むほどバンプと電極端子
とを非常に高い精度で位置合せする必要が生ずる。Furthermore, the higher the degree of integration of semiconductor elements, the smaller the size and pitch of the electrode terminals formed on the mounting substrate. Therefore, as the degree of integration increases, it becomes necessary to align bumps and electrode terminals with extremely high precision.

しかし、そのような高い精度での位置合せには、それな
りの時間が必要であり、実装に要する時間が長くなると
共に、高精度で高価な位置合せ装置を必要とする。この
ため、実装コストが高いものとなっていた。However, alignment with such high precision requires a certain amount of time, increases the time required for implementation, and requires a highly accurate and expensive alignment device. For this reason, the implementation cost has been high.

そこで、上述の事情に鑑み、本発明は実装に要する時間
を短縮すると共に、実装コストを低減することを目的と
している。Therefore, in view of the above-mentioned circumstances, the present invention aims to shorten the time required for implementation and reduce the implementation cost.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明による半導体素子の
実装方法においては、実装基板上の電極端子に半導体素
子上のバンプの頂部を受容する凹部を形成すると共に、
この四部の少なくとも中央部に低融点金属を配しておき
、実装基板を加熱すると共に、実装基板の表面に冷却用
ガスを吹き付けることとしている。In order to achieve the above object, in the method for mounting a semiconductor element according to the present invention, a recess is formed in an electrode terminal on a mounting board to receive the top of a bump on the semiconductor element, and
A low melting point metal is arranged at least in the center of these four parts to heat the mounting board and to spray cooling gas onto the surface of the mounting board.

〔作用〕[Effect]

このようにすることにより、大まかな位置合せ後に半導
体素子を実装基板に押し付けるだけで、半導体素子上の
バンプが実装基板上の電極端子に対して高精度に位置合
せされる。さらに、電極端子の四部の中央部の低融点金
属だけを溶融させることができ、溶融した低融点金属の
表面張力により半導体素子上のバンプが実装基板上の電
極端子の中央部に誘導され、バンプと電極端子とがより
高精度に位置合せされる。By doing so, the bumps on the semiconductor element can be aligned with high precision with respect to the electrode terminals on the mounting board by simply pressing the semiconductor element against the mounting board after rough alignment. Furthermore, it is possible to melt only the low melting point metal at the center of the four parts of the electrode terminal, and the bumps on the semiconductor element are guided to the center of the electrode terminal on the mounting board by the surface tension of the molten low melting point metal. and the electrode terminal are aligned with higher precision.

〔実施例〕〔Example〕

以下、本発明の実施例について第１図〜第３図を参照し
つつ、説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.

第１図は本発明が適用される実装基板とその電極端子に
対して大まかに位置合せされた半導体素子とを示してお
り、第２図は半導体素子上のバンプが第１図に示した状
態から実装基板上の電極端子の中央部に移動する途中の
状態を示しており、第３図は実装後の状態を示している
。FIG. 1 shows a mounting board to which the present invention is applied and a semiconductor element roughly aligned with its electrode terminals, and FIG. 2 shows a state in which the bumps on the semiconductor element are in the same state as shown in FIG. 1. It shows the state in the middle of moving from the electrode terminal to the center of the electrode terminal on the mounting board, and FIG. 3 shows the state after mounting.

図示したように、半導体素子１にはその表面から突出し
て複数のバンプ２が形成されている。As shown in the figure, a plurality of bumps 2 are formed on the semiconductor element 1 so as to protrude from the surface thereof.

他方、半導体素子１が実装される実装基板３には、半導
体素子１上のバンプ２に対応して複数の電極端子５が形
成されている。この電極端子５はその表面にバンプ２の
少なくとも頂部を受容する凹部４を有している。この凹
部４は外周部から中心部に向かって徐々に深くなるよう
に形成されており、該中心部が最も深くなっている。電
極端子５は、例えば次のようにして形成される。まず、
実装基板３の電極端子５が形成される部分に窪みを形成
する。この窪みは半導体素子１上に形成されて．いるバ
ンプ２の少なくとも頂部（図では下端部）を受容し得る
程度の大きさに形成される。そして、この窪みに選択的
に金属メッキや真空蒸着等を施して電極端子５が形成さ
れる。このようにして形成された電極端子５は、その表
面にバンプ２の少なくとも頂部を受容する凹部４を有す
ることとなる。なお、電極端子５は中央部５ａとその外
周部５ｂとが別々に形成され、中央部５ａは外周部５ｂ
を形成する金属よりも融点が低い金属で形成されている
。本実施例では、中央部５ａをＡ　ｕ　／　２　０％Ｓ
ｎの合金で形成し、外周部５ｂをＡｕで形成している。On the other hand, a plurality of electrode terminals 5 are formed on the mounting substrate 3 on which the semiconductor element 1 is mounted, corresponding to the bumps 2 on the semiconductor element 1. The electrode terminal 5 has a recess 4 on its surface for receiving at least the top of the bump 2. The recess 4 is formed so as to become gradually deeper from the outer periphery toward the center, and is deepest at the center. The electrode terminal 5 is formed, for example, as follows. first,
A depression is formed in a portion of the mounting board 3 where the electrode terminal 5 is to be formed. This depression is formed on the semiconductor element 1. The bump 2 is formed in a size large enough to receive at least the top (lower end in the figure) of the bump 2. Then, the electrode terminal 5 is formed by selectively applying metal plating, vacuum deposition, etc. to this depression. The electrode terminal 5 thus formed has a recess 4 on its surface that receives at least the top of the bump 2. Note that the electrode terminal 5 has a central portion 5a and an outer peripheral portion 5b formed separately, and the central portion 5a is formed separately from the outer peripheral portion 5b.
It is made of a metal that has a lower melting point than the metal that forms it. In this embodiment, the central portion 5a is A u / 20%S
The outer peripheral portion 5b is made of Au.

このように形成された実装基板３に対して、半導体素子
１を実装する場合、半導体素子１上のバンプ２と実装基
板３上の電極端子５との位置合せが図示しない位置合せ
装置により行われるが、この位置合せは、第１図に示し
たように、バンプ２の頂部が電極端子５の凹部４内から
はみ出さない程度の大まかな位置合せで足りる。なぜな
ら、バンプ２の頂部が電極端子５の凹部４内に納まる範
囲内に位置合せされていれば、この位置合せの後に半導
体素子１を実装基板３に対して軽く押し付けることによ
り、バンプ２は電極端子５の凹部４の表面に沿って案内
され、凹部４の中心部に向かって自動的に移動するから
である。しかしながら、バンプ２と電極端子５の間には
摩擦力が作用するため、第２図に示したように、バンプ
２は電極端子５の中心から若干ずれた位置にて停止して
しまう。このバンプ２が停止する位置を含むように低融
点金属で電極端子５の中央部５ａを形成しておけば、実
装基板３をホットプレート６等により加熱し電極端子５
の中央部５ａを溶融させることにより、溶融した金属の
表面張力がバンプ２に作用し、この表面張力によりバン
プ２はさらに電極端子５の中心部に向かって誘導される
。したがって、第３図に示したように、非常に高い精度
でバンプ２が電極端子５の中心部に位置合せされる。な
お、表面張力は溶融金属の表面積をできるだけ小さくす
るように作用する。したがって、この表面張力により半
導体素子１上の各バンプ２と実装基板３上の各電極端子
５との総合的な位置ズレが最小となるように、半導体素
子１は実装基板３に対して位置合せされる。When mounting the semiconductor element 1 on the mounting board 3 formed in this way, the bumps 2 on the semiconductor element 1 and the electrode terminals 5 on the mounting board 3 are aligned by an alignment device (not shown). However, as shown in FIG. 1, this alignment only needs to be rough enough that the top of the bump 2 does not protrude from the recess 4 of the electrode terminal 5. This is because if the top of the bump 2 is aligned within the range that fits within the recess 4 of the electrode terminal 5, then by lightly pressing the semiconductor element 1 against the mounting board 3 after this alignment, the bump 2 can be placed in the electrode terminal 5. This is because the terminal 5 is guided along the surface of the recess 4 and automatically moves toward the center of the recess 4. However, since a frictional force acts between the bump 2 and the electrode terminal 5, the bump 2 ends up stopping at a position slightly offset from the center of the electrode terminal 5, as shown in FIG. If the central part 5a of the electrode terminal 5 is formed of a low-melting point metal so as to include the position where the bump 2 stops, the mounting board 3 can be heated with a hot plate 6 or the like, and the electrode terminal 5 can be heated by using a hot plate 6 or the like.
By melting the center portion 5a of the electrode terminal 5, the surface tension of the molten metal acts on the bump 2, and the bump 2 is further guided toward the center of the electrode terminal 5 by this surface tension. Therefore, as shown in FIG. 3, the bump 2 is aligned with the center of the electrode terminal 5 with very high precision. Note that surface tension acts to minimize the surface area of molten metal. Therefore, due to this surface tension, the semiconductor element 1 is aligned with the mounting board 3 so that the overall positional deviation between each bump 2 on the semiconductor element 1 and each electrode terminal 5 on the mounting board 3 is minimized. be done.

しかしながら、実装基板３をホットプレート６等により
加熱する場合、その温度管理は非常に難しい。このため
、実装基板３の加熱により電極端子５全体が溶融してし
まったり、電極以外の配線部までが溶融してしまうこと
がある。このように、電極端子５の中央部５ａ以外の部
分までが溶融してしまうと、表面張力が上述したように
作用しなくなり、バンプ２が電極端子５の凹部中央部に
納まらなくなったり、溶融した電極材料がはみ出して隣
接する電極同士を短絡させてしまうおそれがある。これ
を防止するため、本発明においては、実装基板３を加熱
しながら、実装基板３の電極端子５が形成されている表
面に冷却用のガスを吹き付けることとしている。このよ
うに、ガスを吹き付け実装基板表面を冷却することによ
り、実装基板３の表層における温度勾配を大きくするこ
とができる。この場合に、電極端子５の中央部５ａは窪
んでいるので、冷却ガスが当たり難く、また、温度勾配
の高温側に位置しているので、電極端子５はその凹部中
央部のみが他の部分に比較して高温になる。したがって
、電極端子５の中央部５ａの低融点金属のみが確実に溶
融され、その表面張力によりバンプ２が電極端子５の中
心部に向かって確実に誘導される。なお、冷却用ガスと
しては、Ｎ２ガス等の不活性ガスを用いることが好まし
い。However, when the mounting board 3 is heated by the hot plate 6 or the like, temperature control is very difficult. For this reason, the entire electrode terminal 5 may melt due to heating of the mounting board 3, or even the wiring portion other than the electrode may melt. In this way, if the parts other than the center part 5a of the electrode terminal 5 are melted, the surface tension will no longer act as described above, and the bump 2 will not be able to fit into the center of the recess of the electrode terminal 5, or the melted part will not work. There is a risk that the electrode material may protrude and short-circuit adjacent electrodes. In order to prevent this, in the present invention, while heating the mounting board 3, cooling gas is blown onto the surface of the mounting board 3 on which the electrode terminals 5 are formed. In this way, by cooling the surface of the mounting board by blowing gas, the temperature gradient in the surface layer of the mounting board 3 can be increased. In this case, since the central part 5a of the electrode terminal 5 is recessed, it is difficult for the cooling gas to come into contact with it, and since it is located on the high temperature side of the temperature gradient, the electrode terminal 5 has only the recessed central part apart from other parts. The temperature will be higher than that of Therefore, only the low melting point metal in the center portion 5a of the electrode terminal 5 is reliably melted, and the bump 2 is reliably guided toward the center portion of the electrode terminal 5 due to its surface tension. Note that as the cooling gas, it is preferable to use an inert gas such as N2 gas.

また、その吹き付けは、第２図にも示したように、実装
基板３と半導体素子１とが互いに向かい合わされている
ので、必然的に実装基板側方から半導体素子１と実装基
板３との相互間に吹き込むようにして行われる。実装基
板３に吹き付けられる冷却用ガスの温度は、常温で十分
であるが、このガスの温度及び吹き付け量を調節するこ
ととすれば、これにより実装基板３表面の温度を調節す
ることも可能である。Moreover, as shown in FIG. 2, since the mounting board 3 and the semiconductor element 1 are facing each other, the spraying is inevitably applied to the semiconductor element 1 and the mounting board 3 from the side of the mounting board. It is done by blowing in between. Room temperature is sufficient for the temperature of the cooling gas sprayed onto the mounting board 3, but by adjusting the temperature and spray amount of this gas, it is also possible to adjust the temperature of the surface of the mounting board 3. be.

半導体素子１上に形成されるバンプ２のサ”イズを直径
８０μｍ１高さ約３０μｍとし、また、実装基板３上の
電極端子５のサイズを直径１００μｍとして、半導体素
子１を実装基板３に実装した。この場合に、実装後のバ
ンプ２と電極端子５の位置ズレを±５μｍ以内に納める
ために、位置合せ装置に要求される位置合せ精度は±５
０μｍであった。これに対して、上述の例と同寸法の平
坦な電極端子が形成された従来の実装基板に、上述した
例と同じ半導体素子を実装したところ、位置合せ装置に
要求される精度は±５μｍであった。The semiconductor element 1 was mounted on the mounting board 3 with the size of the bumps 2 formed on the semiconductor element 1 being 80 μm in diameter and approximately 30 μm in height, and the size of the electrode terminals 5 on the mounting board 3 being 100 μm in diameter. In this case, in order to keep the positional deviation between the bump 2 and the electrode terminal 5 after mounting within ±5 μm, the alignment accuracy required of the alignment device is ±5 μm.
It was 0 μm. In contrast, when the same semiconductor element as in the above example was mounted on a conventional mounting board on which flat electrode terminals with the same dimensions as in the above example were formed, the accuracy required for the alignment device was ±5 μm. there were.

この結果を下表に示す。The results are shown in the table below.

また、実装基板３の表面に冷却用ガスを吹き付けた場合
と、吹き付けなかった場合の実装基板表ところで、上述
した実施例においては、実装基板３の上電極端子５の中
央部５ａが低融点金属で形成されているが、電極端子５
全体を融点が比較的高い金属で形成し、その凹部の中央
部表面に低融点金属層をメッキ等により形成しておいて
もよい。In addition, the mounting board table shows the case where the cooling gas is sprayed onto the surface of the mounting board 3 and the case where it is not sprayed.In the above-mentioned embodiment, the center part 5a of the upper electrode terminal 5 of the mounting board 3 is made of a low melting point metal. The electrode terminal 5
The entire structure may be made of a metal having a relatively high melting point, and a low melting point metal layer may be formed on the surface of the central portion of the recessed portion by plating or the like.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば従来のように高精
度で高価な位置合せ装置を必要とせず、比較的安価な位
置合せ装置を用いることができる。As described above, according to the present invention, a relatively inexpensive alignment device can be used instead of requiring a highly accurate and expensive alignment device as in the prior art.

また、位置合せ装置による位置合せは、大まかなもので
足りるので、位置合せ装置による精密な位置合せを必要
としていた従来に比し、位置合せ装置による位置合せに
必要とされる時間が短くなる．したがって、実装に要す
る時間及びコストを低減することができる。Furthermore, since only rough alignment is required by the alignment device, the time required for alignment by the alignment device is shorter than in the past, which required precise alignment by the alignment device. Therefore, the time and cost required for implementation can be reduced.

さらに、冷却用ガスにより半導体素子の温度上昇が抑え
られるので、実装時に半導体素子が熱によるダメージを
受けることを防止できる。Furthermore, since the temperature rise of the semiconductor element is suppressed by the cooling gas, it is possible to prevent the semiconductor element from being damaged by heat during mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明が適用される実装基板とその電極端子に
対して大まかに位置合せされた半導体素子とを示した図
、第２図は半導体素子上のバンプが実装基板上の電極端
子の中心部に移動する途中の状態を示した図、第３図は
それらの実装後の状態を示した図である。 １・・・半導体素子、２・・・バンプ、３・・・実装基
板、４・・・凹部，５・・・電極端子、５ａ・・・中央
部、５ｂ・・・外周部、６・・・ホットプレート。Figure 1 shows a mounting board to which the present invention is applied and a semiconductor element roughly aligned with its electrode terminals, and Figure 2 shows bumps on the semiconductor element aligned with electrode terminals on the mounting board. FIG. 3 is a diagram showing the state in the middle of moving to the center, and FIG. 3 is a diagram showing the state after they are mounted. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Bump, 3... Mounting board, 4... Recessed part, 5... Electrode terminal, 5a... Center part, 5b... Outer periphery part, 6... ·Hot plate.

Claims (1)

【特許請求の範囲】 半導体素子の表面に形成されたバンプを実装基板上の電
極端子に直接接続して前記半導体素子を前記実装基板上
に実装する方法であって、 前記電極端子に前記バンプの頂部を受容する凹部を形成
すると共に、前記凹部の少なくとも中央部に低融点金属
を配しておき、 前記実装基板を加熱すると共に、前記実装基板の表面に
冷却用ガスを吹き付けることを特徴とする半導体素子の
実装方法。[Scope of Claims] A method for mounting the semiconductor element on the mounting substrate by directly connecting bumps formed on the surface of the semiconductor element to electrode terminals on the mounting substrate, the method comprising: connecting the bumps formed on the surface of the semiconductor element to the electrode terminals on the mounting substrate; A recess is formed to receive the top, and a low melting point metal is arranged at least in the center of the recess, and the mounting board is heated and a cooling gas is blown onto the surface of the mounting board. A method for mounting semiconductor elements.
JP2013416A 1990-01-23 1990-01-23 Mounting method of semiconductor element Pending JPH03218038A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2013416A JPH03218038A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element
CA002034700A CA2034700A1 (en) 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device
AU69823/91A AU637874B2 (en) 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device
EP91100821A EP0439137A2 (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device, packaging structure and method
KR1019910001105A KR950001368B1 (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device, packaging structure and method
US07/644,846 US5196726A (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device having particular terminal and bump structure
US07/993,006 US5298460A (en) 1990-01-23 1992-12-18 Substrate for packaging a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013416A JPH03218038A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element

Publications (1)

Publication Number Publication Date
JPH03218038A true JPH03218038A (en) 1991-09-25

Family

ID=11832532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013416A Pending JPH03218038A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element

Country Status (1)

Country Link
JP (1) JPH03218038A (en)

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