JPS6197932A - Compression bonded semiconductor package - Google Patents
Compression bonded semiconductor packageInfo
- Publication number
- JPS6197932A JPS6197932A JP59218411A JP21841184A JPS6197932A JP S6197932 A JPS6197932 A JP S6197932A JP 59218411 A JP59218411 A JP 59218411A JP 21841184 A JP21841184 A JP 21841184A JP S6197932 A JPS6197932 A JP S6197932A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- silicon chip
- crimp
- alumina ceramic
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
- H01L2224/14051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体基体と誘電体基板間を電気的に結合した
圧着型半導体パンケージに係り、特に圧着のだめの加圧
及び圧着端子の正確な位置合せを必要としない圧着型半
導体パッケージに関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a crimp-type semiconductor pancage that electrically connects a semiconductor substrate and a dielectric substrate, and particularly relates to pressurization of a crimp receptacle and accurate positioning of crimp terminals. This invention relates to a crimp-type semiconductor package that does not require.
半導体集積回路は近年ますます高密度化、高集積化に拍
車がかかり、ＬＳＩチップ（半導体基体）は大型化の傾
向が著しい。従来はＬＳＩチップと誘電体基板間ははん
だで接続されていたが、ＬＳＩチップの大型化によりＬ
ＳＩチップと誘電体基板の熱膨張係数の差に基づく熱疲
労破壊がクローズアップされるようにな！１７、ＬＳＩ
チップと誘電体基板の熱膨張係数の差に基づく熱疲労破
壊が原理的に発生しないパンケージ構造の一つとして圧
着型パッケージ構造が提案されはじめている。In recent years, semiconductor integrated circuits have become increasingly dense and highly integrated, and LSI chips (semiconductor substrates) are becoming larger. Conventionally, LSI chips and dielectric substrates were connected by solder, but as LSI chips became larger, LSI
Thermal fatigue failure due to the difference in thermal expansion coefficient between SI chips and dielectric substrates has come under close scrutiny! 17.LSI
A crimp-type package structure has begun to be proposed as a type of package structure that, in principle, does not cause thermal fatigue failure due to the difference in coefficient of thermal expansion between the chip and the dielectric substrate.
圧着型パンケージ構造は大電力を扱う電力用半導体装置
ではよく用いられる構造であるが、ＬＳＩチップと誘電
体基板の結合に適用する考えはまだ一般的でなく、わず
かに特開昭５６−１４２６６０号公報に示されているに
すぎない。The crimp-type pancage structure is a structure that is often used in power semiconductor devices that handle large amounts of power, but the idea of applying it to the connection between an LSI chip and a dielectric substrate is still not common, and the idea of applying it to the connection between an LSI chip and a dielectric substrate is still not common, and the idea is that it is only used in Japanese Patent Application Laid-Open No. 56-142660. It is only indicated in the official gazette.
圧着型パッケージ構造の特長は、ＬＳＩチップと誘電体
基板の各々に設けられた圧着端子が圧着されている接続
部が接着されていないためにＬＳＩチップと誘電体基板
の熱膨張係数の差に基づく熱疲労破壊が原理的に発生し
ない点であるが、その反面圧着端子間の接触を保つため
に何らかの手段で加圧することが必須であり、このこと
がパンケージ構造を複雑にし、実用化の妨げＫなってい
る。The feature of the crimp type package structure is based on the difference in thermal expansion coefficient between the LSI chip and the dielectric substrate because the connection parts where the crimp terminals provided on each of the LSI chip and the dielectric substrate are crimped are not bonded. Although thermal fatigue failure does not occur in principle, it is necessary to apply pressure by some means to maintain contact between crimp terminals, which complicates the pan cage structure and hinders practical application. It has become.
従来はこの点に関する認識があまり充分でなかった。そ
のため上記公知従来例でも加圧をＬＳＩチップの背面か
ら行なう構造を採用しておシ、上記したパッケージ構造
の複雑化への対応は不光分であった。Until now, there was not enough awareness regarding this point. For this reason, the above-mentioned conventional example also adopts a structure in which pressure is applied from the back side of the LSI chip, and it is difficult to cope with the above-mentioned complexity of the package structure.
本発明の目的は圧着型半導体パッケージにおいて、圧着
のための加圧及び圧着端子の正確な位置合せを必要とし
ない圧着型半導体パッケージを提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a crimp-type semiconductor package that does not require pressurization for crimping and accurate positioning of crimp terminals.
本発明の圧着型半導体パッケージは、圧着端子に加えて
圧着のための加圧及び圧着端子の正確な位置合せを自動
的に行なうために複数個の微小はんだ群による接続端子
を併用し、半導体基体と誘電体基板間を電気的かつ機械
的に結合していることを特徴とする。The crimp-type semiconductor package of the present invention uses, in addition to crimp terminals, connection terminals made of a plurality of micro-solder groups in order to automatically apply pressure for crimp bonding and accurately align the crimp terminals. The dielectric substrate is electrically and mechanically coupled to the dielectric substrate.
一般に、はんだ（例えば鉛−錫合金、鉛−インジウム合
金、錫−銀合金等）で代表される低融点金属は圧着端子
用材料として好適な比較的高融点の金′属（金、銅、銀
、アルミニウム等）よりも熱膨張係数が太きい。In general, low melting point metals represented by solders (e.g. lead-tin alloys, lead-indium alloys, tin-silver alloys, etc.) are metals with relatively high melting points (gold, copper, silver, etc.) that are suitable as materials for crimp terminals. , aluminum, etc.).
本発明者らはこの点に着目し、本発明では比較的高融点
の金属による圧着端子の加圧力をはんだと比較的高融点
の金属との熱膨張係数差によυ得ている。すなわち、は
んだの融点以上で圧着端子を接触させ、そのままの状態
を保ちながら常温まで冷却することによって圧着端子へ
の加圧力がはんだと比較的高融点の圧着端子金属との熱
膨張係数差により発生するのである。The present inventors have focused on this point, and in the present invention, the pressing force of the crimp terminal made of a metal with a relatively high melting point is obtained by the difference in coefficient of thermal expansion between the solder and the metal with a relatively high melting point. In other words, by bringing the crimp terminal into contact at a temperature above the melting point of the solder and cooling it to room temperature while maintaining that state, the pressure applied to the crimp terminal is generated due to the difference in coefficient of thermal expansion between the solder and the crimp terminal metal, which has a relatively high melting point. That's what I do.
さらに、この構造ではばんだの溶融時にはんだの表面張
力によって自動的に圧着端子の相対位置が正確に合わせ
られるという利点も合わせもっている。Furthermore, this structure also has the advantage that the relative positions of the crimp terminals are automatically adjusted accurately by the surface tension of the solder when the solder melts.
本発明の一実施例を第１図に従って説明する。 An embodiment of the present invention will be described with reference to FIG.
第１図に示すように、本発明による圧着型半導体パッケ
ージはアルミナセラミック基板（誘電体基板）５とシリ
コンチップ（半導体基板）１とを複数個のシリコンチッ
プ側圧着端子２とアルミナセツミック基板側圧着端子３
の相互接触及び複数個のけんだ４による接続を併用する
ことにより電気的及び機械的に結合した構造体である。As shown in FIG. 1, the crimp type semiconductor package according to the present invention connects an alumina ceramic substrate (dielectric substrate) 5 and a silicon chip (semiconductor substrate) 1 to a plurality of crimp terminals 2 on the silicon chip side and on the alumina ceramic substrate side. Crimp terminal 3
It is a structure that is electrically and mechanically coupled by using mutual contact between the two and connection by a plurality of solders 4.
はんだ４により結合させるためにシリコンチップｌ及び
アルミナセラミック基板５にはそれぞれシリコンチップ
側はんだ行電極６及びアルミナセラミック基板側はんだ
行電極７が形成されている。For bonding by solder 4, a silicon chip side solder row electrode 6 and an alumina ceramic substrate side solder row electrode 7 are formed on the silicon chip 1 and the alumina ceramic substrate 5, respectively.
本発明の実施例ではシリコンチップ１の寸法は一辺Ｌｏ
ｚの正方形、シリコンチップ側圧着端子２及びアルミナ
セラミック基板側圧着端子３はシリコンチップｌの周辺
にのみ配置し、その数は一辺当９２０個、合計８０個、
はんだ４の数はシリコンチップ中央部に４個、シリコン
チップ側圧着端子２及びアルミナセラミック基板側圧着
端子３はいずれも直径２００μｍ１最小ピッチ４００μ
ｍ１高さ５０μｍ１シリコンチツプ側はんだ行電極６及
びアルミナセラミック基板側はんだ行電極７はいずれも
直径２００μｍ１ピツチ４００μｍ、一体化後のシリコ
ンチップ１とアルミナセラミック基板５０間隙はシリコ
ンチップ側圧着端子２とアルミナセラミック基板側圧着
端子３の高さの合計に等しく、１００μｍである。In the embodiment of the present invention, the size of the silicon chip 1 is Lo on one side.
Z square, silicon chip side crimp terminals 2 and alumina ceramic substrate side crimp terminals 3 are arranged only around the silicon chip l, the number is 920 per side, 80 in total,
The number of solders 4 is 4 at the center of the silicon chip, and the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate side are both 200 μm in diameter and 400 μm in minimum pitch.
m1 height 50 μm1 Silicon chip side solder row electrode 6 and alumina ceramic substrate side solder row electrode 7 both have a diameter of 200 μm and 1 pitch of 400 μm, and the gap between silicon chip 1 and alumina ceramic substrate 50 after integration is between silicon chip side crimp terminal 2 and alumina ceramic substrate 50. It is equal to the total height of the crimp terminals 3 on the ceramic substrate side, which is 100 μm.
ここで、本発明による半導体パッケージの製造工程につ
いて第２図に従って説明する。Here, the manufacturing process of the semiconductor package according to the present invention will be explained with reference to FIG.
第２図（ａ）に示すように、内部の回路を形成した後、
金のめつきによシリコンチップ側圧着端子２が形成され
、シリコンチップ側はんだ（鉛９５重量％、錫５重量％
）８がシリコンチップ側はんだ行電極６の上に形成され
たシリコンチップ１を、すでに金のめつきによりアルミ
ナセラミック基板側圧着端子３が形成され、グリーンシ
ート法によシアルミナセラミック基板側はんだ行電極７
、その表面には印刷されたはんだの再溶融により鉛９５
重量％、錫５重量％のアルミナセラミック基板側はんだ
９が形成されたアルミナセラミック基板５に対向させ、
ハーフミラ−を用いて位置合せする。As shown in FIG. 2(a), after forming the internal circuit,
The silicon chip side crimp terminal 2 is formed by gold plating, and the silicon chip side solder (lead 95% by weight, tin 5% by weight)
) 8 is a silicon chip 1 formed on a solder row electrode 6 on the silicon chip side, which has already been plated with gold to form a crimp terminal 3 on the alumina ceramic substrate side, and is attached to a solder row on the sialumina ceramic substrate side using the green sheet method. Electrode 7
, the surface is made of lead 95 by remelting the printed solder.
% by weight, facing an alumina ceramic substrate 5 on which an alumina ceramic substrate-side solder 9 containing 5% by weight of tin was formed,
Align using a half mirror.
次に第２図（ｂ）に示すように、シリコンチップ１とア
ルミナセラミック基板５がシリコンチップ側はんだ８と
アルミナセラミック基板側はんだ９とで接触した状態で
は位置合せ精度の関係からシリコンチップ側圧着端子２
とアルミナセラミック基板側圧着端子３は相対的に少し
位置ずれしているのが通例である。ここでシリコンチッ
プ側はんだ８の体積を６〜９ＸＩＯ−’ｍｍ”として、
シリコンチップ側圧着端子２とアルミナセラミック基板
側圧着端子３が接触しないようにする。Next, as shown in FIG. 2(b), when the silicon chip 1 and the alumina ceramic substrate 5 are in contact with the silicon chip side solder 8 and the alumina ceramic substrate side solder 9, the silicon chip side is crimped due to alignment accuracy. terminal 2
It is normal for the crimp terminals 3 on the alumina ceramic substrate side to be slightly misaligned relative to each other. Here, assuming that the volume of the solder 8 on the silicon chip side is 6 to 9XIO-'mm'',
The crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate side are prevented from coming into contact with each other.
更に第２図（Ｃ）に示すようにこの状態で炉中で鉛９５
重量％、錫５重量−のはんだの液相温度よシ少し高い温
度（３５０Ｃ）まで加熱するとはんだの表面張力によシ
少しずれていたシリコンチップ側圧着端子２とアルミナ
セラミック基板側圧着端子３との相対位置が正確に合う
（自己整合）。その時点で図に示すようにシリコンチッ
プ１の裏面からばね１１による加圧力を加圧部材１０．
１２を介して加える。このままではんだ４の融点以下ま
で冷却すると、熱膨張係数の差によシリコンチップ側圧
着端子２とアルミナセラミック基板側圧着端子３の間に
加圧力が働き、第１図に示すようなパンケージ構造が完
成する。Furthermore, as shown in Figure 2 (C), 95% lead is added in the furnace in this state.
When heated to a temperature slightly higher than the liquidus temperature (350C) of the solder containing 5% by weight of tin, the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate side were slightly misaligned due to the surface tension of the solder. The relative positions of the two match exactly (self-alignment). At that point, as shown in the figure, the pressure applied by the spring 11 is applied from the back surface of the silicon chip 1 to the pressure member 10.
Add via 12. If the solder 4 is cooled down to below its melting point, pressure will be applied between the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate due to the difference in thermal expansion coefficients, resulting in a pan cage structure as shown in Fig. 1. Complete.
この構造ではシリコンチップ１とアルミナセラミック基
板５の熱膨張係数の差にもとづく熱疲労が懸念されるシ
リコンチップ１周辺部ではシリコンチップ１とアルミナ
セラミック基板５が自由に伸縮でき、熱応力が発生しな
い圧着構造（シリコンチップ側圧着端子２とアルミナセ
ラミック基板側圧着端子３は接触しているだけで接着は
していない）をとっているため、熱疲労は問題にならな
い。しかも、シリコンチップ１とアルミナセラミック基
板５の熱膨張係数の差によシ熱疲労が発生する可能性の
ある接着構造はシリコンチップ１の中央部のシリコンチ
ップ１とアルミナセラミック基板５の相対的な変位の少
ない領域に限られており、はんだ４による接着部も電気
的な接続点として充分の信頼性を確保している。はんだ
４を配置する領域はシリコンテップ１の中央を中心とす
る直径５簡の円内であれば光分な信頼性を確保できる。In this structure, the silicon chip 1 and the alumina ceramic substrate 5 can freely expand and contract in the area around the silicon chip 1, where thermal fatigue due to the difference in thermal expansion coefficient between the silicon chip 1 and the alumina ceramic substrate 5 is a concern, and no thermal stress is generated. Since the crimp structure is adopted (the crimp terminal 2 on the silicon chip side and the crimp terminal 3 on the alumina ceramic substrate side are only in contact but not bonded), thermal fatigue is not a problem. Moreover, the bonding structure that may cause thermal fatigue due to the difference in thermal expansion coefficient between the silicon chip 1 and the alumina ceramic substrate 5 is due to the relative difference between the silicon chip 1 and the alumina ceramic substrate 5 in the center of the silicon chip 1. It is limited to a region with little displacement, and the bonded portion by the solder 4 also ensures sufficient reliability as an electrical connection point. Optical reliability can be ensured as long as the area where the solder 4 is placed is within a circle with a diameter of 5 squares centered on the center of the silicon tip 1.
本発明の他の実施例を第３図に従って説明する。Another embodiment of the present invention will be described with reference to FIG.
第３図に示すように、本実施例では第１図に示した実施
例と異なシ、シリコンチップ１の周辺部（正確には四隅
の４個所）にはんだ４を配置した。As shown in FIG. 3, this embodiment differs from the embodiment shown in FIG. 1 in that solder 4 is placed around the periphery of the silicon chip 1 (more precisely, at four corners).
シリコンチップ１の寸法、シリコンチップ側圧着端子２
及びアルミナセラミック基板側圧着端子３の寸法及びピ
ッチ、また、製造プロセスは第１図及び第２図に示した
実施例と同じであるためここでは省略する。Dimensions of silicon chip 1, crimp terminal 2 on silicon chip side
The dimensions and pitch of the crimp terminals 3 on the alumina ceramic substrate side and the manufacturing process are the same as those in the embodiment shown in FIGS. 1 and 2, and therefore will not be described here.
この構造の先に述べた実施例に対する利点を以下に列挙
する。The advantages of this structure over the previously described embodiments are listed below.
（Ｉ）第２図（ｂ）のプロセスにおいて、シリコンチッ
プ側はんだ８のはんだ量がばらついた場合を想定する。(I) In the process shown in FIG. 2(b), assume that the amount of solder 8 on the silicon chip side varies.
このプロセスでは（イ）シリコンチップ側圧着端子２と
アルミナセラミック基板側圧着端子３が絶対に接触しな
いこと、（ｏ）シリコンチップ側はんだ８とアルミナセ
ラミック基板側はんだ９が必ず接触すること、の両条件
を同時に満足しなければならないが、第４図（ａ）に示
すように先に述べた実施例においてシリコンチップ側は
んだ８１が５×１０−’＋＋ｍ”、シリコンチップ側は
んだ８２が９×１０″″４削３の場合にはシリコンチッ
プ側圧着端子２とアルミナセラミック基板側圧着端子３
が接触する部分があり、しかもシリコンチップ側はんだ
８１がアルミナセラミック基板側はんだ９に接触してい
ないという問題点がある。これに対して、第４図（ｂ）
ではシリコンチップ側まんだ８３のはんだ量をシリコン
チップ側はんだ８１と同じ５Ｘ１０−’ｍ’、シリコン
チップ側ばんだ８４のはんだ量をシリコンチップ側はん
だ８２と同じ９Ｘ １０−−’ ｍ” としても（イ）
と（ロ）の条件を同時に満足している。In this process, (a) the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate never come into contact, and (o) the solder 8 on the silicon chip side always comes into contact with the solder 9 on the alumina ceramic substrate side. The conditions must be satisfied at the same time, but as shown in FIG. 4(a), in the above-mentioned embodiment, the silicon chip side solder 81 is 5 x 10-'++ m'', and the silicon chip side solder 82 is 9 x 10 In the case of ``4 cut 3'', crimp terminal 2 on the silicon chip side and crimp terminal 3 on the alumina ceramic board side.
However, there is a problem in that the solder 81 on the silicon chip side is not in contact with the solder 9 on the alumina ceramic substrate side. On the other hand, Fig. 4(b)
Now, let's assume that the amount of solder on the silicon chip side solder 83 is the same as the silicon chip side solder 81, 5X10-'m'', and the amount of solder on the silicon chip side solder 84 is the same as the silicon chip side solder 82, 9X 10-'m". (stomach)
and (b) are satisfied at the same time.
このように、本実施例ではシリコンチップ側はんだ８の
はんだ量の許容範囲が大きい（４〜９×１０″’ ｍｍ
” 、先に述べた実施例では６〜９×１０−’＋ｍ３
）。As described above, in this embodiment, the allowable range of the amount of solder 8 on the silicon chip side is large (4 to 9 x 10'' mm
”, in the embodiment described above, 6 to 9×10−′+m3
).
（ｔｌ）はんだ４の位置がシリコンチップ１の中心から
離れているだめ、はんだ４による自己整合時に働くモー
メントが大きく、第２図の（２）から第２図の（３）Ｆ
−至る過程ではんだ４による自己整合（自動位置合せ）
が先に述べた実施例よりもより確実に行なわれる。(tl) Since the position of the solder 4 is far from the center of the silicon chip 1, the moment acting during self-alignment by the solder 4 is large, and from (2) in Fig. 2 to (3) F in Fig. 2
- Self-alignment (automatic alignment) by solder 4 in the process
is performed more reliably than in the previously described embodiments.
これらの実施例から、当然のことながら、シリコンチッ
プｌの中央部と周辺部にばんだ４を配置した構造あるい
はシリコンチップ１内の中央部、周辺部にかかわらずは
んだ４を均一にあるいは不均一に配置し７１ｃ構造もあ
りうることは簡単に類推できる。しかも、はんだ４によ
りシリコンチップ側圧着端子２、アルミナセラミック基
板側圧着端子３の間にＧａｐを与える必要性からはんだ
４の数は１個のシリコンチップ１につき最低３個必要な
ことも明白である。From these examples, it is obvious that the structure in which the solder 4 is arranged at the center and the periphery of the silicon chip 1 or the structure in which the solder 4 is arranged uniformly or unevenly in the center and the periphery of the silicon chip 1 It can be easily inferred that a 71c structure is also possible. Furthermore, it is clear that the number of solders 4 is at least three per silicon chip 1 because it is necessary to provide a gap between the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate side by the solder 4. .
また、はんだ４はシリコンチップ側圧着端子２、アルミ
ナセラミック基板側圧着端子３の熱膨張係数より大きい
材質であれば鉛９５重量％、錫５重量％に限らず、鉛−
錫系、錫−銀系、金−錫系、錫−ビスマス系、鉛−イン
ジウム系等、一般に用いられているはんだ材から適当に
選んでもよい。In addition, if the solder 4 is made of a material with a coefficient of thermal expansion larger than that of the crimp terminal 2 on the silicon chip side and the crimp terminal 3 on the alumina ceramic substrate side, the solder 4 is not limited to 95% by weight of lead and 5% by weight of tin.
The solder material may be appropriately selected from commonly used solder materials such as tin-based, tin-silver-based, gold-tin-based, tin-bismuth-based, lead-indium-based, etc.
また、シリコンチップ側圧着端子２、アルミナセラミッ
ク基板側圧着端子３は金に限らずはんだ４の熱膨張係数
より小さい材質であれば銀、銅、アルミニウム等、さら
にこれら同志またはこれらと池の材料との複合材料であ
ってもよいことも自明である。In addition, the crimp terminals 2 on the silicon chip side and the crimp terminals 3 on the alumina ceramic substrate side are not limited to gold, but may be made of silver, copper, aluminum, etc. as long as they have a coefficient of thermal expansion smaller than that of the solder 4. It is also obvious that the material may be a composite material.
次に、アルミナセラミック基板５の材質はアルミナセラ
ミックに限らず、誘電体であれば有機樹脂、無機セラミ
ック（Ｓ ｉｃ、 ＳｉＮ、ムライト等１、ガラス等で
もよいことも明らかである。Next, it is clear that the material of the alumina ceramic substrate 5 is not limited to alumina ceramic, but may be any dielectric material such as organic resin, inorganic ceramic (SiC, SiN, mullite, etc.1), glass, etc.
本発明によれば、複数個の微小はんだ群による接続端子
を圧着端子と併用することにより、圧着のための加圧及
び圧着端子の正確な位置合せが自動的に行なわれ、半導
体基体と誘電体基板間を電気的かつ機械的に結合した圧
着型半導体パッケージを得ることができる。According to the present invention, by using a connection terminal made of a plurality of micro solder groups together with a crimp terminal, pressure for crimping and accurate positioning of the crimp terminal are automatically performed, and the semiconductor substrate and dielectric A crimp-type semiconductor package in which the substrates are electrically and mechanically coupled can be obtained.
第１図は本発明による一実施例を示す断面図、第２図（
ａ）〜（Ｃ）は第１図に示した本発明による実施例の製
造工程を示す断面図、第３図は本発明による他の実施例
を示す断面図、第４図（ａ）（ｂ）は、第１図、第３図
に示す実施例におけるはんだによる結合状況を示す図で
ある。
１・・・シリコンチップ、２・・・シリコンチップ側圧
着端子、３・・・アルミナセラミック基板側圧着端子、
４・・・はんだ、５・・・アルミナセラミック基板。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 (
a) to (C) are cross-sectional views showing the manufacturing process of the embodiment according to the present invention shown in FIG. 1, FIG. 3 is a cross-sectional view showing another embodiment according to the present invention, and FIGS. ) is a diagram showing a state of solder connection in the embodiment shown in FIGS. 1 and 3. 1... Silicon chip, 2... Silicon chip side crimp terminal, 3... Alumina ceramic substrate side crimp terminal,
4...Solder, 5...Alumina ceramic board.
Claims (1)
群により電気的に結合する圧着型半導体パッケージにお
いて、該微小圧着端子群に加えて該半導体基体と該誘電
体基板の間に３個以上の微小はんだ群を配置したことを
特徴とする圧着型半導体パッケージ。 ２、特許請求の範囲第１項において、該微小はんだ群の
配置される領域が該半導体基体の中央を中心とし、直径
５ｍｍの円内であることを特徴とする圧着型半導体パッ
ケージ。 ３、特許請求の範囲第１項において、該微小はんだ群の
配置される領域が該半導体基体の周辺部の四隅であるこ
とを特徴とする圧着型半導体パッケージ。[Claims] 1. In a crimp-type semiconductor package in which a semiconductor substrate and a dielectric substrate are electrically coupled by a plurality of groups of micro crimp terminals, in addition to the group of micro crimp terminals, the semiconductor substrate and the dielectric substrate are A crimp-type semiconductor package characterized by having three or more micro solder groups arranged between a substrate. 2. The crimp-type semiconductor package according to claim 1, wherein the region in which the solder particles are arranged is within a circle having a diameter of 5 mm centered on the center of the semiconductor substrate. 3. The crimp-type semiconductor package according to claim 1, wherein the regions where the solder micro-groups are arranged are the four corners of the periphery of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59218411A JPS6197932A (en) | 1984-10-19 | 1984-10-19 | Compression bonded semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59218411A JPS6197932A (en) | 1984-10-19 | 1984-10-19 | Compression bonded semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6197932A true JPS6197932A (en) | 1986-05-16 |
| JPH0572751B2 JPH0572751B2 (en) | 1993-10-12 |
Family
ID=16719489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59218411A Granted JPS6197932A (en) | 1984-10-19 | 1984-10-19 | Compression bonded semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6197932A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
| WO2014136241A1 (en) * | 2013-03-07 | 2014-09-12 | 東北マイクロテック株式会社 | Laminate and method of producing same |
| JP2017028156A (en) * | 2015-07-24 | 2017-02-02 | 新光電気工業株式会社 | Mounting structure and manufacturing method therefor |
| JP2018195664A (en) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | Semiconductor device and method of manufacturing the same |
-
1984
- 1984-10-19 JP JP59218411A patent/JPS6197932A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
| WO2014136241A1 (en) * | 2013-03-07 | 2014-09-12 | 東北マイクロテック株式会社 | Laminate and method of producing same |
| JP2017028156A (en) * | 2015-07-24 | 2017-02-02 | 新光電気工業株式会社 | Mounting structure and manufacturing method therefor |
| JP2018195664A (en) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0572751B2 (en) | 1993-10-12 |
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