JP2892055B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2892055B2 JP2892055B2 JP1294371A JP29437189A JP2892055B2 JP 2892055 B2 JP2892055 B2 JP 2892055B2 JP 1294371 A JP1294371 A JP 1294371A JP 29437189 A JP29437189 A JP 29437189A JP 2892055 B2 JP2892055 B2 JP 2892055B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- semiconductor device
- element body
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は樹脂封止型半導体素子に係り、特に回路基板
に搭載・実装して使用される樹脂封止された小型の半導
体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a resin-encapsulated semiconductor device, and particularly to a small-sized resin-encapsulated semiconductor device used by being mounted and mounted on a circuit board. The present invention relates to a semiconductor device.
（従来の技術） 近年、電子機器においては小形化ないし高機能化が要
求されており、この要求に対応して半導体素子も高集積
化されている。また、この高集積化された半導体素子を
所要の回路基板上に、高密度に搭載・実装して使用する
要求ないし形態が増加している。(Prior Art) In recent years, electronic devices have been required to be smaller and have higher functionality, and semiconductor devices have been highly integrated in response to this demand. In addition, there is an increasing demand or form for using the highly integrated semiconductor element mounted and mounted on a required circuit board at a high density.
ところで、半導体素子を回路基板上に搭載・実装する
手段としては、挿入型のDIPや表面実装型のSOJなどのよ
うに、パッケージ化された半導体素子をたとえばリフロ
ー法により、回路基板上に半田付けする手段が知られて
いる。By the way, as a means for mounting and mounting a semiconductor element on a circuit board, a packaged semiconductor element such as an insertion type DIP or a surface mount type SOJ is soldered on the circuit board by, for example, a reflow method. Means for doing so are known.
しかしながら、上記パッケージを用いる手段は、イン
ナーリードを含むパッケージサイズが半導体素子本体の
３〜４倍程度となり、高密度化に限界があった。この対
策として、パッケージ化せずに、ベアチップを回路基板
上に直接ダイマウントし、ボンディングワイヤでベアチ
ップのボンディングパッドと回路基板上のパッドとを接
続するCOB（チップオンボード）技術が高密度実装に採
用されるようになってきた。However, in the means using the package, the package size including the inner leads is about three to four times the size of the semiconductor element body, and there is a limit to the high density. As a countermeasure, COB (chip-on-board) technology, in which a bare chip is die-mounted directly on a circuit board without using a package, and the bonding pads on the bare chip are connected to the pads on the circuit board with bonding wires, is used for high-density mounting. It has been adopted.
しかして、上記COB技術では、高温高湿度に対する信
頼性保持のため、半導体素子本体の裏面をポッティング
樹脂で被覆封止する方法が用いられていることが多い。In the COB technique, a method of covering and sealing the back surface of the semiconductor element body with a potting resin is often used in order to maintain reliability against high temperature and high humidity.
しかし、樹脂のポッティングにより被覆封止する手段
を用いた構造は、チップないし素子本体とこれを搭載す
る回路基板、さらに被覆するポッティング樹脂と各々の
熱膨張係数が最大１桁と相異する場合が多いため、温度
サイクルが機器に加わった場合は素子本体を中心として
クラックが生じたり、ワイヤーがはずれたりして信頼性
上問題があるばかりでなく、ボンディングワイヤーを含
めた接続に必要とされる面積も素子本体の２〜３倍必要
となり、高密度実装の上で問題がある。However, in the structure using the means for covering and sealing by resin potting, the chip or element body, the circuit board on which the chip or element body is mounted, and the potting resin to be further covered may differ from the thermal expansion coefficient of each by up to one digit. When temperature cycling is applied to the device, cracks occur around the element body, and the wires come off, which causes problems in reliability.In addition, the area required for connection including bonding wires Is also required to be two to three times as large as the element body, and there is a problem in high-density mounting.
これらの問題に対してバンプ電極を介して基板上にフ
ェイスダウンで接続するフリップチップ実装が近年注目
を浴びている。この手段は予め回路パターンが形成され
た回路基板上に、バンプ電極を介して半導体素子本体を
フェイスダウンで実装することから、その実装密度もチ
ップ面積と同等にでき高密度化が可能となる。In recent years, attention has been paid to flip-chip mounting for connecting these components face-down on a substrate via bump electrodes. In this means, the semiconductor element body is mounted face-down via bump electrodes on a circuit board on which a circuit pattern has been formed in advance, so that the mounting density can be made equal to the chip area and the density can be increased.
（発明が解決しようとする課題） しかしながら、上記バンプ電極を介して半導体素子本
体をフェイスダウンで実装する手段は、ベアチップを実
装するため、樹脂をポッティングし被覆封止しない場合
バンプ電極を介した隙間から水分の浸入が起こり耐湿上
問題が起きる。一方、樹脂をポッティングまたは回路基
板をベアチップ間に挿入した場合は、先に述べたような
熱膨張係数の相異が熱的ストレスの影響を受け易く高信
頼性を保持できないという不都合がある。さらに、実装
段階においてベアチップを取り扱うことから温度、湿
度、保存雰囲気など保存環境の維持にコストがかかるば
かりでなく、チッピングなどの不良が発生する割合も高
いという問題がある。(Problems to be Solved by the Invention) However, the means for mounting the semiconductor element body face-down via the bump electrode is a method for mounting a bare chip, so that when a resin is not potted and covered and sealed, the gap via the bump electrode is not provided. Infiltration of moisture from the surface causes a problem of moisture resistance. On the other hand, when the resin is potted or the circuit board is inserted between the bare chips, there is a disadvantage that the above-described difference in the coefficient of thermal expansion is easily affected by the thermal stress and high reliability cannot be maintained. Further, since the bare chip is handled in the mounting stage, not only is it costly to maintain the storage environment such as temperature, humidity, and storage atmosphere, but also there is a problem that the rate of occurrence of defects such as chipping is high.
本発明は上記問題に鑑みてなされたもので、高密度実
装が可能でかつ、取扱いの容易な信頼性ある樹脂封止型
半導体素子を提供するものである。The present invention has been made in view of the above problems, and provides a reliable resin-encapsulated semiconductor element that can be mounted at high density and is easy to handle.
［発明の構成］ （課題を解決するための手段） 本発明は、一主面にバンプ電極の形成された半導体素
子の全面を前記バンプ電極を露出させて樹脂封止してな
る樹脂封止型半導体素子であって、前記半導体素子のバ
ンプ電極の形成された主面を封止する樹脂を他の部分を
封止する樹脂と異ならせて成ることを特徴とする。[Constitution of the Invention] (Means for Solving the Problems) The present invention relates to a resin-sealed mold in which the entire surface of a semiconductor element having a bump electrode formed on one main surface is exposed and resin-sealed. A semiconductor element, wherein a resin for sealing a main surface of the semiconductor element on which bump electrodes are formed is different from a resin for sealing other portions.
（作 用） 本発明によれば、外部端子としてのバンプ電極を有す
る樹脂封止層（パッケージ）を具備するため、パッケー
ジ自体の小型化が可能となる。また、フリップチップ実
装時にベアチップを用いた場合よりも耐湿性が向上し、
信頼性の向上を図り得るばかりでなく、半導体素子本体
が樹脂で被覆封止されているので取扱いも容易となる。
加えて、樹脂封止型半導体素子はダイパッドを有さない
構造であるため、水分の浸入に起因するリフロー時のク
ラックが生じないという作用効果も同時に呈する。(Operation) According to the present invention, since a resin sealing layer (package) having a bump electrode as an external terminal is provided, the size of the package itself can be reduced. In addition, the moisture resistance is improved as compared with the case where a bare chip is used at the time of flip chip mounting,
Not only can the reliability be improved, but also the handling becomes easy because the semiconductor element body is covered and sealed with resin.
In addition, since the resin-encapsulated semiconductor element has a structure that does not have a die pad, the effect of preventing cracks during reflow due to intrusion of moisture does not occur.
（実施例） 以下第１図を参照して本発明の実施例を説明する。第
１図は本発明に係る樹脂封止型半導体素子の構造例を示
す断面図で、１は樹脂封止型半導体素子、２は前記樹脂
封止型半導体素子の主要部を成す半導体素子本体、3a、
3bは前記半導体素子本体２を被覆封止する樹脂層（パー
ッケージ本体）で、3aはたとえば着色剤としてのカーボ
ンなど適当なフィラーをを混入したエポキシ樹脂また3b
はたとえばα線遮へいに用いる不純物濃度をppmレベル
に抑えたポリイミド樹脂でそれぞ形成されている。さら
に、４は前記半導体素子本体２の一主面に形設されたAl
ボンディングパッド、５は前記Alボンディングパット４
と電気的に接続しているバンプ電極たとえばPb/Sn:95/5
のハンダ層である。Embodiment An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view showing a structural example of a resin-encapsulated semiconductor device according to the present invention. 3a,
Reference numeral 3b denotes a resin layer (package main body) for covering and sealing the semiconductor element main body 2, and 3a denotes an epoxy resin mixed with an appropriate filler such as carbon as a coloring agent, or 3b.
Are formed of, for example, a polyimide resin in which the impurity concentration used for α-ray shielding is suppressed to the ppm level. Further, reference numeral 4 denotes an Al formed on one main surface of the semiconductor element body 2.
The bonding pad 5 is the Al bonding pad 4
Bump electrode electrically connected to, for example, Pb / Sn: 95/5
Of the solder layer.
次に上記構造の樹脂封止型半導体素子の製造例を説明
する。先ず、前記半導体素子本体２を被覆封止する前
に、前記ハンダバンプ電極５を形成する。すなわち、ポ
リイミド樹脂などからなる樹脂層3bを、Alボンディング
パッド４部を除いて形成したウェハー上にTi/Ni/Cu薄膜
を蒸着により1000Å/3000Å/5000Å形成した上に、所要
のバンプを形成する部分にエッチングレジストを被覆
し、Cu,Ni,Tiを順次エッチングする。このエッチング
は、Cuを過硫酸アンモニウム水溶液により、Niはメタノ
ール、塩酸、硫酸銅の混合液により、Tiはアンモニア、
過酸化水素水、エチレンジアミン四酢酸からなる混合液
によるウェットエッチングで行ない得る。かくして、Al
ボンディングパッド４に接続するTi/Ni/Cu接続パッドを
形成し、Sn/Pbのハンダ槽内にディップすることでハン
ダ電極バンプを形成する。バンプを形成後ウェハーをダ
イシングして半導体ペレット（半導体素子本体）とす
る。Next, an example of manufacturing a resin-sealed semiconductor device having the above structure will be described. First, before the semiconductor element body 2 is covered and sealed, the solder bump electrodes 5 are formed. That is, a Ti / Ni / Cu thin film is formed on a wafer having a resin layer 3b made of a polyimide resin or the like excluding 4 parts of the Al bonding pads by 1000 蒸 着 / 3000Å / 5000Å by vapor deposition, and then required bumps are formed. A portion is coated with an etching resist, and Cu, Ni, and Ti are sequentially etched. In this etching, Cu is mixed with an aqueous solution of ammonium persulfate, Ni is mixed with a mixed solution of methanol, hydrochloric acid and copper sulfate, Ti is mixed with ammonia,
It can be performed by wet etching with a mixed solution of hydrogen peroxide and ethylenediaminetetraacetic acid. Thus, Al
A Ti / Ni / Cu connection pad connected to the bonding pad 4 is formed, and a solder electrode bump is formed by dipping in a Sn / Pb solder bath. After the bumps are formed, the wafer is diced into semiconductor pellets (semiconductor element bodies).
上記バンプ電極５が形成された半導体素子本体２を、
たとえば第２図にて断面的に示す構造の金型６内に配置
し、トランスファーモールドする。このモールド時の温
度は、前記半導体素子本体２に形成されたバンプ電極４
であるハンダの融点以下で行い、被覆封止樹脂総3aは半
導体素子本体２の厚さ以内で形成されるように金型６の
設計を行い、半導体素子本体２を配置する。The semiconductor element main body 2 on which the bump electrodes 5 are formed,
For example, it is placed in a mold 6 having a structure shown in cross section in FIG. 2 and transfer-molded. The temperature at the time of molding is determined by the bump electrode 4 formed on the semiconductor element body 2.
The mold 6 is designed so that the coating and sealing resin 3a is formed within the thickness of the semiconductor element body 2 and the semiconductor element body 2 is arranged.
上記により半導体素子本体２を樹脂封止して構成した
樹脂封止型半導体素子１は、被覆封止樹脂層3b表面に対
してバンプ電極４が30μｍ±10μｍ突出した形で形成さ
れており、また被覆封止樹脂層3bは５μｍの厚さで、被
覆封止樹脂層3aは半導体素子本体２の周囲を250μｍの
厚さで夫々被覆封止した構成を成していた。The resin-encapsulated semiconductor element 1 in which the semiconductor element body 2 is resin-encapsulated as described above is formed such that the bump electrode 4 projects 30 μm ± 10 μm from the surface of the encapsulation resin layer 3b. The coating and sealing resin layer 3b has a thickness of 5 μm, and the coating and sealing resin layer 3a has a configuration in which the periphery of the semiconductor element body 2 is coated and sealed with a thickness of 250 μm.
上記構成した樹脂封止型半導体素子１を85℃、85％の
高温高湿中に1000H放置したところ、特性は故障判定基
準に対してマージンをもって動作しており、腐食などの
不良は発生しなかった。When the resin-encapsulated semiconductor element 1 having the above structure was left in a high-temperature and high-humidity environment of 85 ° C. and 85% for 1000 hours, the characteristics were operating with a margin with respect to the failure criterion, and no defects such as corrosion occurred. Was.
さらにこの樹脂封止型半導体素子１をセラミック基板
上にフリップチップ接続したところJIS C7022に定める
温度サイクル試験−55℃（30分）〜25℃（５分）〜150
℃（30分）〜25℃（５分）300cycleに対して断線などの
不良発生もなく高信頼性を有していることを確認した。
また取扱い上の原因で発生する不良もベアチップを取り
扱う場合と比較して10％減少させることができた。Further, when this resin-encapsulated semiconductor element 1 was flip-chip connected on a ceramic substrate, a temperature cycle test defined by JIS C7022 -55 ° C. (30 minutes) to 25 ° C. (5 minutes) to 150 ° C.
It was confirmed that there was no failure such as disconnection and high reliability for 300 cycles of 30 ° C. (30 minutes) to 25 ° C. (5 minutes).
Defects caused by handling were also reduced by 10% compared to handling bare chips.
本発明は上記実施例に限定されるものではなくその要
旨を逸脱しない範囲で種々変更可能である。たとえば接
続パンブの形成にTi/Ni/Cuの代わりに、Ti/NiもしくはT
i/Ni/Pd/Auを用いてもよいし、ハンダバンプ電極はPb/S
n＝95/5に限られるものではなく、その形成方法は半導
体素子本体２を樹脂3a,3bによって被覆した後に形成し
てもよい。さらにバンプ電極５はAlボンディングパッド
４上に対応して形成されるものに限らず、薄膜配線を引
きまわし、被覆封止樹脂層3aの全面にわたって形成され
るものであってもよい。The present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist thereof. For example, instead of Ti / Ni / Cu, Ti / Ni or T
i / Ni / Pd / Au may be used, and Pb / S
The method is not limited to n = 95/5, and may be formed after the semiconductor element body 2 is covered with the resins 3a and 3b. Further, the bump electrode 5 is not limited to the one formed on the Al bonding pad 4 but may be formed over the entire surface of the covering sealing resin layer 3a by running a thin film wiring.
［発明の効果］ 本発明によれば、半導体素子本体のバンプ電極の形成
された主面を、例えばポリイミド樹脂のような低粘度の
樹脂により薄く封止することが可能であり、この被覆封
止樹脂層からバンプ電極を露出させ、これを外部接続端
子としているために小型化が可能となる。さらに、樹脂
層で半導体素子本体を被覆封止してあるため、フリップ
チップ実装時にベアチップを用いた場合よりも耐湿性が
大幅に向上するばかりでなく、樹脂を基板上の半導体ペ
レットに対してポッティングする場合と比較して熱的ス
トレスに対する耐性も向上する。また樹脂層で半導体素
子本体を被覆封止してあるため、取扱いが容易となると
同時にダイパッドを有さない構造であるため水分の浸入
に起因するリフロー時のクラックが生じないという効果
も生じる。[Effects of the Invention] According to the present invention, it is possible to thinly seal the main surface of the semiconductor element body on which the bump electrodes are formed with a low-viscosity resin such as a polyimide resin. Since the bump electrodes are exposed from the resin layer and are used as external connection terminals, miniaturization is possible. Furthermore, since the semiconductor element body is covered and sealed with a resin layer, not only the moisture resistance is significantly improved than when a bare chip is used during flip chip mounting, but also the resin is potted to the semiconductor pellet on the substrate. The resistance to thermal stress is also improved as compared to the case where In addition, since the semiconductor element body is covered and sealed with the resin layer, it is easy to handle, and at the same time, since it has a structure without a die pad, cracks during reflow due to intrusion of moisture do not occur.
第１図は本発明に係る樹脂封止型半導体素子の一構成例
を示す断面図、第２図は本発明に係る樹脂封止型半導体
素子の製造例を模式的に示す断面図である。 １……樹脂封止型半導体素子 ２……半導体素子本体 3a、3b……被覆封止する樹脂層 ４……Alボンディングパッド ５……バンプ電極 ６……モールド金型FIG. 1 is a cross-sectional view showing one configuration example of a resin-sealed semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view schematically showing a production example of the resin-sealed semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Resin sealing type semiconductor element 2 ... Semiconductor element main body 3a, 3b ... Resin layer to cover and seal 4 ... Al bonding pad 5 ... Bump electrode 6 ... Mold die
───────────────────────────────────────────────────── フロントページの続き (72)発明者 須藤 俊夫 神奈川県川崎市幸区小向東芝町１番地 株式会社東芝総合研究所内 (56)参考文献 特開 平３−104141（ＪＰ，Ａ) 実開 昭63−1341（ＪＰ，Ｕ) 実開 平２−131348（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 H01L 23/30 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toshio Sudo 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (56) References JP-A-3-104141 (JP, A) 63-1341 (JP, U) JP-A 2-131348 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 H01L 23/30
Claims (1)
子の全面を前記バンプ電極を露出させて樹脂封止してな
る樹脂封止型半導体素子であって、 前記半導体素子のバンプ電極の形成された主面を封止す
る樹脂を他の部分を封止する樹脂と異ならせて成ること
を特徴とする樹脂封止型半導体素子。1. A resin-encapsulated semiconductor device, wherein the entire surface of a semiconductor element having a bump electrode formed on one principal surface is exposed to the bump electrode and sealed with a resin. A resin-encapsulated semiconductor device, wherein a resin for encapsulating the formed main surface is different from a resin for encapsulating other portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294371A JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294371A JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03154344A JPH03154344A (en) | 1991-07-02 |
| JP2892055B2 true JP2892055B2 (en) | 1999-05-17 |
Family
ID=17806850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1294371A Expired - Fee Related JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2892055B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582582A (en) * | 1991-09-24 | 1993-04-02 | Nec Yamagata Ltd | Semiconductor device |
| JP3258764B2 (en) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same |
| US5766972A (en) * | 1994-06-02 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Method of making resin encapsulated semiconductor device with bump electrodes |
-
1989
- 1989-11-13 JP JP1294371A patent/JP2892055B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03154344A (en) | 1991-07-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |