JPH03105934A - Semiconductor integrated circuit device and manufacture thereof - Google Patents
Semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPH03105934A JPH03105934A JP24196989A JP24196989A JPH03105934A JP H03105934 A JPH03105934 A JP H03105934A JP 24196989 A JP24196989 A JP 24196989A JP 24196989 A JP24196989 A JP 24196989A JP H03105934 A JPH03105934 A JP H03105934A
- Authority
- JP
- Japan
- Prior art keywords
- film wiring
- thick film
- thick
- bonding
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000001737 promoting effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野３
本発明は、半導体集積回路装置およびその製造方法に関
し、特にパッケージ基板上に形戊される厚膜配線の微細
化に適用して有効な技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field 3] The present invention relates to a semiconductor integrated circuit device and its manufacturing method, and particularly relates to a technique that is effective when applied to miniaturization of thick film wiring formed on a package substrate. It is related to.
１
〔従来技術〕
セラミック・ビングリッドアレイ（ｐｉｎ ｇｒｉｄ
ａｒｒａｙ）は、セラミック材料からなるパッケージ基
板上に厚膜配線を形或し、この厚膜配線の先端（ボンデ
ィングエリア）と半導体チップとの間にワイヤをボンデ
ィングした構或になっている。上記厚膜配線は、スクリ
ーン印刷法などを用いてメタライズされたＷ（タングス
テン）やＭ○ （モリブデン）からなり、その表面には
、例えばＮ ｒ 、Ａ． ｕの順でメッキが施される。1 [Prior art] Ceramic pin grid array
The array has a structure in which a thick film wiring is formed on a package substrate made of a ceramic material, and a wire is bonded between the tip (bonding area) of this thick film wiring and a semiconductor chip. The above-mentioned thick film wiring is made of W (tungsten) or M○ (molybdenum) that is metalized using a screen printing method or the like, and its surface is coated with, for example, N r , A. Plating is applied in the order of u.
なお、この種のセラミック・ビングリッドアレイについ
ては、例えば特公昭６１５ ８ ５ ３ ３号公報に記
載されている。This type of ceramic bin grid array is described, for example, in Japanese Patent Publication No. 615-85-33.
ピングリッドアレイの多ピン化に伴い、前記厚膜配線の
線幅やピッチも次第に狭くなっているが、厚膜配線の微
細化には限界がある。これは、厚膜配線の′ａ福を狭く
すると、印刷時のグレやメッキの付きまわり等に起因し
て配線のエッジ部が丸くなり、有効なボンディングエリ
アの確保が困難となるため、ワイヤの倒れやよじれ等の
ボンディング不良が多発するようになるからである。そ
の対策として、Ａｌ蒸着法を用いて微細な薄膜配線を形
戊する方法が一部で採用されているが、，！蒸着による
薄膜配線は、前記厚膜配線に比べてコストが高いという
欠点がある。また、半導体チップをパッケージ基板上に
搭載するには、ノクツケージ基板上に配線と同一材料の
チップ取付部を形或し、その上に半導体チップを接合す
るが、Ａｌ蒸着法を用いて形或したチップ取付部の膜厚
が厚くなると、半導体チップにクラツクが発生し易くな
るという問題がある。As the number of pins in a pin grid array increases, the line width and pitch of the thick film wiring are gradually becoming narrower, but there is a limit to the miniaturization of the thick film wiring. This is because if the thickness of the thick-film wiring is narrowed, the edges of the wiring will become rounded due to blurring during printing and the surrounding area of the plating, making it difficult to secure an effective bonding area. This is because bonding defects such as falling and twisting occur frequently. As a countermeasure to this problem, a method of forming fine thin film wiring using the Al vapor deposition method has been adopted in some cases, but...! Thin film wiring formed by vapor deposition has the disadvantage that it is more expensive than the thick film wiring. In addition, in order to mount a semiconductor chip on a package substrate, a chip mounting part made of the same material as the wiring is formed on the cage board, and the semiconductor chip is bonded onto it, which is formed using the Al vapor deposition method. When the thickness of the chip mounting portion increases, there is a problem in that cracks are more likely to occur in the semiconductor chip.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は厚膜配線の微細化を促進することのでき
る技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can promote the miniaturization of thick film wiring.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
る。 Ru.
すなわち、本願の一発明は、パッケージ基板上にメタラ
イズされた厚膜配線のボンディングエリアを圧潰して平
坦化した半導体集積回路装置である。That is, one invention of the present application is a semiconductor integrated circuit device in which a bonding area of thick film wiring metallized on a package substrate is crushed and flattened.
上記した手段によれば、ボンディングエリアを平坦化す
ることにより、ボンディング時におけるワイヤの倒れや
よじれ等の発生を回避することができるので、厚膜配線
の微細化を促進することができる。According to the above-mentioned means, by flattening the bonding area, it is possible to avoid the occurrence of wire collapse, twisting, etc. during bonding, and therefore it is possible to promote the miniaturization of thick film wiring.
第２図は、本発明の一実施例であるセラミック・ビング
リッドアレイ１を示している。ＳｉＣなどのセラミック
材料からなるパッケージ基板２上には、スクリーン印刷
法などを用いてメタライズされた厚膜配線３がパターン
形成されている。厚膜配線３は、ＷやＭｏからなり、そ
の表面には、例えばＮｉ、Ａｕの順にメッキが施されて
いる。FIG. 2 shows a ceramic bin grid array 1 which is an embodiment of the present invention. On a package substrate 2 made of a ceramic material such as SiC, metalized thick film wiring 3 is patterned using a screen printing method or the like. The thick film wiring 3 is made of W or Mo, and its surface is plated with, for example, Ni and Au in that order.
パッケージ基板２の中央部には、上記厚膜配線３と同一
材料で構或されたチップ取付部４が設けられており、こ
のチップ取付部４上には、耐熱性エポキシ樹脂などの接
合材５を介して半導体チップ６が搭載されている。半導
体チップ６と前記厚膜配線３とは、ＡｕあるいはＡｌな
どのワイヤ７を介して電気的に接続されている。A chip mounting portion 4 made of the same material as the thick film wiring 3 is provided in the center of the package substrate 2, and a bonding material 5 such as a heat-resistant epoxy resin is placed on the chip mounting portion 4. A semiconductor chip 6 is mounted thereon. The semiconductor chip 6 and the thick film wiring 3 are electrically connected via wires 7 made of Au, Al, or the like.
パッケージ基板２の上面には、ＡｌＮなどのセラミック
財料からなるキャップ８が設けられ、このキャップ８と
パッケージ基板２とで前記半導体チップ６を気密封止し
ている。このキャップ８は、ガラスなどの封止材９を介
してパッケージ基板２の上面に接合されている。A cap 8 made of a ceramic material such as AlN is provided on the upper surface of the package substrate 2, and the semiconductor chip 6 is hermetically sealed between the cap 8 and the package substrate 2. This cap 8 is bonded to the upper surface of the package substrate 2 via a sealing material 9 such as glass.
パッケージ基板２の下面には、セラミック・ピングリッ
ドアレイｌの外部端子を構或するリードピン１０が設け
られている。リードピンＩＯは、４２アロイ、コバール
などで構或され、Ａｇなどのろう材ｌ１によってパッケ
ージ基板２の下面に接合されている。また、リードビン
ｌＯは、パッケージ基板２を貫通するスルーホールｌ２
を通じて前記厚膜配線３と電気的に接続されている。Lead pins 10, which constitute external terminals of the ceramic pin grid array l, are provided on the lower surface of the package substrate 2. The lead pin IO is made of 42 alloy, Kovar, etc., and is bonded to the lower surface of the package substrate 2 by a brazing material l1 such as Ag. Further, the lead bin lO has a through hole l2 penetrating the package substrate 2.
It is electrically connected to the thick film wiring 3 through.
ところで厚膜配線３は、本来その表面が平坦となるよう
に設計されるが、実際のパッケージ基板２上にメタライ
ズされた厚膜配線３は、第１図に示すように、印刷時の
グレやメッキの付きまわり等に起因してそのエッジ部が
丸くなるので、その断面がカマボコ状になってしまう。Incidentally, the thick film wiring 3 is originally designed to have a flat surface, but the thick film wiring 3 metalized on the actual package substrate 2 is susceptible to blur and other problems during printing, as shown in Fig. 1. Because the edges are rounded due to the plating, etc., the cross section becomes hollow.
この傾向は、厚膜配線３の線幅が微細化される程顕著に
なるため、微細な厚膜配線３においては、有効なボンデ
ィングエリアの確保が困難となる結果、ワイヤ７の倒れ
やよじれ等のボンディング不良が多発し易い。そこで本
実施例では、第１図に示すように、厚膜配線３をパッケ
ージ基板２上にメクライズした後、そのボンディングエ
リア３ａをプレス、または超音波を併用したプレス等で
圧潰して平坦化する。これにより、厚膜配線３が微細化
された場合においても、ボンディング時におけるワイヤ
７の倒れやよじれ等の発生を回避することができるので
、厚膜配線３を微細化し、セラミック・ビングリッドア
レイ１の多ピン化を促進することができる。This tendency becomes more pronounced as the line width of the thick film wiring 3 becomes finer. Therefore, in the fine thick film wiring 3, it becomes difficult to secure an effective bonding area, and as a result, the wire 7 may fall or twist. Bonding defects tend to occur frequently. Therefore, in this embodiment, as shown in FIG. 1, after the thick film wiring 3 is meklyized on the package substrate 2, the bonding area 3a is crushed and flattened using a press or a press using ultrasonic waves. . As a result, even when the thick film wiring 3 is miniaturized, it is possible to avoid the occurrence of falling or twisting of the wire 7 during bonding. The number of pins can be increased.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野であるセラミック・ピン
グリッドアレイに適用した場合について説明したが、本
発明はこれに限定されるものではなく、パッケージ基板
上に厚膜配線をメタライズした各種の半導体集積回路装
置に適用することができる。In the above description, the invention made by the present inventor was mainly applied to a ceramic pin grid array, which is the field of application that formed the background of the invention, but the present invention is not limited to this, and the present invention is not limited to this. It can be applied to various semiconductor integrated circuit devices in which thick film wiring is metallized on a substrate.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.
パッケージ基板上にメタライズされた厚膜配線のボンデ
ィングエリアを圧潰して平坦化することにより、ボンデ
ィング時におけるワイヤの倒れやよじれ等の不良発生を
回避することができるので、厚膜配線の微細化を促進す
ることができる。By crushing and flattening the bonding area of thick film wiring metallized on the package substrate, it is possible to avoid defects such as falling or kinking of the wire during bonding, making it possible to miniaturize thick film wiring. can be promoted.
第１図は、本発明の一実施例である半導体集積回路装置
の厚膜配線を示す要部拡大斜視図、第２図は、この半導
体集積回路装置の断面図である。
１・・・セラミック・ビングリッドアレイ、２・パッケ
ージ基板、３・・・厚膜配線、３ａ・ボンディングエリ
ア、４・・・チップ取付５・・・接合材、６・・・半導
体チップ、７・ワイヤ、８・・・キャップ、９・・・封
止ｌＯ・・・リードビン、ｌ１・・・ろう材、●●−ス
ルーホール。FIG. 1 is an enlarged perspective view of essential parts showing thick film wiring of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view of this semiconductor integrated circuit device. DESCRIPTION OF SYMBOLS 1... Ceramic bin grid array, 2... Package substrate, 3... Thick film wiring, 3a, Bonding area, 4... Chip attachment 5... Bonding material, 6... Semiconductor chip, 7. Wire, 8... Cap, 9... Sealing lO... Lead bottle, l1... Brazing metal, ●●-Through hole.
Claims (1)
イヤを介して接続してなる半導体集積回路装置であって
、前記厚膜配線のボンディングエリアを圧潰して平坦化
したことを特徴とする半導体集積回路装置。 ２、前記厚膜配線のボンディングエリアを平坦化するに
際し、プレスまたは超音波を併用したプレスにより前記
ボンディングエリアを圧潰することを特徴とする請求項
１記載の半導体集積回路装置の製造方法。[Claims] 1. A semiconductor integrated circuit device in which thick film wiring on a package substrate and a semiconductor chip are connected via wires, wherein the bonding area of the thick film wiring is flattened by crushing it. A semiconductor integrated circuit device characterized by: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein when flattening the bonding area of the thick film wiring, the bonding area is crushed by a press or a press using ultrasonic waves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24196989A JPH03105934A (en) | 1989-09-20 | 1989-09-20 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24196989A JPH03105934A (en) | 1989-09-20 | 1989-09-20 | Semiconductor integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03105934A true JPH03105934A (en) | 1991-05-02 |
Family
ID=17082277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24196989A Pending JPH03105934A (en) | 1989-09-20 | 1989-09-20 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03105934A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335602A (en) * | 1995-06-08 | 1996-12-17 | Ngk Spark Plug Co Ltd | Ceramic substrate and its manufacturing method |
| US5856212A (en) * | 1994-05-11 | 1999-01-05 | Goldstar Electron Co., Ltd. | Method of producing semiconductor package having solder balls |
| JP2007251065A (en) * | 2006-03-17 | 2007-09-27 | Mitsubishi Electric Corp | Ceramic wiring board, and its manufacturing method |
| JP2008092356A (en) * | 2006-10-03 | 2008-04-17 | Hosiden Corp | Headset |
| JP2010103419A (en) * | 2008-10-27 | 2010-05-06 | Toshiba Lighting & Technology Corp | Printed circuit board, and electronic device with the same |
-
1989
- 1989-09-20 JP JP24196989A patent/JPH03105934A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5856212A (en) * | 1994-05-11 | 1999-01-05 | Goldstar Electron Co., Ltd. | Method of producing semiconductor package having solder balls |
| JPH08335602A (en) * | 1995-06-08 | 1996-12-17 | Ngk Spark Plug Co Ltd | Ceramic substrate and its manufacturing method |
| JP2007251065A (en) * | 2006-03-17 | 2007-09-27 | Mitsubishi Electric Corp | Ceramic wiring board, and its manufacturing method |
| JP2008092356A (en) * | 2006-10-03 | 2008-04-17 | Hosiden Corp | Headset |
| JP2010103419A (en) * | 2008-10-27 | 2010-05-06 | Toshiba Lighting & Technology Corp | Printed circuit board, and electronic device with the same |
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