JPH0292936U - - Google Patents
Info
- Publication number
- JPH0292936U JPH0292936U JP1989000960U JP96089U JPH0292936U JP H0292936 U JPH0292936 U JP H0292936U JP 1989000960 U JP1989000960 U JP 1989000960U JP 96089 U JP96089 U JP 96089U JP H0292936 U JPH0292936 U JP H0292936U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- printed circuit
- chip carrier
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Description
第1図は、本考案に於けるチツプキヤリアIC
の実施例を示す平面図。第2図は、第1図の側面
図である。第3図は、本考案に於けるチツプキヤ
リアICの他の実施例を示す平面図。第4図は、
第3図の側面図である。第5図は、従来のチツプ
キヤリアICの平面図。 1……プリント基板、2……外部接続用凸起端
子、3……外部接続用端子。
の実施例を示す平面図。第2図は、第1図の側面
図である。第3図は、本考案に於けるチツプキヤ
リアICの他の実施例を示す平面図。第4図は、
第3図の側面図である。第5図は、従来のチツプ
キヤリアICの平面図。 1……プリント基板、2……外部接続用凸起端
子、3……外部接続用端子。
Claims (1)
- プリント基板にICチツプを固定し、該プリン
ト基板の配線パターンと該ICチツプを接続し、
樹脂で封止を行なつたチツプキヤリアICに於い
て、該チツプキヤリアICの外部接続端子が、凸
起状に形成されていることを特徴とするチツプキ
ヤリアIC。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989000960U JPH0292936U (ja) | 1989-01-09 | 1989-01-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989000960U JPH0292936U (ja) | 1989-01-09 | 1989-01-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0292936U true JPH0292936U (ja) | 1990-07-24 |
Family
ID=31200434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989000960U Pending JPH0292936U (ja) | 1989-01-09 | 1989-01-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0292936U (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4941901A (ja) * | 1972-08-29 | 1974-04-19 | ||
JPS4942624A (ja) * | 1972-08-23 | 1974-04-22 | ||
JPH01235356A (ja) * | 1988-03-16 | 1989-09-20 | Nec Corp | モジュール基板 |
-
1989
- 1989-01-09 JP JP1989000960U patent/JPH0292936U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4942624A (ja) * | 1972-08-23 | 1974-04-22 | ||
JPS4941901A (ja) * | 1972-08-29 | 1974-04-19 | ||
JPH01235356A (ja) * | 1988-03-16 | 1989-09-20 | Nec Corp | モジュール基板 |