JPH027472A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH027472A JPH027472A JP12614788A JP12614788A JPH027472A JP H027472 A JPH027472 A JP H027472A JP 12614788 A JP12614788 A JP 12614788A JP 12614788 A JP12614788 A JP 12614788A JP H027472 A JPH027472 A JP H027472A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- cathode
- cathode electrode
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 230000000994 depressogenic effect Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000002923 metal particle Substances 0.000 abstract description 5
- 239000011856 silicon-based particle Substances 0.000 abstract description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 3
- 239000011733 molybdenum Substances 0.000 abstract description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 239000002245 particle Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は上部より電極板を接続する構成の半導体装置
に関するｂのである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a structure in which electrode plates are connected from above.
第２図は従来のゲートターンオフサイリスタ（ＧＴＯ）
を示す部分断面図である。同図において、１はｎベース
層であり、このｎベース層１の表面にｐベースＮ２．裏
面にｎエミツタ層３を形成している。Figure 2 shows a conventional gate turn-off thyristor (GTO)
FIG. In the figure, 1 is an n-base layer, and the surface of this n-base layer 1 has a p-base N2. An n emitter layer 3 is formed on the back surface.
ｎベース層２の凸部上面上にｎエミツタ層４が形成され
、このｎエミツタ層４上にカソード電極５が形成される
ことで同図に示すようにカソード電極５が島状に配置さ
れることになる。また、ｎベース層２の凹部底面上にゲ
ート電１ｆｉ ６が、ｎエミツタ層３の裏面にアノード
電極７が各々オーミック接触して形成されており、ゲー
ト電極６が絶縁膜８で覆われている。An n emitter layer 4 is formed on the upper surface of the convex portion of the n base layer 2, and a cathode electrode 5 is formed on this n emitter layer 4, so that the cathode electrode 5 is arranged in an island shape as shown in the figure. It turns out. Further, a gate electrode 1fi 6 is formed on the bottom surface of the concave portion of the n base layer 2, and an anode electrode 7 is formed in ohmic contact with the back surface of the n emitter layer 3, and the gate electrode 6 is covered with an insulating film 8. .
さらに島状のカソード電極５全てと硬質材料からなるカ
ソード電極板９を上部から電気的に接続している。Further, all of the island-shaped cathode electrodes 5 and a cathode electrode plate 9 made of a hard material are electrically connected from above.
このように構成されたＧＴＯはｎエミツタ層３からｎエ
ミツタ層４へ流れている陽極電流をオフ状態にする動作
は、カソード電１ｉ５に対して負の電圧をゲート電極６
に与え、ｎベース層２中のキャリアをゲート電極６から
引き抜くことで行われる。In the GTO configured in this way, the operation of turning off the anode current flowing from the n-emitter layer 3 to the n-emitter layer 4 is to apply a negative voltage to the cathode electrode 1i5 to the gate electrode 6.
This is done by giving a current to n-base layer 2 and extracting carriers from gate electrode 6.
上記した陽極電流とｎベース層２中のキャリアをゲート
電極６から引き抜くゲート電流の比をターンオフゲイン
（Ｇ ）と称し、このＧ。０は通常Ｏ
３〜５の値を示す。従って、カソード電極５とゲート電
極６の電位差が１５〜３０Ｖであるが、陽極電流が１０
００Ａ程度であれば、このＧＴＯをオフさせるためには
２００〜３４０Ａの大きなゲート電流を流すことになる
。The ratio of the above-mentioned anode current to the gate current that extracts carriers in the n-base layer 2 from the gate electrode 6 is called turn-off gain (G). 0 usually indicates a value of O 3-5. Therefore, although the potential difference between the cathode electrode 5 and the gate electrode 6 is 15 to 30V, the anode current is 10V.
If the current is approximately 00A, a large gate current of 200 to 340A will be required to turn off the GTO.
従来のＧＴＯは以上のように構成されており、絶縁膜８
によりカソード電極板９（カソード電極５）とゲート電
極６を絶縁していた。The conventional GTO is configured as described above, and the insulating film 8
The cathode electrode plate 9 (cathode electrode 5) and gate electrode 6 were insulated.
しかしながら、製造工程中にシリコンの欠けた粒子ある
いは製造用部品等の金属片等の異物がゲート電極６上あ
るいは絶縁Ｉｌ！８上に付着する。さらに、カソード電
極５．ゲート電極６を形成する時における真空中のアル
ミニウム等の金属の蒸着の際、電極材料の大きい粒子（
絶縁Ｉｌｌ ８の厚さ程度以上）がゲート電極６上に付
着する。However, during the manufacturing process, foreign substances such as chipped silicon particles or metal pieces from manufacturing parts may be deposited on the gate electrode 6 or insulating Il! 8. Further, a cathode electrode 5. During the vapor deposition of metal such as aluminum in vacuum when forming the gate electrode 6, large particles of the electrode material (
An insulating layer (approximately the thickness of the insulator Ill 8) is deposited on the gate electrode 6.
このような場合、金属粒子あるいはシリコン粒子が絶縁
膜８を突き扱け、これらの粒子によりカソード電極板９
とゲート電極６が短絡される問題点があった。従って、
顕微鏡等による検査でこのような粒子を検出し、除去す
る作業が必要となり、製造工程が複雑化する。また、上
記した検査によっても粒子を検出しえない場合もあり、
上記したカソード電極板９とゲート電極６の短絡問題を
回避しえていない。In such a case, metal particles or silicon particles can pierce the insulating film 8, and these particles can damage the cathode electrode plate 9.
There was a problem that the gate electrode 6 was short-circuited. Therefore,
It is necessary to detect and remove such particles by inspection using a microscope or the like, which complicates the manufacturing process. In addition, there may be cases where particles cannot be detected even with the above-mentioned tests.
The short circuit problem between the cathode electrode plate 9 and the gate electrode 6 described above cannot be avoided.
この発明は上記のような問題点を解決するためになされ
たもので、異なる電極間が短絡されることのない半導体
装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device in which different electrodes are not short-circuited.
この発明にかかる半導体装置は、複数の半導体層を積層
して形成された半導体チップであって、その最上層を形
成する最上部半導体層が前記半導体チップの上面の一部
分のみに突出形成されていることにより、前記半導体チ
ップの上面部が、前記突出形成による凸部と、前記凸部
の周辺部に相当する凹部とを有する半導体チップと、前
記四部の底面上に形成された第１の電極と、前記凸部の
上面上に形成された第２の電極と、前記第１と第２の電
極の上方に設けられ、前記第１と第２の電極の双方に対
向する広がりを持つとともに、前記第２の上面に固着さ
れることで前記第２の電極を介して前記最上部半導体層
に電気的に接続する電極板とを備えた半導体装置におい
て、前記電極板の下面のうち前記第１の電極に対向する
領域に、前記電極板の上面側に向って陥没する堀込みを
設けている。The semiconductor device according to the present invention is a semiconductor chip formed by stacking a plurality of semiconductor layers, and the top semiconductor layer forming the top layer is formed to protrude from only a part of the top surface of the semiconductor chip. By this, the top surface of the semiconductor chip has a convex portion formed by the protrusion, a concave portion corresponding to the peripheral portion of the convex portion, and a first electrode formed on the bottom surface of the four portions. , a second electrode formed on the upper surface of the convex portion, provided above the first and second electrodes, and having an extension facing both the first and second electrodes; an electrode plate fixed to a second upper surface to be electrically connected to the uppermost semiconductor layer via the second electrode; A trench that is depressed toward the upper surface of the electrode plate is provided in a region facing the electrode.
この発明における電極板は、その下面における第１の電
極領域に対向する領域に掘込みを設けているため、第１
の電極と電極板間に比較的大きな空間を形成することが
できる。The electrode plate according to the present invention has a recess on the lower surface thereof in a region opposite to the first electrode region.
A relatively large space can be formed between the electrode and the electrode plate.
第１図はこの発明の一実施例であるＧＴＯを示す部分断
面図である。以下、同図を参照しつつ、１！Ｊ造方法を
説明する。FIG. 1 is a partial sectional view showing a GTO which is an embodiment of the present invention. Below, while referring to the same figure, 1! The J construction method will be explained.
まず、シリコン基板であるｎベース層１の表裏面をガリ
ウム、ボロン等を用いて、ｐ型拡散を行い、ｎベース層
２及びｎエミツタ層３を形成する。First, p-type diffusion is performed on the front and back surfaces of an n-base layer 1, which is a silicon substrate, using gallium, boron, etc., to form an n-base layer 2 and an n-emitter layer 3.
このｎベース層２表面上にリンを全面あるいは選択拡散
して約２０μｍの厚さのｎエミツタ層４を形成する。次
に、選択的にｎエミツタ層４と、ｎベース層２の一部を
エツチングすることで同図に示すように島状のｎエミツ
タ層４を突出形成する。この島状のｎエミツタ層４は約
５００μｍ間隔で並列に配置され、その幅は約２００μ
ｍである。そして、このｎエミツタ層４の突出形成によ
り、上記各半導体層１〜４よりなる半導体チップは、そ
の上面に凹部１０と凸部１１とを有することとなる。On the surface of this n base layer 2, phosphorus is diffused over the entire surface or selectively to form an n emitter layer 4 having a thickness of about 20 μm. Next, by selectively etching a portion of the n emitter layer 4 and the n base layer 2, an island-shaped n emitter layer 4 is formed to protrude as shown in the figure. These island-shaped n emitter layers 4 are arranged in parallel at intervals of approximately 500 μm, and their width is approximately 200 μm.
It is m. Due to the protruding formation of the n-emitter layer 4, the semiconductor chip made up of the semiconductor layers 1 to 4 has a recess 10 and a projection 11 on its upper surface.
次に、ｎエミツタ層３の裏面にはアルミニウムを蒸着す
ることでアノード電極７を形成し、このアノード電極７
の裏面にモリブデン板等の図示しない金属補強板を貼り
付ける。また、金属材料をρベース層２上及びｎエミツ
タ層４１全面に約１０μｍの厚さで蒸着し、写真製版で
一部除去することで、第１図に示すようにカソード電極
５を凸部１１の上面に、また、ゲート電極６を四部１゜
の底面上に、それぞれ形成する。このゲート電極６をポ
リイミド等を用いた厚さ３μｍの絶縁膜８で覆う。Next, an anode electrode 7 is formed on the back surface of the n-emitter layer 3 by vapor-depositing aluminum, and this anode electrode 7 is
A metal reinforcing plate (not shown) such as a molybdenum plate is attached to the back side of the plate. In addition, by depositing a metal material to a thickness of about 10 μm on the ρ base layer 2 and the entire surface of the n emitter layer 41 and partially removing it by photolithography, the cathode electrode 5 is formed on the convex portion 11 as shown in FIG. A gate electrode 6 is formed on the top surface of the wafer, and a gate electrode 6 is formed on the bottom surface of each of the four parts. This gate electrode 6 is covered with an insulating film 8 made of polyimide or the like and having a thickness of 3 μm.
そして、モリブデンよりなるカソード電極板９の裏面の
うち、ゲート電極６に対向すべき領域以外にマスクを施
し、硝酸等で約２００μｍエツチングし、掘込み部９ａ
を形成する。また、堀込み部９ａあるいは平面部９ｂに
対応するカソード電極板９の表面にマークを入れ、この
マークにより位置ズレすることなく平面部９ｂとカソー
ド電極５と貼り合せる。Then, on the back surface of the cathode electrode plate 9 made of molybdenum, a region other than the region that should face the gate electrode 6 is masked, and etched by about 200 μm with nitric acid or the like, and the dug portion 9a is etched.
form. In addition, a mark is placed on the surface of the cathode electrode plate 9 corresponding to the dug portion 9a or the flat portion 9b, and the mark allows the flat portion 9b and the cathode electrode 5 to be bonded together without misalignment.
このように製造されたＧＴＯのカソード電極板９は第１
図に示すようにゲート電極６とカソード電極５との双方
に対向する広がりを持つとともに、ゲート電極６上にお
いて、カソード電極板９の上面側に向って陥没する堀込
み部９ａを設けた構成となる。その結果、ゲート電極６
とカソード電極５との距離が２００μ而以−ヒとなり、
目視検出可能な金属粒子あるいはシリコン粒子がゲート
電極６あるいは絶縁膜８に付着した以外はゲート電極６
、カソード電極板９間が短絡することはない。The cathode electrode plate 9 of the GTO manufactured in this way is the first
As shown in the figure, a grooved portion 9a is provided on the gate electrode 6, extending toward both the gate electrode 6 and the cathode electrode 5, and recessed toward the upper surface of the cathode electrode plate 9. Become. As a result, the gate electrode 6
The distance between and the cathode electrode 5 is 200μ, so
Gate electrode 6 except that visually detectable metal particles or silicon particles adhere to gate electrode 6 or insulating film 8
, there will be no short circuit between the cathode electrode plates 9.
従って、顕微鏡を用いて金属粒子等を除去する工程は不
用となり、製造工程が簡略化され歩留まりの向上が図れ
る。Therefore, the step of removing metal particles and the like using a microscope is unnecessary, the manufacturing process is simplified, and the yield can be improved.
ざらに、この実施例に加え、カソード電極板９の堀込み
部９ａにエポキシ樹脂等、絶縁物質を流し込む、あるい
は吹き付ける等でカソード電極板９、ゲート電極６間を
充填することでゲート電極６とカソード電極板９との短
絡を完全になくすことが可能となり、絶縁Ｉｌ！８の形
成は不用となる。Roughly, in addition to this embodiment, by filling the space between the cathode electrode plate 9 and the gate electrode 6 by pouring or spraying an insulating material such as epoxy resin into the digging part 9a of the cathode electrode plate 9, the gate electrode 6 can be formed. It becomes possible to completely eliminate short circuits with the cathode electrode plate 9, and the insulation Il! The formation of 8 is unnecessary.
以上説明したように、この発明によれば、電極板の下面
のうち第１の電極に対向する領域に堀込みを設けたため
、異なる電極間が短絡されることはない。As explained above, according to the present invention, since the groove is provided in the region facing the first electrode on the lower surface of the electrode plate, there is no possibility of short-circuiting between different electrodes.
第１図はこの発明の一実施例であるＧＴＯを示す部分断
面図、第２図は従来のＧ、ＴＯを示す部分断面図である
。
図において、５はカソード電極、６はゲート電極、９は
カソード電極板、９ａは堀込み部である。
第１図
なお、各図中同一符号は同一または相当部分を示す。
第２図FIG. 1 is a partial sectional view showing a GTO which is an embodiment of the present invention, and FIG. 2 is a partial sectional view showing a conventional G and TO. In the figure, 5 is a cathode electrode, 6 is a gate electrode, 9 is a cathode electrode plate, and 9a is a trenched portion. FIG. 1 Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 2
Claims (1)
プであって、その最上層を形成する最上部半導体層が前
記半導体チップの上面の一部分のみに突出形成されてい
ることにより、前記半導体チップの上面部が、前記突出
形成による凸部と、前記凸部の周辺部に相当する凹部と
を有する半導体チップと、 前記凹部の底面上に形成された第１の電極と、前記凸部
の上面上に形成された第２の電極と、前記第１と第２の
電極の上方に設けられ、前記第１と第２の電極の双方に
対向する広がりを持つとともに、前記第２の上面に固着
されることで前記第２の電極を介して前記最上部半導体
層に電気的に接続する電極板とを備えた半導体装置にお
いて、 前記電極板の下面のうち前記第１の電極に対向する領域
に、前記電極板の上面側に向って陥没する掘込みを設け
たことを特徴とする半導体装置。(1) A semiconductor chip formed by stacking a plurality of semiconductor layers, in which the top semiconductor layer forming the top layer is formed to protrude from only a part of the top surface of the semiconductor chip. A semiconductor chip whose upper surface has a convex portion formed by the protrusion and a concave portion corresponding to a peripheral portion of the convex portion, a first electrode formed on the bottom surface of the concave portion, and a first electrode formed on the bottom surface of the convex portion. a second electrode formed on the upper surface; and a second electrode provided above the first and second electrodes, extending to face both the first and second electrodes, and on the second upper surface. A semiconductor device comprising: an electrode plate that is fixedly fixed to the uppermost semiconductor layer to be electrically connected to the uppermost semiconductor layer via the second electrode; a region of the lower surface of the electrode plate that faces the first electrode; A semiconductor device, further comprising a recess that is depressed toward the upper surface of the electrode plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12614788A JPH027472A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12614788A JPH027472A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH027472A true JPH027472A (en) | 1990-01-11 |
Family
ID=14927841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12614788A Pending JPH027472A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH027472A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5506425A (en) * | 1993-03-31 | 1996-04-09 | Siemens Components, Inc. | Semiconductor device and lead frame combination |
-
1988
- 1988-05-23 JP JP12614788A patent/JPH027472A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5506425A (en) * | 1993-03-31 | 1996-04-09 | Siemens Components, Inc. | Semiconductor device and lead frame combination |
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