JPS603154A - Amplifying gate type thyristor - Google Patents
Amplifying gate type thyristorInfo
- Publication number
- JPS603154A JPS603154A JP11117483A JP11117483A JPS603154A JP S603154 A JPS603154 A JP S603154A JP 11117483 A JP11117483 A JP 11117483A JP 11117483 A JP11117483 A JP 11117483A JP S603154 A JPS603154 A JP S603154A
- Authority
- JP
- Japan
- Prior art keywords
- electrode film
- cathode electrode
- contact
- auxiliary cathode
- additional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000003321 amplification Effects 0.000 claims description 16
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41716—Cathode or anode electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は増幅ゲート型サイリスタの電極構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an electrode structure of an amplification gate type thyristor.
サイリスタの高速化を目的として開発された増幅ゲ・−
ト型サイリスクは、さらに臨界電流上昇率などの特性向
上の／ζめ、複雑な電極形状をとるものが多くなってい
る。そのような増幅ゲート型サイリスク素子の表面形状
を表わす例を第１図に主要部に斜線を入れた平面図で示
し、第２図には第１図のＡ−Ａ部拡大断面図を示す、第
１図、第２図において、半導体基板１は主表面に複雑な
補助カソード電極膜２と、主カソード電極膜３とを備え
ている。４はゲート電極膜である。さらに、との主カソ
ード電極膜３の上には第３図に示すごとく、平滑な面を
もった導電性金属の接触電極板５が当接される。このよ
うなサイリスク素子が、正常な増幅ゲート動作を維持す
るためには、補助カソード電極膜２と、接触電極板５と
が短絡してはならない。補助カソード電極膜２と接触電
極板５とが電気的に短絡されない配置とするだめの手段
は、第２図、または第３図かられかるが例えば、半導体
基板１の主表面が凹凸面をもつように、薬品等を用いて
、エツチング加工によシ段差を形成し、半導体基板１の
凹部に例えば了ルミ蒸着膜からなる補助カソード電極膜
２と、半導体基板ｌの最外表面に同じくアルミ蒸着膜か
らなる主カソード電＆膜３を設けることによシ行われる
。このようにして半導体基板１の主表面に設けた凹凸面
の高低差によシ、補助カソード電極膜２と接触電極板５
との間に空間絶縁部が生じ、補助カソード電極膜２は、
接触電極板５に当接している主カソード電極膜３と電気
的絶縁状態が保たれ、増幅ゲート動作が行われるのであ
る。An amplification game developed for the purpose of increasing the speed of thyristors.
In order to improve characteristics such as the rate of increase in critical current, many of the T-type Cyrisks have complex electrode shapes. An example of the surface shape of such an amplification gate type thyrisk element is shown in Fig. 1 as a plan view with diagonal lines in the main parts, and Fig. 2 shows an enlarged cross-sectional view of section A-A in Fig. 1. 1 and 2, a semiconductor substrate 1 has a complex auxiliary cathode electrode film 2 and a main cathode electrode film 3 on its main surface. 4 is a gate electrode film. Furthermore, as shown in FIG. 3, a contact electrode plate 5 made of a conductive metal and having a smooth surface is brought into contact with the main cathode electrode film 3 . In order for such a silice element to maintain normal amplification gate operation, the auxiliary cathode electrode film 2 and the contact electrode plate 5 must not be short-circuited. As shown in FIG. 2 or 3, a means for arranging the auxiliary cathode electrode film 2 and the contact electrode plate 5 so that they are not electrically short-circuited is, for example, a method in which the main surface of the semiconductor substrate 1 has an uneven surface. In this way, a step is formed by etching using a chemical or the like, and an auxiliary cathode electrode film 2 made of, for example, a luminescent film is deposited on the concave portion of the semiconductor substrate 1, and an aluminum vapor-deposited film is similarly deposited on the outermost surface of the semiconductor substrate 1. This is done by providing a main cathode and membrane 3 consisting of a membrane. In this way, due to the difference in height between the uneven surfaces provided on the main surface of the semiconductor substrate 1, the auxiliary cathode electrode film 2 and the contact electrode plate 5 are
A space insulation part is created between the auxiliary cathode electrode film 2 and
An electrically insulated state from the main cathode electrode film 3 in contact with the contact electrode plate 5 is maintained, and an amplification gate operation is performed.
しかしながら、このような構造をとっているために必然
的に生ずる欠点は、半導体基板１の主表面に形成される
四部の深さ寸法を０．０２±００１端程度に制御し々け
ればならないという加工上の困難さを伴うことである。However, a drawback that inevitably arises due to such a structure is that the depth dimension of the four parts formed on the main surface of the semiconductor substrate 1 must be controlled to about 0.02±001 edge. This is accompanied by difficulties in processing.
なぜならば、との深さが深すぎると、通常は拡散によっ
て形成しであるｎエミッタまたはｐベースの濃度低下に
よる接触抵抗の増加、シート抵抗の増加のため、このサ
イリスタ素子の特性の劣化を招くからである。一方、凹
部の深さが規定寸法よシ浅すぎた場合には、第４図に示
すように補助カソード電極膜２に、ホトエツチングの精
度の悪さなどに起因して突起部６が生じた場合などに、
この突起部６が接触電極板５に接触してしまうことがあ
ｐｌその結果補助カソード電極膜２と主カソード電極月
々３との電気的な短絡を生じ、増幅ゲート動作が得られ
なくなる。This is because if the depth of the thyristor element is too deep, the characteristics of the thyristor element will deteriorate due to an increase in contact resistance due to a decrease in the concentration of the n-emitter or p-base, which is usually formed by diffusion, and an increase in sheet resistance. It is from. On the other hand, if the depth of the recess is too shallow than the specified dimensions, a protrusion 6 may be formed on the auxiliary cathode electrode film 2 due to poor photoetching accuracy, etc., as shown in FIG. To,
This protrusion 6 may come into contact with the contact electrode plate 5, which results in an electrical short circuit between the auxiliary cathode electrode film 2 and the main cathode electrode 3, making it impossible to obtain an amplification gate operation.
また、第５図に示したように半導体基板１の主表面に設
けた四部に製造工程中に金属微粒子などの異物７が混入
した場合にも、この導電性の異物７を介して、補助カソ
ード電極２と接触電極板５が接触して、上の場合と同じ
ように増幅ゲート動作が得られない。Furthermore, even if foreign matter 7 such as metal particles gets mixed into the four parts provided on the main surface of semiconductor substrate 1 during the manufacturing process as shown in FIG. 5, the auxiliary cathode Since the electrode 2 and the contact electrode plate 5 are in contact with each other, an amplification gate operation cannot be obtained as in the above case.
本発明は上述の欠点を除去して、確実な増幅ゲート動作
の得られる電極渦造とした増幅ゲート型サイリスタを提
供するものである。The present invention eliminates the above-mentioned drawbacks and provides an amplification gate type thyristor with a swirled electrode structure that provides reliable amplification gate operation.
本発明は増幅ゲート型サイリスク素子において主カソー
ド電極膜を補助カソード電極膜よシ厚くすることにょシ
補助カソード電極膜と接触を杉板との短絡を防止して、
上記の目的を達成させるものである。The present invention makes the main cathode electrode film thicker than the auxiliary cathode electrode film in an amplification gate type silice element, thereby preventing short circuit between the auxiliary cathode electrode film and the cedar board.
This is to achieve the above objectives.
以下本発明を図面にもとづいて説明する。第６図に本発
明による電極膜構成の一例を、第２図と同じ個所の増幅
ゲート型サイリスクの断面図で示す。第２図と同一符号
は同一名称をもって表しであるＣ第６図において、主カ
ソード電極膜３上に付加電極膜８が設けられているのに
対し、補助カソード電極２上には付加電極膜を欠くだめ
接触電極板５を付加電極膜８に接触させたとき、補助カ
ソード電極膜２は付加電極膜８の厚さ分だけ接触電極板
５との距離が大きくなるので接触電極板５との短絡が起
らない。主カソード電極膜の厚さは通常２０〜３０μｍ
でちるから、付加電極膜８の厚さを２０〜１００μｍ程
度とすれば、たとえ第４図。The present invention will be explained below based on the drawings. FIG. 6 shows an example of the electrode film structure according to the present invention in a cross-sectional view of the amplification gate type silice at the same location as FIG. 2. The same reference numerals as in FIG. 2 represent the same names.C In FIG. 6, an additional electrode film 8 is provided on the main cathode electrode film 3, whereas an additional electrode film is provided on the auxiliary cathode electrode 2. When the chipped contact electrode plate 5 is brought into contact with the additional electrode film 8, the distance between the auxiliary cathode electrode film 2 and the contact electrode plate 5 increases by the thickness of the additional electrode film 8, so a short circuit with the contact electrode plate 5 occurs. does not occur. The thickness of the main cathode electrode film is usually 20 to 30 μm
Therefore, if the thickness of the additional electrode film 8 is set to about 20 to 100 μm, even if the thickness is as shown in FIG.
第５図に示したようなことが生じたとしても、補助カソ
ード電極膜２と接触電極板５とは短絡することがない。Even if the situation shown in FIG. 5 occurs, the auxiliary cathode electrode film 2 and the contact electrode plate 5 will not be short-circuited.
したがってこのサイリスタ素子はＪ曽幅ゲート動作が正
常に行われる。Therefore, this thyristor element normally performs the J-width gate operation.
この付加電極膜８は導電性の良好な金属であればはじめ
に形成した主カソード電極膜３と利質が同じでもよいし
違ってもよい。第６図の栴成を形づくる具体的な方法と
しては、第１の方法として第７図に示すマスク９を通し
ての選択蒸着法や選択ＣＶＤ法を用いることができる。This additional electrode film 8 may have the same or different quality as the initially formed main cathode electrode film 3 as long as it is a metal with good conductivity. As a specific method for forming the layer shown in FIG. 6, a selective vapor deposition method through a mask 9 shown in FIG. 7 or a selective CVD method can be used as a first method.
ｉだ非電導性のマスクを密着させての一気化学的な選択
析出法を適用してもよい。一般にこれらの選択的な形成
法は形成した皮膜の寸法精度が余シ高くはできないが主
カソード電極膜３を精度良く形成してあれば付加電極膜
８の精度はそれ程高いことを必要とせず、これらの選択
的な形成法で十分である。It is also possible to apply a selective deposition method using a one-shot chemical method in which a non-conductive mask is brought into close contact. In general, these selective formation methods cannot increase the dimensional accuracy of the formed film, but if the main cathode electrode film 3 is formed with high precision, the additional electrode film 8 does not need to have such high precision. These selective formation methods are sufficient.
もち論よシ高精度な方法としてはホトエツチング技術の
適用が考えられる。すなわち、第２の方法はホトエツチ
ング技術を用いたとき主力ンード電極膜に付加する金属
層は素子表面の全面に成長するのであるが、その成長前
にホトレジストを不要部分には残して置き付加された金
属層の成長後にその不要部分に被着した金属層をホトレ
ジストとともに除去する方法であシ、第３の方法として
ホトレジスト技術では最も普通に付加された金稙層の成
長後にホトエッチにょｐ、必要部分すなわち主力ンード
電極部分の付加金属層だけを残す方法がある。Of course, a highly accurate method would be to apply photoetching technology. In other words, in the second method, when photoetching technology is used, the metal layer added to the main electrode film is grown over the entire surface of the element, but before the growth, the photoresist is left in unnecessary areas and the metal layer is added. After the growth of the metal layer, the metal layer deposited on the unnecessary parts is removed together with the photoresist.The third method is to remove the metal layer deposited on the unnecessary parts together with the photoresist.The third method is to remove the metal layer deposited on the unnecessary parts after the growth of the metal layer, which is most commonly added in the photoresist technology, by photoetching the necessary parts. That is, there is a method of leaving only the additional metal layer on the main node electrode portion.
上記のような方法を用いて主カソード電極３の±に付加
電極膜８を形成して補助カソード％ｉ、枠Ｂ？セ２と接
触電極板５との間に絶縁空間を設けることによシ、補助
カソード電極膜と接触電極板との短終を回避でき、増幅
ゲート動作が正常に行われるようになる。Using the method described above, the additional electrode film 8 is formed on the ± of the main cathode electrode 3 to form the auxiliary cathode %i, frame B? By providing an insulating space between the cell 2 and the contact electrode plate 5, short termination between the auxiliary cathode electrode film and the contact electrode plate can be avoided, and the amplification gate operation can be performed normally.
以上説明したごとく本発明によれば半導体基板の主表向
に極めて面倒な、しかも深さ制御が困蛯な凹部を形成す
るための加工が不要となシ、従来方法よシ加工精度の自
由度の大きい被膜形成法の採用によって従来の増幅ゲー
ト型サイリスタに比べて補助カソード電極膜と接触電極
板との間に大きな絶縁空間部を形成することができるの
で短絡を生ずることなく、本発明による増巾ゲート型サ
イリスタは信頼度もさらに向上するという大きな効果を
挙げることができる。As explained above, according to the present invention, there is no need for extremely troublesome machining to form recesses on the main surface of the semiconductor substrate, and the depth control is difficult, and there is greater flexibility in machining accuracy than in conventional methods. By adopting a film formation method with a large resistance, it is possible to form a large insulating space between the auxiliary cathode electrode film and the contact electrode plate compared to conventional amplification gate type thyristors. The width gate type thyristor has the great effect of further improving reliability.
第１図は増幅ゲート型サイリスタの電極構造の平角」図
、第２図は同じく部分断面図、第３図は接触電極板をψ
ｊＩＩえた断面図、第４図、第５図は電極の短絡状態を
示した断面図、第６図は本発明による電極構造の増幅ゲ
ート型サイリスタの断面図。
第７図は付加電極膜を選択形成するだめの配置図である
。
１、半導体基板 ２．補助カソード電極膜３．主カソー
ド電極膜 ４．ゲート電極１ｑ ５．接触電極板 ６゜
補助カソード電極膜の突起部 ７．導電性の異物８、付
加電極膜 ９．付加電極膜選択形成のだめの７２２図
１
７ｊ図 ］Figure 1 is a rectangular view of the electrode structure of an amplification gate type thyristor, Figure 2 is a partial sectional view of the same, and Figure 3 shows the contact electrode plate ψ.
FIG. 4 and FIG. 5 are cross-sectional views showing a short-circuited state of electrodes, and FIG. 6 is a cross-sectional view of an amplification gate type thyristor having an electrode structure according to the present invention. FIG. 7 is a layout diagram for selectively forming additional electrode films. 1. Semiconductor substrate 2. Auxiliary cathode electrode film 3. Main cathode electrode film 4. Gate electrode 1q 5. Contact electrode plate 6° Protrusion of auxiliary cathode electrode film 7. Conductive foreign matter 8, additional electrode film 9. 722 diagram of additional electrode membrane selective formation
Figure 1 7j]
Claims (1)
リスク電極膜および該主サイリスタ電極膜よ！ｌｌＲい
補助サイリスタ電極膜と、前記主サイリスタ電極膜のみ
に接触する接触電極板とを有することを特徴とする増幅
ゲート壓サイリスタ０1) The thyristor electrode film and the main thyristor electrode film provided on the same plane on the main surface of the semiconductor substrate! An amplification gate thyristor 0 characterized in that it has an auxiliary thyristor electrode film and a contact electrode plate that contacts only the main thyristor electrode film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11117483A JPS603154A (en) | 1983-06-21 | 1983-06-21 | Amplifying gate type thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11117483A JPS603154A (en) | 1983-06-21 | 1983-06-21 | Amplifying gate type thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS603154A true JPS603154A (en) | 1985-01-09 |
Family
ID=14554356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11117483A Pending JPS603154A (en) | 1983-06-21 | 1983-06-21 | Amplifying gate type thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603154A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6289360A (en) * | 1985-10-15 | 1987-04-23 | シ−メンス、アクチエンゲゼルシヤフト | Power thyristor |
-
1983
- 1983-06-21 JP JP11117483A patent/JPS603154A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6289360A (en) * | 1985-10-15 | 1987-04-23 | シ−メンス、アクチエンゲゼルシヤフト | Power thyristor |
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