JPH0231872B2 - - Google Patents
Info
- Publication number
- JPH0231872B2 JPH0231872B2 JP59087574A JP8757484A JPH0231872B2 JP H0231872 B2 JPH0231872 B2 JP H0231872B2 JP 59087574 A JP59087574 A JP 59087574A JP 8757484 A JP8757484 A JP 8757484A JP H0231872 B2 JPH0231872 B2 JP H0231872B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- etching
- substrate
- etched
- glaze layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000919 ceramic Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) この発明はパターン形成方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a pattern forming method.
(従来の技術)
たとえばAl配線パターンをエツチングにより
形成することはよく知られている。これはセラミ
ツク製の基板の表面にAlを蒸着又はスパツタに
より薄膜に形成し、これをフオトエツチング処理
によつて、所望のパターンどおりとする方法であ
る。(Prior Art) For example, it is well known that an Al wiring pattern is formed by etching. This is a method in which a thin film of Al is formed on the surface of a ceramic substrate by vapor deposition or sputtering, and then a desired pattern is formed by photoetching the film.
(発明が解決しようとする問題点)
ところで、一般に基板の表面に密のパターンを
エツチングによつて形成する場合、各パターン間
の間隔が小さいので、エツチングすべきAlの量
は少ない。一方粗のパターンの場合では、各パタ
ーン間隔が大きいため、エツチングすべきAlの
量は多い。(Problems to be Solved by the Invention) Generally, when dense patterns are formed on the surface of a substrate by etching, the spacing between each pattern is small, so the amount of Al to be etched is small. On the other hand, in the case of coarse patterns, since the intervals between each pattern are large, the amount of Al to be etched is large.
したがつて粗密混じり合うパターンを基板の表
面に同時に形成しようとするとき、粗密パターン
を同じレートでエツチングすると、次のような不
都合が生ずる。 Therefore, when attempting to simultaneously form patterns in which the sparse and dense patterns are mixed on the surface of the substrate, if the sparse and dense patterns are etched at the same rate, the following disadvantages occur.
密のパターンを基準にエツチング時間、エツチ
ング液量等のエツチング条件を設定すると、密の
パターンは所定の線幅にエツチングできるけれど
も、そのときは粗のパターンはエツチングすべき
Alの量が少ないため、配線パターン間が短絡す
ることがある。 If etching conditions such as etching time and etching liquid amount are set based on a dense pattern, the dense pattern can be etched to a predetermined line width, but in that case, the coarse pattern should be etched.
Because the amount of Al is small, short circuits may occur between wiring patterns.
一方、粗のパターンを基準にしてエツチング条
件を設定すると、密のパターンはエツチングされ
る量が多すぎるため、粗のパターンを所定線幅に
までエツチングしたときは、密のパターンは過剰
にエツチングされてしまい、配線パターンが切断
されることがある。 On the other hand, if the etching conditions are set based on the coarse pattern, the dense pattern will be etched too much, so when the coarse pattern is etched to a predetermined line width, the dense pattern will be etched excessively. This may cause the wiring pattern to be cut.
この発明は、粗密のパターンが混じり合つてい
る場合でも、これを同時にエツチングによつて形
成するとき、粗密のパターンともに最適なエツチ
ングを可能にすることを目的とする。 An object of the present invention is to enable optimum etching of both the coarse and dense patterns when they are simultaneously formed by etching even when coarse and dense patterns are mixed.
(問題点を解決するための手段)
この発明は、基板の表面にグレーズ層を設け、
このグレーズ層の表面に、基板のセラミツク部分
に形成されるパターンよりも微細な間隔のパター
ンをエツチングによつて形成することを特徴とす
る。(Means for solving the problem) This invention provides a glaze layer on the surface of a substrate,
A feature of this method is that a pattern with finer intervals than the pattern formed on the ceramic portion of the substrate is formed on the surface of this glaze layer by etching.
(作 用)
同じエツチング条件でも、セラミツク製の基板
の表面のAlをエツチングするときと、その基板
上のグレーズ層の表面のAlをエツチングすると
きとでは、エツチングレートが異なる。(Function) Even under the same etching conditions, the etching rate is different when etching Al on the surface of a ceramic substrate and when etching Al on the surface of the glaze layer on that substrate.
これを具体例をあげて説明すると、厚さ1〜
2μmのAlについては、セラミツク製基板の表面
におけるエツチングレートは、グレーズ層の表面
におけるそれよりも、約20%大きくなる。 To explain this with a specific example, the thickness is 1~
For 2 μm Al, the etching rate at the surface of the ceramic substrate is approximately 20% greater than that at the surface of the glaze layer.
第1図はAlのエツチング速度特性図を示し、
厚た2μmのAlを、リン酸系エツチング液(液温
40℃)でエツチングしたときの、エツチング時間
に対するエツチングされたAlの厚さを示したも
のである。 Figure 1 shows the etching rate characteristics of Al.
A 2 μm thick Al layer was etched with a phosphoric acid etching solution (solution temperature
This figure shows the thickness of etched Al versus etching time when etching was performed at 40°C.
これからも、セラミツク基板上のAlがグレー
ズ層上のそれよりも、多くエツチングされている
ことが理解される。これはセラミツク基板上の
Al表面が凹凸で、エツチング液との当接面積が
大きいので、エツチングが速くすすむことに起因
するものと考えられる。 It can be seen from this that more Al on the ceramic substrate is etched than on the glaze layer. This is on a ceramic substrate
This is thought to be due to the fact that the Al surface is uneven and has a large contact area with the etching solution, so etching progresses quickly.
したがつて粗密のパターンが混じり合う場合、
密のパターンをエツチングレートの小さいグレー
ズ層の表面に形成してエツチングすれば、密のパ
ターンのエツチングされるAlの量は抑制され、
粗密ともに最適にエツチングできるようになる。 Therefore, when coarse and dense patterns are mixed,
If a dense pattern is formed on the surface of a glaze layer with a low etching rate and then etched, the amount of Al etched in the dense pattern is suppressed.
Optimal etching can be achieved in terms of density and roughness.
(実施例)
第2図はこの発明の実施例方法を示すもので、
セラミツク、たとえばアルミナセラツミツク製の
基板1の表面にAl配線パターンをエツチングで
形成するのに、パターン間隔が微細な(密の)配
線部2を形成するとき、その配線部2は、基板1
上に予め形成したグレーズ層3の表面に形成す
る。(Example) Figure 2 shows an example method of this invention.
When an Al wiring pattern is formed by etching on the surface of a substrate 1 made of ceramic, for example, alumina ceramic, and a wiring portion 2 with fine (dense) pattern spacing is formed, the wiring portion 2 is formed on the substrate 1.
It is formed on the surface of the glaze layer 3 previously formed thereon.
具体的には、配線部2の形成予定位置に予めグ
レーズ層3を形成しておき、ついで基板1の表面
(グレーズ層3の表面も含む。)にAlの薄膜を形
成してから、フオトエツチングにより配線部2
を、パターン間隔が粗の配線部4と同時に形成す
ればよい。 Specifically, a glaze layer 3 is formed in advance at the position where the wiring portion 2 is planned to be formed, and then a thin film of Al is formed on the surface of the substrate 1 (including the surface of the glaze layer 3), and then photo-etching is performed. Wiring section 2
may be formed at the same time as the wiring portion 4 with coarse pattern spacing.
配線部2におけるエツチング量は、配線部4の
それより少ないので、配線部2が所定の線幅にエ
ツチングされる頃には、配線部4も所定の線幅に
エツチングされるようになり、したがつて両配線
部2,4は最適にエツチングされることになる。 Since the amount of etching in the wiring part 2 is smaller than that in the wiring part 4, by the time the wiring part 2 is etched to a predetermined line width, the wiring part 4 is also etched to a predetermined line width. As a result, both wiring portions 2 and 4 are etched optimally.
なおここに使用できるグレーズ層としては、そ
の組成が、SiO2、MgO2、Zr2O3系のものが好適
である。また以上の説明はパターンの形成対象と
してAlの場合について説明したが、Cu、Auなど
についても同様の効果が得られることが確認され
ている。 Note that the glaze layer that can be used here preferably has a composition based on SiO 2 , MgO 2 , and Zr 2 O 3 . Furthermore, although the above description has been made regarding the case of Al as the pattern forming target, it has been confirmed that similar effects can be obtained with Cu, Au, and the like.
(発明の効果)
以上詳述したようにこの発明によれば、基板表
面に粗密の混じり合うパターンを同時にエツチン
グによつて形成する場合、粗密のパターンともに
最適にエツチングできる効果を奏する。(Effects of the Invention) As described in detail above, according to the present invention, when a mixture of coarse and dense patterns is simultaneously formed on the surface of a substrate by etching, both the coarse and dense patterns can be etched optimally.
第1図はエツチング速度を示す特性図、第2図
はこの発明の実施例方法を説明するための基板の
平面図である。
1……基板、2……パターン間隔が微細な配線
部、3……グレーズ層、4……パターン間隔が粗
い配線部。
FIG. 1 is a characteristic diagram showing the etching rate, and FIG. 2 is a plan view of a substrate for explaining an embodiment of the method of the present invention. 1...Substrate, 2...Wiring portion with fine pattern spacing, 3...Glaze layer, 4... Wiring portion with coarse pattern spacing.
Claims (1)
が粗密混じり合うパターンをエツチングによつて
同時に形成する方法において、 前記基板の表面にグレーズ層を設け、前記グレ
ーズ層の表面に、前記基板のセラミツク部分に形
成されるパターンよりも微細な間隔のパターンを
エツチングによつて形成することを特徴とするパ
ターン形成方法。[Scope of Claims] 1. A method for simultaneously forming, by etching, on the surface of a ceramic substrate a pattern in which the pattern spacing is mixed in spacing and density, the method comprising: providing a glaze layer on the surface of the substrate; and on the surface of the glaze layer, A pattern forming method comprising forming by etching a pattern with finer intervals than the pattern formed on the ceramic portion of the substrate.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8757484A JPS60231386A (en) | 1984-04-28 | 1984-04-28 | Method of forming pattern |
JP32301989A JPH02216890A (en) | 1984-04-28 | 1989-12-13 | Forming method for pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8757484A JPS60231386A (en) | 1984-04-28 | 1984-04-28 | Method of forming pattern |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32301989A Division JPH02216890A (en) | 1984-04-28 | 1989-12-13 | Forming method for pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60231386A JPS60231386A (en) | 1985-11-16 |
JPH0231872B2 true JPH0231872B2 (en) | 1990-07-17 |
Family
ID=13918769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8757484A Granted JPS60231386A (en) | 1984-04-28 | 1984-04-28 | Method of forming pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60231386A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02216890A (en) * | 1984-04-28 | 1990-08-29 | Rohm Co Ltd | Forming method for pattern |
US4751142A (en) * | 1985-09-18 | 1988-06-14 | Kyocera Corporation | Magneto-optical recording element |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54152163A (en) * | 1978-05-22 | 1979-11-30 | Shinetsu Polymer Co | Circuit board and method of producing same |
JPS56131992A (en) * | 1980-03-19 | 1981-10-15 | Tokyo Shibaura Electric Co | Glazed board |
-
1984
- 1984-04-28 JP JP8757484A patent/JPS60231386A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54152163A (en) * | 1978-05-22 | 1979-11-30 | Shinetsu Polymer Co | Circuit board and method of producing same |
JPS56131992A (en) * | 1980-03-19 | 1981-10-15 | Tokyo Shibaura Electric Co | Glazed board |
Also Published As
Publication number | Publication date |
---|---|
JPS60231386A (en) | 1985-11-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |