JPS60198745A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS60198745A
JPS60198745A JP59054931A JP5493184A JPS60198745A JP S60198745 A JPS60198745 A JP S60198745A JP 59054931 A JP59054931 A JP 59054931A JP 5493184 A JP5493184 A JP 5493184A JP S60198745 A JPS60198745 A JP S60198745A
Authority
JP
Japan
Prior art keywords
conductive film
section
film layer
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59054931A
Other languages
Japanese (ja)
Inventor
Norihiko Kamiyama
神山　規彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP59054931A priority Critical patent/JPS60198745A/en
Publication of JPS60198745A publication Critical patent/JPS60198745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To improve the degree of integration of a power supply line section, and to facilitate measurement work by forming a stepped section, the thickness thereof is thinned, in one part of an electrode pad region in the end section of a wiring metallic layer shaped on a semiconductor substrate. CONSTITUTION:A conductive film layer 13 is evaporated on an insulating layer 12 on a semiconductor substrate 11, thus forming a signal detecting pad for a semiconductor integrated circuit device. The conductive film layer 13 is removed through etching only by the thickness (d) of the layer 13 while leaving one part of a signal pad region for the semiconductor integrated circuit consisting of the conductive film layer 13 and a wiring region section. According to such constitution, a needle picking up signals is erected easily by erecting the needle to a section having a stepped section. Width can be narrowed becaused the thickness of the conductive film layer 13 is shaped thickly in a power supply wiring section even in a wiring, and the degree of integration is improved.

Description

【発明の詳細な説明】 技術分野 本発明は半導体集積回路装置用検出パッドに関する。[Detailed description of the invention] Technical field The present invention relates to a detection pad for a semiconductor integrated circuit device.

従来技術 よる回路途中の半導体集積回路装置用信号検出パッドで
の信号チェムクが増加している。第１図に従来の半導体
集積回路装置用信号検出パッドの平面図、断面図を示す
。半導体基板１の上の絶縁層２及びその上部に信号検出
用導電膜層３とで形成されている。従来は信号検出導電
膜層３が平らな几め導電膜層に針を立て信号を拾うとき
針が滑りく集積度の同上に支障があるという欠点があっ
た。According to the prior art, signal check is increasing at a signal detection pad for a semiconductor integrated circuit device in the middle of a circuit. FIG. 1 shows a plan view and a sectional view of a conventional signal detection pad for a semiconductor integrated circuit device. It is formed of an insulating layer 2 on a semiconductor substrate 1 and a signal detection conductive film layer 3 on top of the insulating layer 2. Conventionally, when the signal detecting conductive film layer 3 picks up a signal by setting a needle on the flat, narrow conductive film layer, the needle slips, causing problems in terms of integration.

発明の目的 本発明の目的は従来の欠点である電源線部分の集積度の
低下と測定作業がし易い信号検出パッドを備えた半導体
集積回路装置を提供するにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that overcomes the disadvantages of the prior art, such as a reduction in the degree of integration of the power supply line portion, and that is equipped with a signal detection pad that facilitates measurement work.

発明の溝底 本発明は半導体基板上に形成された配線金属層の端部の
電極バッド領域の１部において厚みを薄くした段差部ｔ
−有する半導体集積回路装置を得る。Groove Bottom of the Invention The present invention provides a stepped portion t having a reduced thickness in a part of an electrode pad region at an end of a wiring metal layer formed on a semiconductor substrate.
- Obtaining a semiconductor integrated circuit device having:

実施例 第２図ｔａ）、　を切に本発明の第１の実施例の平面図
および断面図を示す。半導体基板１１の上の絶縁層１２
の上に導電膜層１３が蒸着されて半導体集積回路装置用
信号検出パッドが形成される。次に導電膜層１３から成
る半導休業積回路装置用信号パッド領域の１部分及び配
線領吠部分を残して導電膜層１３を厚みｄだけエツチン
グ除去する。Embodiment FIG. 2 (ta) shows a plan view and a sectional view of a first embodiment of the present invention. Insulating layer 12 on semiconductor substrate 11
A conductive film layer 13 is deposited thereon to form a signal detection pad for a semiconductor integrated circuit device. Next, the conductive film layer 13 is etched away by a thickness d, leaving a portion of the signal pad area for the semiconductor integrated circuit device and a wiring area made of the conductive film layer 13.

本発明によれば段差ｔ−Ｎシている部分に信号を拾う針
を立てることによって容易に針が滑らずに。According to the present invention, by setting the needle to pick up the signal on the part where there is a step t-N, the needle does not slip easily.

他の信号線や半導体素子を破壊することなくでき。This can be done without destroying other signal lines or semiconductor elements.

同時に配線においても導電膜層１３の厚みが電源配線部
分では厚く形成されるため４１ｉｆｔ狭くで！！集積度
を向上させる効果が得られる。At the same time, in the wiring, the thickness of the conductive film layer 13 is thicker in the power supply wiring part, so it is 41ft narrower! ! The effect of improving the degree of integration can be obtained.

第３図（ａ）および（りに本発明の第２の実施例の平面
図、断面図を示すが、半導体基板２１の上の絶縁層２２
上に導電膜層２３（導電膜層１３）を蒸着するまでは前
述の第１の実施例と同様に行う。3(a) and 3(a) show a plan view and a sectional view of the second embodiment of the present invention, in which an insulating layer 22 on a semiconductor substrate 21 is shown.
The same procedure as in the first embodiment described above is performed until the conductive film layer 23 (conductive film layer 13) is deposited thereon.

導電膜層°２３の一部を除去するのに信号検出パッド部
分のみ第１の５Ａ施例とは凹凸部を逆にエツチング除去
してもよい。To remove a portion of the conductive film layer 23, only the signal detection pad portion may be etched to remove the uneven portion, contrary to the first 5A embodiment.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）および（ｂ）は従来の半導体装置を示す平
面図および第１図（ａ）のｘ−ｘ’での断面図である。 第２図（ａ）およびｔｂ）は本発明の第１の実施例を示
す平面図および第２図（ａ）のＹ−Ｙ／での断面図。 第３図（句および（ｂ）は本発明の第２の実施例を示す
平面図および第３図ｆａ）の２−２′での断面図である
。 １．１１．２１・・・・・・半導体基板、２，１２゜２
２・・・・・・絶縁層、３，１３．２３・・・・・・導
電膜層。 １４．２４・・・・・・導電膜層のエツチング除去部分
。 ｄ・・・・・・導電膜層の除去厚み。 第１図 第２図FIGS. 1(a) and 1(b) are a plan view showing a conventional semiconductor device and a sectional view taken along line xx' in FIG. 1(a). FIGS. 2(a) and tb) are a plan view and a sectional view taken along YY/ in FIG. 2(a), showing a first embodiment of the present invention. FIGS. 3(b) and 3(b) are a plan view and a sectional view taken along line 2-2' of FIG. 3fa showing a second embodiment of the present invention. 1.11.21...Semiconductor substrate, 2,12゜2
2... Insulating layer, 3,13.23... Conductive film layer. 14.24... Etched removed portion of the conductive film layer. d... Removal thickness of the conductive film layer. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成されｔ端部に電極パッドを備え几配
線層と、核配線層の前記電極パッド部がその１部におい
て厚みが薄くなっていることを特徴とする半導体集積回
路装置。1. A semiconductor integrated circuit device formed on a semiconductor substrate and having an electrode pad at a t-end thereof, and characterized in that the electrode pad portion of the core wiring layer is thin in a portion thereof.
JP59054931A 1984-03-22 1984-03-22 Semiconductor integrated circuit device Pending JPS60198745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59054931A JPS60198745A (en) 1984-03-22 1984-03-22 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59054931A JPS60198745A (en) 1984-03-22 1984-03-22 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60198745A true JPS60198745A (en) 1985-10-08

Family

ID=12984368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59054931A Pending JPS60198745A (en) 1984-03-22 1984-03-22 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60198745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179439U (en) * 1988-06-06 1989-12-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179439U (en) * 1988-06-06 1989-12-22

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