JPS54161285A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS54161285A JPS54161285A JP7050178A JP7050178A JPS54161285A JP S54161285 A JPS54161285 A JP S54161285A JP 7050178 A JP7050178 A JP 7050178A JP 7050178 A JP7050178 A JP 7050178A JP S54161285 A JPS54161285 A JP S54161285A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- wiring
- layer
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
PURPOSE: To obtain a fine and high-density wiring easily with excellent mass- producibility by eliminating a shift in position, by forming the internal wiring, made of a three-layer metal thin film, between semiconductor elements by single etching process.
CONSTITUTION: Onto Si substrate 101, SiO2 film 102 is bonded, contact hole 103 is made in a desired region, and Pt.Si layer 104 is formed there, thereby constituting semiconductor element 105. At the side of film 102, the 1st metal Ti film 106 and 2nd metal Pt film 107 are bonded by stacking and resist-film pattern 108 is formed at a wiring equivalent part. Then, this is used as a mask to etch and remove the exposed part of thin film 107 by using aqua regia, Al film 109 is bonded onto the entire surface, and pattern 108 is removed together with film 109 on it. Next, the surface layers part of remaining film 109 is converted into Al2O3 film 109' through a heat treatment and the 3rd metal Au film 110 as main wiring is stacked on film 109 exposed on Pt.Si layer 104 by plating, thereby obtaining internal wiring 111 of Ti-Pt-Au three-layer structure.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7050178A JPS54161285A (en) | 1978-06-12 | 1978-06-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7050178A JPS54161285A (en) | 1978-06-12 | 1978-06-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54161285A true JPS54161285A (en) | 1979-12-20 |
Family
ID=13433326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7050178A Pending JPS54161285A (en) | 1978-06-12 | 1978-06-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54161285A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5094979A (en) * | 1989-03-03 | 1992-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device |
| US5266519A (en) * | 1991-11-12 | 1993-11-30 | Nec Corporation | Method for forming a metal conductor in semiconductor device |
| US5275973A (en) * | 1993-03-01 | 1994-01-04 | Motorola, Inc. | Method for forming metallization in an integrated circuit |
| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
-
1978
- 1978-06-12 JP JP7050178A patent/JPS54161285A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
| US5094979A (en) * | 1989-03-03 | 1992-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device |
| US5266519A (en) * | 1991-11-12 | 1993-11-30 | Nec Corporation | Method for forming a metal conductor in semiconductor device |
| US5275973A (en) * | 1993-03-01 | 1994-01-04 | Motorola, Inc. | Method for forming metallization in an integrated circuit |
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