JPH0227835B2 - - Google Patents
Info
- Publication number
- JPH0227835B2 JPH0227835B2 JP56171412A JP17141281A JPH0227835B2 JP H0227835 B2 JPH0227835 B2 JP H0227835B2 JP 56171412 A JP56171412 A JP 56171412A JP 17141281 A JP17141281 A JP 17141281A JP H0227835 B2 JPH0227835 B2 JP H0227835B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- thick film
- thin film
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 38
- 239000010409 thin film Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 35
- 239000000758 substrate Substances 0.000 description 27
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、多層配線に用いる配線基板の製造方
法に係るもので特に薄膜・厚膜混成方式の配線基
板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a wiring board used for multilayer wiring, and particularly to a method of manufacturing a wiring board of a thin film/thick film hybrid type.
電子計算機等に用いる大容量の混成集積回路用
多層配線基板として、一般に配線を厚膜印刷焼結
方式で形成し、基板および層間絶縁物としてアル
ミナセラミツクを用いた基板が用いられている。
ところが近年、電子計算機において高機能、高速
化の要請が強く、この結果大配線容量の混成集積
回路用基板が要求されるようになつた。厚膜アル
ミナセラミツク基板では、配線密度が印刷工程の
精度で限定され（最小可能配線ピツチ150μｍ）
るため、配線層５〜10層、絶縁層５〜10層の多層
で基板寸法100mm□
の基板が出現している。層数
の増大は各層間の接続点数を大幅に増すため、基
板製造歩留の大幅低下をもたらすという欠点があ
る。また基板の大型化は、信号伝送路の増大をき
たすため高速化が図れない。 As a multilayer wiring board for a large-capacity hybrid integrated circuit used in an electronic computer or the like, a board is generally used in which wiring is formed by a thick film printing and sintering method and alumina ceramic is used as the board and interlayer insulator.
However, in recent years, there has been a strong demand for higher functionality and higher speed in electronic computers, and as a result, a substrate for hybrid integrated circuits with a large wiring capacity has become required. For thick-film alumina ceramic substrates, the wiring density is limited by the precision of the printing process (minimum possible wiring pitch of 150 μm).
As a result, multilayer boards with 5 to 10 wiring layers and 5 to 10 insulating layers and a board size of 100 mm have appeared. An increase in the number of layers greatly increases the number of connection points between each layer, which has the disadvantage of significantly reducing the board manufacturing yield. Furthermore, increasing the size of the board increases the number of signal transmission paths, making it impossible to increase the speed.
そこで、配線形成を半導体工業のプロセスであ
る薄膜ホトプロセスを用いることが試みられてい
る。薄膜プロセスを用いて多層化した基板では、
電子計算機用混成集積回路基板として必要なコネ
クタの着脱に耐える数百本の端子をとりだすこと
は一般に困難である。この端子に関しては基板裏
面全域に焼結タングステンにNiメツキしたピン
接続部を配列し、この接続部に銀ろうあるいはは
んだろうでリードピンを接続している従来の厚膜
多層配線基板が適している。ところで高密度、高
速化を要する回路領域は論理信号回路である。電
源回路グランド層は、従来の厚膜多層配線の配線
密度で十分余裕がある。したがつて、論理信号層
を薄膜基板部として形成し、電源グランド層やリ
ードピン端子部を厚膜基板部として形成した薄膜
−厚膜混成方式で高密度、高速基板を達成でき
る。 Therefore, attempts have been made to use thin film photoprocessing, which is a process used in the semiconductor industry, to form interconnections. In multilayer substrates using thin film process,
It is generally difficult to extract several hundred terminals that can withstand the connection and disconnection of connectors required for a hybrid integrated circuit board for an electronic computer. For this terminal, a conventional thick-film multilayer wiring board is suitable, in which pin connection parts made of sintered tungsten plated with Ni are arranged over the entire back surface of the board, and lead pins are connected to these connection parts with silver solder or solder. By the way, a circuit area that requires high density and high speed is logic signal circuits. The power supply circuit ground layer has sufficient margin with the wiring density of conventional thick-film multilayer wiring. Therefore, a high-density, high-speed substrate can be achieved using a thin film/thick film hybrid method in which the logic signal layer is formed as a thin film substrate part, and the power ground layer and lead pin terminal part are formed as a thick film substrate part.
薄膜−厚膜混成方式の多層配線基板の製造は、
第１図に示す工程でできる。焼結タングステンか
らなる電源・グランド層２リードピン端子部３を
含む厚膜基板部１０を通常の厚膜多層基板の製法
であるグリンシード法で形成する。薄膜基板部の
配線と接続する厚膜配線端子４をアルミナ絶縁層
５のスルホールに穴うめして形成しておく。この
厚膜基板部１０の上面に薄膜基板部の配線部とな
る配線膜６を通常の薄膜プロセスである抵抗加熱
蒸着あるいはスパツクにてAlあるいはCr／Cu／
Crで形成し、ネガ型レジストを用いるホトリゾ
エツチングで配線膜６をパターン化する。このと
き配線端子４と配線パターン６を必ず重ね合せ
る。厚膜基板部１０は製造時の焼結収縮にばらつ
きがあり端子４の位置ばらつきは基板中心からみ
てその位置の中心からの距離の0.6〜1.0％とな
る。このため、両基板部の接続を基板全域で図る
ためには、位置ばらつきの幅を厚膜配線端子４あ
るいは配線パターン６の接続部に与えなければな
らない。このため、配線パターン６は高密度配線
化が図れるホトリゾエツチング工程を用いなが
ら、厚膜配線基板部の配線密度と同じにしなけれ
ばならない。この上に、通常の薄膜プロセスで形
成するSiO2やポリイミド膜を絶縁層７とし、そ
のスルホール８をホトリゾエツチングで形成す
る。こののち絶縁層７の上面に配線パターン６１
を配線パターン６と同様に形成し更に絶縁層７
１、スルホール８１を絶縁層７、スルホール８と
同様に形成する。これらの工程を繰返して薄膜基
板部１１を形成し、高密度、高速用の多層配線基
板となる。 The production of multilayer wiring boards using thin film and thick film hybrid methods is as follows:
This can be done through the steps shown in Figure 1. A thick film substrate section 10 including a power supply/ground layer 2 and a lead pin terminal section 3 made of sintered tungsten is formed by the Grinseed method, which is a conventional thick film multilayer substrate manufacturing method. Thick film wiring terminals 4 to be connected to wiring on the thin film substrate portion are formed by filling through holes in the alumina insulating layer 5. On the upper surface of this thick film substrate section 10, a wiring film 6, which will become the wiring section of the thin film substrate section, is formed by resistive heating vapor deposition or spacing, which is a normal thin film process, such as Al or Cr/Cu/
The wiring film 6 is made of Cr and patterned by photolithography using a negative resist. At this time, the wiring terminal 4 and the wiring pattern 6 must be overlapped. The thick film substrate portion 10 has variations in sintering shrinkage during manufacturing, and the variations in the position of the terminals 4 are 0.6 to 1.0% of the distance from the center of the substrate. Therefore, in order to connect both substrate parts over the entire substrate area, it is necessary to provide a width of positional variation to the connection part of the thick film wiring terminal 4 or the wiring pattern 6. For this reason, the wiring pattern 6 must be made to have the same wiring density as that of the thick film wiring board portion, while using a photolithography process that allows for high-density wiring. On top of this, an insulating layer 7 is made of SiO 2 or polyimide film formed by a normal thin film process, and through holes 8 are formed by photolithography. After this, a wiring pattern 61 is placed on the upper surface of the insulating layer 7.
is formed in the same manner as the wiring pattern 6, and then an insulating layer 7 is formed.
1. Through holes 81 are formed in the same manner as insulating layer 7 and through holes 8. These steps are repeated to form the thin film substrate portion 11, resulting in a high-density, high-speed multilayer wiring board.
この多層配線基板では高密度化になんら寄与し
ない厚膜−薄膜接続の適合のための層がパターン
６層および絶縁層７と２層要しており、このため
工程が冗長され、歩便り低下の原因だけとなつて
いる。 This multilayer wiring board requires two layers, a pattern 6 layer and an insulating layer 7, for adapting thick-film-thin-film connections that do not contribute to high density, resulting in redundant processes and a reduction in process efficiency. It has become only the cause.
また、第１図の配線端子４には、パターン６で
覆われない個所が必ず発生する。これはパターン
６のパターン化時のエツチング液が配線端子４に
触れるため、パターン６のエツチングへの悪影響
や、また配線端子４を酸化させ、信頼性を落す原
因となる。また厚膜基板部１０の表面粗さは通常
３〜4μｍあるため、ホトリゾエツチングのパタ
ーン６のパターン化が困難であり、表面粗さ３〜
4μｍ上のパターン６の配線抵抗の安定性が悪い
ことがわかつている。 Further, in the wiring terminal 4 shown in FIG. 1, there will always be a portion that is not covered with the pattern 6. This is because the etching solution during patterning of the pattern 6 comes into contact with the wiring terminal 4, which has an adverse effect on the etching of the pattern 6, and also oxidizes the wiring terminal 4, causing a drop in reliability. Furthermore, since the surface roughness of the thick film substrate portion 10 is usually 3 to 4 μm, it is difficult to pattern the pattern 6 by photolithography.
It is known that the stability of the wiring resistance of pattern 6 on 4 μm is poor.
本発明の目的は、以上の製造上の欠点を除き、
薄膜・厚膜混成方式の高密度、高速用の多層配線
基板の製造方法を提供することにある。 The purpose of the present invention is to eliminate the above manufacturing disadvantages,
An object of the present invention is to provide a method for manufacturing a multilayer wiring board for high density and high speed using a thin film/thick film hybrid method.
本発明の特徴は、厚膜配線基板部の薄膜配線基
板部と接続すべき配線端子の大きさを、厚膜配線
の位置ずれ量を見込んで形成し、その上部に絶縁
層を形成し、この絶縁層にいわゆる薄膜プロセス
であるホトリゾグラフイでスルホールを形成し、
以後、薄膜プロセスを用いて薄膜多層配線基板部
を形成して厚膜薄膜混成の多層配線基板を製造す
るものである。 The feature of the present invention is that the size of the wiring terminal to be connected to the thin film wiring board part of the thick film wiring board part is determined by taking into account the amount of positional deviation of the thick film wiring, and an insulating layer is formed on top of the wiring terminal. Through holes are formed in the insulating layer using photolithography, a so-called thin film process.
Thereafter, a thin film multilayer wiring board section is formed using a thin film process to manufacture a thick film/thin film hybrid multilayer wiring board.
以下第２図に示す実施例により、本発明を具体
的に説明する。同図ａは厚膜配線基板部を作る方
法を説明する図、同図ｂは厚膜配線基板部に薄膜
配線基板部を形成する方法を説明する図である。 The present invention will be specifically explained below with reference to the embodiment shown in FIG. FIG. 1A is a diagram illustrating a method for forming a thick film wiring board section, and FIG. 1B is a diagram explaining a method for forming a thin film wiring board section on a thick film wiring board section.
図に示す１０は、タングステンの焼結体からな
る電源配線層やグランド層２を含む、グリンシー
ト法で製造したアルミナ厚膜多層配線基板部１０
である。配線端子４はアルミナ絶縁層５のスルホ
ールにタングステンペースドを穴うめ焼結して形
成されている。配線端子４の径は、接続する薄膜
のスルホール径に（グリンシート法での焼結収縮
ばらつき0.6〜1.0％Ｘ基板の長辺寸法×1/2）を
加えた径とする。基板寸法を50cm□
、薄膜スルホ
ール径を50μｍとすると、端子の径は250μｍ前後
とする。基板部１０の裏面には焼結タングステン
パツドに銀ろうで接続されたリードピン９がつい
ている。配線端子４はアルミナ絶縁層５の上面と
同一平面もしくは10μｍ以下で突出するように形
成されている。この基板部１０にポリイミド樹脂
をスピンコーテイング方式で塗布し、熱硬化して
絶縁層７を形成する。この絶縁層７にネガ型レジ
スト（例えば東京応化製のOMR83）をコーテイ
ングし、レジストを紫外線露光でパターン化し、
湿式エツチングで配線端子４の上部の絶縁層７に
スルホール８を形成する。スルホール８の形成に
ネガ型レジストを用いるのは、厚膜基板部１が硬
く、そり、うねりがあるため、もろいポジ型レジ
ストでは露光時にマスクとの接触でレジストがは
く離し、絶縁層７にピンホールが発生するのを避
けることにある。そして配線端子４の上面をアル
ミナ絶縁層の上面より沈めないのは、ネガ型レジ
ストを用いるので、露光時にマスクと間隙があく
と紫外光のまわりこみでスルホール８が形成でき
なくなるのを避けるためである。スルホール８形
成後、抵抗加熱あるいはエレクトロンビーム蒸着
スパツタなどでアルミあるいはチタン＋銅＋チタ
ン膜６を形成し通常のホトリゾ工程でパターン化
する。この配線６は絶縁層７の上でのパターン化
のため表面粗さの大きい厚膜多層配線基板部１０
（表面粗さ４〜6μｍ）上と異なり、20〜40μｍピ
ツチでの配線化ができ、厚膜基板部１０の影響を
受けない。そして配線パターン６のパターン化の
際にそのエツチング液が配線端子４に触れること
はない。以降、この上部にポリイミド樹脂層７１
と配線層６１を繰返し形成し、薄膜多層配線基板
部１１を形成する。したがつて、厚膜・薄膜の適
合層は絶縁層７一層となる。これにより高密度配
線の多層配線基板が形成される。なお、リードピ
ン９は、薄膜配線基板部１１を形成したあとに付
けてもよい。 10 shown in the figure is an alumina thick film multilayer wiring board section 10 manufactured by the green sheet method, including a power supply wiring layer and a ground layer 2 made of sintered tungsten.
It is. The wiring terminals 4 are formed by filling through holes in the alumina insulating layer 5 with tungsten paste and sintering them. The diameter of the wiring terminal 4 is the diameter of the through hole of the thin film to be connected plus (sintering shrinkage variation in the green sheet method 0.6 to 1.0% x long side dimension of the substrate x 1/2). Assuming that the substrate dimensions are 50 cm□ and the diameter of the thin film through hole is 50 μm, the diameter of the terminal will be approximately 250 μm. A lead pin 9 connected to a sintered tungsten pad with silver solder is attached to the back surface of the substrate part 10. The wiring terminal 4 is formed to be flush with the upper surface of the alumina insulating layer 5 or to protrude by 10 μm or less. Polyimide resin is applied to this substrate portion 10 by spin coating, and is thermally cured to form an insulating layer 7. This insulating layer 7 is coated with a negative resist (for example, OMR83 manufactured by Tokyo Ohka), and the resist is patterned by UV exposure.
Through holes 8 are formed in the insulating layer 7 above the wiring terminals 4 by wet etching. The reason why a negative resist is used to form the through holes 8 is that the thick film substrate portion 1 is hard and has warps and undulations, so if a brittle positive resist is used, the resist will peel off when it comes into contact with the mask during exposure, causing pins to form on the insulating layer 7. The purpose is to avoid holes from occurring. The reason why the upper surface of the wiring terminal 4 is not sunk below the upper surface of the alumina insulating layer is to avoid forming the through hole 8 due to the penetration of ultraviolet light if there is a gap between the mask and the mask during exposure since a negative resist is used. . After forming the through holes 8, an aluminum or titanium+copper+titanium film 6 is formed by resistance heating or electron beam evaporation sputtering, and patterned by a normal photolithography process. This wiring 6 is patterned on the insulating layer 7, so a thick film multilayer wiring board part 10 with a large surface roughness is formed.
(Surface roughness 4 to 6 μm) Unlike the above, wiring can be done at a pitch of 20 to 40 μm and is not affected by the thick film substrate portion 10. When patterning the wiring pattern 6, the etching solution does not come into contact with the wiring terminals 4. Thereafter, a polyimide resin layer 71 is formed on top of this.
The wiring layer 61 is repeatedly formed to form the thin film multilayer wiring board section 11. Therefore, the compatible layer for thick and thin films is the insulating layer 7. As a result, a multilayer wiring board with high-density wiring is formed. Note that the lead pins 9 may be attached after the thin film wiring board section 11 is formed.
以上のように、本発明によれば、従来の厚膜多
層配線基板より２〜３倍の高密度化が図れる。従
つて配線層数、スルホール接続数が低減でき、製
品歩留りが向上し、更にコネクタ着脱に耐える多
端子のとりだしが容易に図れる。 As described above, according to the present invention, the density can be increased two to three times as much as that of the conventional thick film multilayer wiring board. Therefore, the number of wiring layers and through-hole connections can be reduced, product yield can be improved, and multiple terminals that can withstand connector attachment and detachment can be easily taken out.
第１図は薄膜混成多層基板の従来製造方法を説
明する図、第２図は本発明の実施例を説明する図
である。
１０……厚膜多層配線基板部、１１……薄膜多
層配線基板部、４……厚膜基板部の配線端子、５
……厚膜基板部の絶縁層、７，７１……薄膜基板
部の絶縁層、６，６１……薄膜基板部の配線、９
……リードピン。
FIG. 1 is a diagram illustrating a conventional manufacturing method of a thin film hybrid multilayer substrate, and FIG. 2 is a diagram illustrating an embodiment of the present invention. 10... Thick film multilayer wiring board part, 11... Thin film multilayer wiring board part, 4... Wiring terminal of thick film board part, 5
... Insulating layer of thick film substrate part, 7, 71 ... Insulating layer of thin film substrate part, 6, 61 ... Wiring of thin film substrate part, 9
...Lead pin.
Claims (1)
混成構成の多層配線基板の製造方法において、厚
膜配線基板部の薄膜配線基板部と接続すべき配線
端子の大きさを、厚膜配線の位置ずれ量を見込ん
で厚膜配線基板部の上部面に形成し、その上部に
絶縁層を形成し、この絶縁層にホトリゾエツチン
グ法によりスルーホールを形成し、このスルーホ
ールを介して両基板部間の配線接続を行なうこと
を特徴とする多層配線基板の製造方法。 ２ 上記配線端子を、その上面が厚膜配線基板部
の上部面よりも少なくとも沈まないように形成し
た特許請求の範囲第１項記載の多層配線基板の製
造方法。[Claims] 1. In a method for manufacturing a multilayer wiring board having a hybrid configuration consisting of a thick film wiring board section and a thin film wiring board section, the size of the wiring terminal to be connected to the thin film wiring board section of the thick film wiring board section is formed on the upper surface of the thick film wiring board part in anticipation of the amount of misalignment of the thick film wiring, an insulating layer is formed on top of the insulating layer, and a through hole is formed in this insulating layer by photolithography. A method for manufacturing a multilayer wiring board, characterized in that wiring connections are made between both board parts via holes. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the wiring terminal is formed so that its upper surface does not sink below the upper surface of the thick film wiring board portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17141281A JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17141281A JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3105533A Division JPH0810792B2 (en) | 1991-05-10 | 1991-05-10 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873193A JPS5873193A (en) | 1983-05-02 |
| JPH0227835B2 true JPH0227835B2 (en) | 1990-06-20 |
Family
ID=15922654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17141281A Granted JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873193A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010698A (en) * | 1983-06-29 | 1985-01-19 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
| JPS60170294A (en) * | 1984-02-14 | 1985-09-03 | 日本電気株式会社 | Method of producing multilayer circuit board with pin |
| JPS62119951A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Multilayer interconnection substrate |
| JPS63144598A (en) * | 1986-12-09 | 1988-06-16 | 日本電気株式会社 | Manufacture of multilayer circuit board |
| JPS63169797A (en) * | 1987-01-07 | 1988-07-13 | 日本電気株式会社 | Hybrid integrated circuit device |
| JP2588549B2 (en) * | 1987-11-20 | 1997-03-05 | 株式会社日立製作所 | Semiconductor device |
| JP3087899B2 (en) * | 1989-06-16 | 2000-09-11 | 株式会社日立製作所 | Method for manufacturing thick film thin film hybrid multilayer wiring board |
| JPH0821648B2 (en) * | 1989-06-20 | 1996-03-04 | 三菱マテリアル株式会社 | Pinless grid array electrode structure formed by thick film technology |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
-
1981
- 1981-10-28 JP JP17141281A patent/JPS5873193A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5873193A (en) | 1983-05-02 |
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