JPS5873193A - Method of producing multilayer circuit board - Google Patents
Method of producing multilayer circuit boardInfo
- Publication number
- JPS5873193A JPS5873193A JP17141281A JP17141281A JPS5873193A JP S5873193 A JPS5873193 A JP S5873193A JP 17141281 A JP17141281 A JP 17141281A JP 17141281 A JP17141281 A JP 17141281A JP S5873193 A JPS5873193 A JP S5873193A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- thick film
- insulating layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明ａ１多層配線に用いる配線基板の製造方法に係る
もので％ｒ１ｒｃ薄膜・厚膜混成方式の配線基板の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a wiring board used in a1 multilayer wiring, and relates to a method for manufacturing a wiring board using a thin film/thick film hybrid method.
電子計算機等に用いる大容量の混成集積回路用多層配線
基板として、一般に配線を厚膜印刷焼結方式で形成し、
基板および層間絶縁物としてアルミナセラミ９り全周い
た基板が用いられている。As a multilayer wiring board for large-capacity hybrid integrated circuits used in electronic computers, etc., wiring is generally formed using a thick film printing and sintering method.
A substrate covered with alumina ceramic 9 all around is used as the substrate and interlayer insulator.
ところが近年、電子計算機において高機能、高速化の要
精が強く、この結果大配線容量の混成集積回路用基板が
要求されるようになった。厚膜アルミナセラミヅク基板
では、配線密度が印刷工程の精度で限定され（Ｉｉ＆小
可能配線ビヴテ１５０μｍ）るため、配線層５〜１０層
、絶縁層５〜１０層の多層で基板寸法１００顛の基板が
出現している。However, in recent years, there has been a strong demand for high performance and high speed in electronic computers, and as a result, a substrate for hybrid integrated circuits with a large wiring capacity has become required. For thick-film alumina ceramic substrates, the wiring density is limited by the precision of the printing process (Ii & small possible wiring width 150 μm), so a board size of 100 pieces can be achieved with multiple layers of 5 to 10 wiring layers and 5 to 10 insulating layers. A board has appeared.
層数の増大は各層間の接続点数音大幅に増すため、基板
製造歩留の大幅低下ｔもたらすという欠点がある。また
基板の大型化は、信号伝送路の増大會き九すため高速化
が図れない。An increase in the number of layers greatly increases the number of connection points between each layer, which has the disadvantage of significantly reducing the board manufacturing yield. Furthermore, increasing the size of the board increases the number of signal transmission paths, making it difficult to achieve higher speeds.
そこで、配線形成を半導体工業のプロセスである薄膜ホ
トプロセスを用いることが試みられている。薄膜プロセ
スを用いて多層化し九基板では、電子計算機用混成集積
回路基板として必要なコネクタの着脱に耐える数百本の
電子をとシだすことは一般に困難である。この端子に関
しては基叛農面全壊に焼結タングステンニＮ１メ〜ギし
７ｔビン接続Ｓを配列し、この接続部に釧ろうあるいは
けんだろうでリードビン會接続している従来の厚膜多層
配線基板が適している。ところで高密度、高速化會要す
る（口）路領塚は論理信号回路である。電源回路グラン
ド層は、従来の厚−多層配縁の配線密度で十分余裕があ
る。したがって、−理信号層を薄膜基板部として形成し
、電源グランド層やリードビン端子部を厚膜基板部とし
て形成した薄膜−厚膜混成方式で高密度、高速基８ｉヲ
達成できる。Therefore, attempts have been made to use thin film photoprocessing, which is a process used in the semiconductor industry, to form interconnections. It is generally difficult to emit several hundred electrons that can withstand the connection and disconnection of connectors necessary for a hybrid integrated circuit board for an electronic computer in a multi-layered board using a thin film process. Regarding this terminal, conventional thick-film multilayer wiring is used, in which sintered tungsten N1 mesh 7t bin connections S are arranged on the base plate, and a lead bin connection S is made with a wire or wire. The board is suitable. By the way, the key to high density and high speed technology is logic signal circuits. The power supply circuit ground layer has sufficient margin with the wiring density of conventional thick multilayer wiring. Therefore, a high-density, high-speed substrate 8i can be achieved by a thin film-thick film hybrid system in which the physical signal layer is formed as a thin film substrate part and the power supply ground layer and lead bin terminal part are formed as a thick film substrate part.
薄膜−厚膜混成方式の多層配線基板の製造は、第１図に
示す工程でできる。焼結タングステンからなる電源・グ
ランド層２リードビン海子ｔｈ１３’に含む厚膜基板部
１０を通常の厚膜多層基板の製法であるグリンシート法
で形成する。厚膜基板部の配線と接続する厚膜配線端子
４をアルミナ絶縁層５のスルホールに穴うめして形成し
ておく。この厚膜基板部１０の上面に薄膜基板部の配Ｉ
Ｉｇｆｔｌとなる配線膜６を通常の薄膜プロセスである
抵抗力０熱＃着あるいはスパーツクにてＡ２あるいはＣ
ｒ／Ｃｕ／Ｃｒ で形成し、ネガ型しジス）ｋ用いるホ
トリゾエ９チングで配線膜６をパターン化する。このと
き配線端子４と配線パターン６を必ず重ね合せる。A thin film/thick film hybrid type multilayer wiring board can be manufactured by the steps shown in FIG. The thick film substrate portion 10 included in the power supply/ground layer 2 lead bin th13' made of sintered tungsten is formed by the green sheet method, which is a normal method for manufacturing thick film multilayer substrates. Thick film wiring terminals 4 to be connected to wiring on the thick film substrate portion are formed by filling through holes in the alumina insulating layer 5. A thin film substrate portion is arranged on the upper surface of this thick film substrate portion 10.
The wiring film 6 that will become Igftl is A2 or C using a normal thin film process such as zero-resistance heat bonding or spatter-coating.
The wiring film 6 is patterned by photolithography using a negative type resistor. At this time, the wiring terminal 4 and the wiring pattern 6 must be overlapped.
厚膜基板部１０は製造時の焼結収縮にばらつきがあり１
子４の位置ばらつきは基板中心からみてその位置の中心
からの距離のα６〜１．０Ｘとなる。The thick film substrate part 10 has variations in sintering shrinkage during manufacturing.
The positional variation of the child 4 is α6 to 1.0X of the distance from the center of the substrate when viewed from the center of the substrate.
このため、両基板部の接続全基板全域で図るために：は
、位置ばらつきの幅を厚膜配線端子４あるいは配線パタ
ーン６の接続部に与えなけれはならない。このため、配
線パターン６は高密度配線化が図ｎるホトリゾエツチン
グ工程を用いながら、厚膜配線基板部の配線密度と同じ
にしなければならない。この上に、通常の薄膜プ可セス
で形成する−８ ｉ ＯＲやポリイミド膜を絶縁層７と
し、そのスルホール８をホトリゾ上９テングで形成する
。こののち絶縁層７の上面に配線パターン６１を配線パ
ターン６と同様に形成し更に絶縁層７１、スルホール８
１に絶縁層７、スルホール８と同様に形成する。これら
の工程を繰返して薄勝基板＃１１ｔニー形成し、高密度
、′ＮＪ連用の多層配線基板となる。Therefore, in order to connect both substrate portions over the entire substrate area, it is necessary to provide the width of positional variation to the connection portion of the thick film wiring terminal 4 or the wiring pattern 6. For this reason, the wiring pattern 6 must be made to have the same wiring density as that of the thick-film wiring board portion, while using a photolithography process that allows for high-density wiring. On top of this, an insulating layer 7 is made of -8 i OR or a polyimide film formed by a normal thin film process, and its through holes 8 are formed using a photolithography process. After that, a wiring pattern 61 is formed on the upper surface of the insulating layer 7 in the same manner as the wiring pattern 6, and then the insulating layer 71 and the through holes 8 are formed.
1, an insulating layer 7 and a through hole 8 are formed in the same manner. These steps are repeated to form a thin-cut board #11t knee, resulting in a high-density multilayer wiring board for continuous use in NJ.
この多層配線基板では高密度化になんら寄与しない厚膜
薄膜混成の適合のための層がパターン６層および絶縁層
７と２層要しており、この次め工程が冗長され、歩測り
低下の原因だけとなっている。This multilayer wiring board requires two layers, a pattern 6 layer and an insulating layer 7, for adapting a thick film/thin film mixture that does not contribute to high density. It is only the cause.
ま友、第１図の配線端子４には、パターン６で僚われな
い個所が必す発生する。これはパターン６のパターン化
時の工・ソチンダ液が配線端子４に触れる友め、パター
ン６のエツチングへの悪影響や、ま定配線端子４１に酸
化させ、信頼性會落す原因となる。また厚膜基板部１０
の表面粗さは通常３〜４μｍある九め、ホトリゾエ・ｙ
チングのパターン６のパターン化が困難であり、表面粗
さ３〜４μｒｎ上のパターン６の配線抵抗の安定性が悪
いことかわかっている。Friend, in the wiring terminal 4 shown in FIG. 1, there will inevitably be parts that are not covered by the pattern 6. This causes the etching solution during patterning of the pattern 6 to come into contact with the wiring terminal 4, which adversely affects the etching of the pattern 6 and oxidizes the fixed wiring terminal 41, resulting in a decrease in reliability. In addition, the thick film substrate section 10
The surface roughness of photolithography is usually 3 to 4 μm.
It is known that it is difficult to pattern the pattern 6 of the chipping, and that the stability of the wiring resistance of the pattern 6 on a surface roughness of 3 to 4 μrn is poor.
本発明の目的は、以上の製造上の欠点を除き、薄膜・厚
膜混成方式の高密度、高速片の多層配線基板の製造方法
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high-density, high-speed multilayer wiring board using a thin-film/thick-film hybrid method, which eliminates the above manufacturing disadvantages.
本発明の特徴は、厚膜配線基板部の厚膜配線基板部と接
続すべき配線端子の大きさを、厚膜配線の位置ずれｉ’
に見込んで形成し、その上部に絶縁増？形成し、この絶
縁層にいわゆる薄膜プロセスであるホトリゾグラフィで
スルホール全形成し、以降、薄膜プロセス金用いて薄膜
多層配線基板部を形成して厚膜薄膜混成の多層配線基板
を製造するものである。A feature of the present invention is that the size of the wiring terminal to be connected to the thick film wiring board portion of the thick film wiring board portion is determined by adjusting the positional deviation i' of the thick film wiring.
Formed in anticipation of and increased insulation on top of it? All through holes are formed in this insulating layer using photolithography, which is a so-called thin film process, and then a thin film multilayer wiring board part is formed using thin film process gold to manufacture a thick film and thin film mixed multilayer wiring board. be.
以下第２図に示す実施例により、本発明ケ具体的に説明
する。同図（＆）社厚膜配線基板部ケ作る方法を説明す
る図、同図（ｂ）は厚膜配線基板部に厚膜配線基板部を
形成する方法全説明する図である。The present invention will be specifically explained below with reference to an embodiment shown in FIG. The same figure (&) is a diagram explaining the method of making the thick film wiring board part, and the same figure (b) is a diagram explaining the whole method of forming the thick film wiring board part on the thick film wiring board part.
図に示す１０は、タングステンの焼結体からなる電碑配
線層やグランド層２奮含む、グリンシート法で製造した
アルミナ厚膜多層配線基板部１０である。配＃端子４は
アルミナ絶縁層５のスルホールにタングステンベースド
音大うめ焼結して形成さｎている。配線端子４の径は、
接続する薄膜のスルホール径に（グリンシート法での焼
結収縮ばらつきＱ、６〜１．υＸＸ基板の長辺寸法Ｘ
１／２ ）ｒカロえた径とする。基板寸法全５０（至）
、薄膜スルホール径全５０μｍとすると、端子の径は２
５０μ山前後とする。基板部１０の裏面には焼結タング
ステンパッドに銀ろうで接続されたリードビン９かつい
ている。配線端子４はアルミナ絶縁層５の上面と同一平
面もしくは１０μω以下で突出するように形成されてい
る。この基板部１０４ｃポリイミド樹脂をスピンコーテ
ィング方式で塗布し、熱硬化して絶縁層７を形成する。The reference numeral 10 shown in the figure is an alumina thick film multilayer wiring board section 10 manufactured by the green sheet method, which includes an electric wiring layer and two ground layers made of a sintered body of tungsten. The wiring terminals 4 are formed by sintering a tungsten-based high-temperature filler into the through holes of the alumina insulating layer 5. The diameter of the wiring terminal 4 is
The through-hole diameter of the thin film to be connected (sintering shrinkage variation Q in the green sheet method, 6 to 1.υXX, the long side dimension of the substrate
1/2) The diameter is increased by r. Total board dimensions 50 (up to)
, if the total diameter of the thin film through holes is 50 μm, the diameter of the terminal is 2
The height should be around 50μ. A lead via 9 connected to a sintered tungsten pad with silver solder is attached to the back surface of the substrate section 10. The wiring terminal 4 is formed to be flush with the upper surface of the alumina insulating layer 5 or to protrude by 10 μω or less. This polyimide resin on the substrate portion 104c is applied by spin coating and thermally cured to form the insulating layer 7.
この絶縁層７にネガ型レジスト（例えは東京応化裂のＯ
ＭＩ’＋８５）ｉコーティングし、レジストを紫外線１
４光でパターン化し、湿式１・Ｖチングで配線端子４の
上部の絶縁層７にスルホール８を形成する。スルホール
８の形成にネガ型しジス）Ｉｔ！いるのは、厚膜基板部
１が硬く、そり、うねＶがあるため、もろいポジ型しジ
ヌトでは無光時にマスクとの接触でレジストが―〈離し
、絶縁層７にピンホールが発生するのを避けることにあ
る。そして１１ｗ端子４の上面ｔアルミナ絶縁層の上面
エフ沈めないのは、ネガ型しジメ）ｔ−用いるので、無
光時にマスクと間隙力ｉあくと紫外光のまわりごみでス
ルホールできなくなるのｔ避けるためである。スルホー
ル８形成後、抵抗加熱あるいはエレクトロンビーム蒸着
スバ・ツタなどでアルミあるい扛チタン＋銅十チタン膜
６會形成し通常のホトリゾ工程でパターン化する。この
配線６は絶縁層７の上でのパターン化のため表面粗さの
大きい厚膜多層配線基板部１０（表面粗さ４〜６μｌ）
上と異なり、２０〜４０μｍピッチでの配線化ができ、
厚膜基板ｓ１０の影響？受けない。そして配線パターン
６のパターン化の際にそのエツチング液が配線端子４に
触れることはない。以降、この上ｓＶＣポリイミド樹脂
層７１と配線層６１を繰返し形成し、薄膜多層配線基板
ｆｍ１１’を形成する。し九がって、厚膜・薄膜の適合
層は絶縁層７一層となる。これにより高密度配線の多層
配線基板が形成される。なお、リードビン９は、薄膜配
線基板部１１紮形成したあとに付けてもよい。This insulating layer 7 is coated with a negative resist (for example, Tokyo Okasen's O
MI'+85)i coating and UV 1
Patterning is performed using 4 lights, and through holes 8 are formed in the insulating layer 7 above the wiring terminals 4 using wet 1-V chiming. Negative die to form through hole 8) It! The reason for this is that the thick film substrate part 1 is hard and has warps and ridges, so it is a brittle positive type.In the case of GINUTO, the resist comes into contact with the mask when there is no light. The purpose is to avoid 11w The top surface of the terminal 4, the top surface of the alumina insulating layer, and the reason why it does not sink is because it is a negative type. If the gap between the mask and the mask is too large when there is no light, it will not be possible to form a through hole due to dust around the ultraviolet light. It's for a reason. After forming the through holes 8, six aluminum or titanium/copper/titanium films are formed by resistance heating or electron beam evaporation, and patterned by a normal photolithography process. This wiring 6 is patterned on the insulating layer 7, so the thick film multilayer wiring board part 10 has a large surface roughness (surface roughness 4 to 6 μl).
Unlike the above, wiring can be done at a pitch of 20 to 40 μm,
Influence of thick film substrate s10? I don't accept it. When patterning the wiring pattern 6, the etching solution does not come into contact with the wiring terminals 4. Thereafter, an sVC polyimide resin layer 71 and a wiring layer 61 are repeatedly formed on this, thereby forming a thin film multilayer wiring board fm11'. Therefore, the compatible layer for thick and thin films is the insulating layer 7. As a result, a multilayer wiring board with high-density wiring is formed. Note that the lead bin 9 may be attached after the thin film wiring board portion 11 is formed.
以上のように、本発明によれば、従来の厚膜多層配線基
板Ｌジ２〜３倍の高密度化が図れる．従って配線層数，
スルホール接続数が低減でき、製品歩留りが向上し、更
にコネクタ着脱に耐える多端子のとりたしが容易に図れ
る。As described above, according to the present invention, the density of the conventional thick film multilayer wiring board L can be increased two to three times. Therefore, the number of wiring layers,
The number of through-hole connections can be reduced, product yield is improved, and multiple terminals that can withstand connector attachment and detachment can be easily installed.
第１図は＃Ｍ混成多層基板の従来製造方法を説明する図
、第２図は本発明の実施例′ｋＩｉ５２明する図である
。
１０・・・厚膜多層配線基板部、１１・・・薄膜多層配
線基板部、４・・・厚膜基板部の配ｆｉｌ端子、５・・
・厚膜基板部の絶縁層，７．７１・・・薄膜基根部の絶
縁層、６、６１・・・ｗｌ．膜基板部の配線、９・・リ
ードビン。
代理人弁理士 薄 １）利 幸FIG. 1 is a diagram for explaining a conventional manufacturing method of a #M hybrid multilayer board, and FIG. 2 is a diagram for explaining an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Thick film multilayer wiring board part, 11... Thin film multilayer wiring board part, 4... Film distribution terminal of thick film board part, 5...
- Insulating layer of thick film substrate part, 7.71... Insulating layer of thin film base part, 6, 61... wl. Wiring of membrane substrate part, 9... Lead bin. Representative Patent Attorney Susuki 1) Yuki Toshi
Claims (1)
構成の多層配線基板の製造方法において、厚膜配線基板
部の薄膜配線基板部と接続すべき配線端子の大きさ會、
厚膜配線の位置ずれｉｎｋ見込んで厚−配線基板部の上
部面に形成し、その上部に絶縁層を形成し、この絶縁層
にホトリゾエツチング法によりスルーホールを形成し、
このスルーホール全弁して両基飯部間の配線接続を行な
うこと全特徴とする多層配線基板の製造方法。 ２ 上記配線端子ｒ１その上面が厚膜配線基板部の上部
面より少なくとも沈まないように形成した特許請求の範
囲第１項記載の多層配線基板の製造方法。[Claims] 1. In a method for manufacturing a multilayer wiring board having a hybrid configuration consisting of a thick film wiring board part and a thin film wiring board part, the size of the wiring terminal to be connected to the thin film wiring board part of the thick film wiring board part Meeting,
Anticipating misalignment of thick film wiring, ink is formed on the upper surface of the thick wiring board section, an insulating layer is formed on top of the ink, and through holes are formed in this insulating layer by photolithography.
A method for manufacturing a multilayer wiring board, characterized in that the through-holes are fully valved to connect wiring between both base portions. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the wiring terminal r1 is formed so that its upper surface does not sink below the upper surface of the thick film wiring board portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17141281A JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17141281A JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3105533A Division JPH0810792B2 (en) | 1991-05-10 | 1991-05-10 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873193A true JPS5873193A (en) | 1983-05-02 |
| JPH0227835B2 JPH0227835B2 (en) | 1990-06-20 |
Family
ID=15922654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17141281A Granted JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873193A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010698A (en) * | 1983-06-29 | 1985-01-19 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
| JPS60170294A (en) * | 1984-02-14 | 1985-09-03 | 日本電気株式会社 | Method of producing multilayer circuit board with pin |
| JPS62119951A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Multilayer interconnection substrate |
| JPS63144598A (en) * | 1986-12-09 | 1988-06-16 | 日本電気株式会社 | Manufacture of multilayer circuit board |
| JPS63169797A (en) * | 1987-01-07 | 1988-07-13 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPH01135056A (en) * | 1987-11-20 | 1989-05-26 | Hitachi Ltd | Semiconductor device |
| JPH0319395A (en) * | 1989-06-16 | 1991-01-28 | Hitachi Ltd | Pattern forming method and device for thick film thin film hybrid multilayer wiring board |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
-
1981
- 1981-10-28 JP JP17141281A patent/JPS5873193A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010698A (en) * | 1983-06-29 | 1985-01-19 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
| JPH0239878B2 (en) * | 1983-06-29 | 1990-09-07 | Nippon Electric Co | |
| JPS60170294A (en) * | 1984-02-14 | 1985-09-03 | 日本電気株式会社 | Method of producing multilayer circuit board with pin |
| JPH0254677B2 (en) * | 1984-02-14 | 1990-11-22 | Nippon Electric Co | |
| JPS62119951A (en) * | 1985-11-19 | 1987-06-01 | Nec Corp | Multilayer interconnection substrate |
| JPH053760B2 (en) * | 1985-11-19 | 1993-01-18 | Nippon Electric Co | |
| JPS63144598A (en) * | 1986-12-09 | 1988-06-16 | 日本電気株式会社 | Manufacture of multilayer circuit board |
| JPS63169797A (en) * | 1987-01-07 | 1988-07-13 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPH0551199B2 (en) * | 1987-01-07 | 1993-07-30 | Nippon Electric Co | |
| JPH01135056A (en) * | 1987-11-20 | 1989-05-26 | Hitachi Ltd | Semiconductor device |
| JPH0319395A (en) * | 1989-06-16 | 1991-01-28 | Hitachi Ltd | Pattern forming method and device for thick film thin film hybrid multilayer wiring board |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0227835B2 (en) | 1990-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4665468A (en) | Module having a ceramic multi-layer substrate and a multi-layer circuit thereupon, and process for manufacturing the same | |
| JP2966972B2 (en) | Semiconductor chip carrier, module mounting the same, and electronic device incorporating the same | |
| KR100271838B1 (en) | Planar redistribution structure and printed wiring device | |
| JP2996510B2 (en) | Electronic circuit board | |
| US5106461A (en) | High-density, multi-level interconnects, flex circuits, and tape for tab | |
| JP3359865B2 (en) | Electronic interconnect structure and method for manufacturing the same | |
| EP0425607A1 (en) | High-density, multi-level interconnects, flex circuits, and tape for tab | |
| JPH0226392B2 (en) | ||
| JP3953122B2 (en) | Circuit card and manufacturing method thereof | |
| JPH053159B2 (en) | ||
| US6384344B1 (en) | Circuit board for mounting electronic parts | |
| TW200411879A (en) | Substrate with stacked via and fine circuit thereon, and method for fabricating the same | |
| USRE44251E1 (en) | Circuit board for mounting electronic parts | |
| US20060243482A1 (en) | Circuit board structure and method for fabricating the same | |
| JPS5873193A (en) | Method of producing multilayer circuit board | |
| JP2000349437A (en) | Multilayered wiring board and its manufacture | |
| WO1991011025A1 (en) | A method for manufacturing of mineature impedance matched interconnection patterns | |
| JP2810143B2 (en) | Thick film thin film hybrid multilayer wiring board | |
| CN205864853U (en) | A kind of printed circuit board | |
| JPH04226097A (en) | Manufacture of multilayer wiring board | |
| JP3210740B2 (en) | Multilayer circuit board, electronic module and electronic device | |
| JP4637389B2 (en) | Manufacturing method of multilayer wiring board | |
| JP4693258B2 (en) | Manufacturing method of multilayer wiring board | |
| JPH0433396A (en) | Multilayer printed ceramic board with air layer | |
| JPS60148191A (en) | Method of producing thick film thin film hybrid multilayer circuit board |