JPH07235768A - Production process for thin film multilayer wiring board - Google Patents
Production process for thin film multilayer wiring boardInfo
- Publication number
- JPH07235768A JPH07235768A JP2796294A JP2796294A JPH07235768A JP H07235768 A JPH07235768 A JP H07235768A JP 2796294 A JP2796294 A JP 2796294A JP 2796294 A JP2796294 A JP 2796294A JP H07235768 A JPH07235768 A JP H07235768A
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- JP
- Japan
- Prior art keywords
- layer
- forming
- thin film
- pattern
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は薄膜多層配線基板の製
造方法に係り、さらに詳しくは、マルチチップモジュー
ルなどの構成に適する薄膜多層配線基板の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer wiring board, and more particularly to a method for manufacturing a thin film multilayer wiring board suitable for a structure such as a multichip module.
【０００２】[0002]
【従来の技術】近年、電子部品もしくは電子回路の小形
化，高密度化（大容量化）などが図られており、たとえ
ばパッケージ化した半導体装置を、いわゆるプリント基
板に搭載・実装することが広く知られている。しかし、
前記従来の実装手段では、その高密度化（大容量化）な
どに限界があるため、薄膜技術によって製造し得る薄膜
多層配線基板を、実装用の配線基板としたマルチチップ
モジュールなどの開発が進められている。2. Description of the Related Art In recent years, electronic parts or electronic circuits have been miniaturized and increased in density (increased capacity). For example, packaged semiconductor devices are widely mounted and mounted on so-called printed circuit boards. Are known. But,
Since the conventional mounting means has a limitation in increasing the density (capacity), development of a multi-chip module etc. using a thin film multilayer wiring board which can be manufactured by a thin film technology as a wiring board for mounting is advanced. Has been.
【０００３】また、この種の薄膜多層配線基板は、一般
的に、次のような工程を経て製造されている。図11〜図
17は従来の薄膜多層配線基板の製造工程における実施態
様を模式的に示したもので、先ず、少くとも表面に絶縁
層が設けられている絶縁性支持基板１を用意し、この絶
縁性支持基板１の所定領域面上に、たとえば化学Cuメッ
キによって薄い導電体層２を設ける。次に、前記形成し
た導電体層２面上に、感光性樹脂層３を設け、この感光
性樹脂層３に選択的な露光，現像処理を施して、図11に
要部を断面的に示すごとく、配線パターニングする。そ
の後、前記導電体層２をメッキ用電極として、その露出
面上に、たとえば電気Cuメッキ層および電気Niメッキ層
を、選択的に成膜させて、図11に要部を断面的に示すご
とく、第１の配線パターン４を形成する。Further, this type of thin film multilayer wiring board is generally manufactured through the following steps. Figure 11-Figure
Reference numeral 17 schematically shows an embodiment in the manufacturing process of a conventional thin film multilayer wiring board. First, an insulating support substrate 1 having an insulating layer provided on at least the surface thereof is prepared. A thin conductor layer 2 is provided on the surface of the predetermined region 1 by, for example, chemical Cu plating. Next, a photosensitive resin layer 3 is provided on the surface of the conductor layer 2 formed as described above, and the photosensitive resin layer 3 is selectively exposed and developed. Then, the wiring is patterned. Then, the conductor layer 2 is used as a plating electrode, and, for example, an electric Cu plating layer and an electric Ni plating layer are selectively formed on the exposed surface thereof, as shown in FIG. , The first wiring pattern 4 is formed.
【０００４】次いで、前記第１の配線パターン４を形成
した面全体に、再び感光性樹脂層３′を設け、この感光
性樹脂層３′に選択的な露光，現像処理を施して、図13
に要部を断面的に示すごとく、配線パターン層間を電気
的に接続領域としてビアホール（ビア開口部）５を形成
する。その後、前記第１の配線パターン４を形成した場
合と同様に、電気Cuメッキ層および電気Niメッキ層を、
前記ビア開口部５内に選択的に成膜させて、図14に要部
を断面的に示すように、フィルドビア（ビア接続部）６
を形成する。Next, a photosensitive resin layer 3'is again provided on the entire surface on which the first wiring pattern 4 has been formed, and the photosensitive resin layer 3'is subjected to selective exposure and development treatment, as shown in FIG.
A via hole (via opening) 5 is formed as an electrically connecting region between the wiring pattern layers, as shown in cross section in FIG. After that, as in the case where the first wiring pattern 4 is formed, an electric Cu plating layer and an electric Ni plating layer are formed,
A film is selectively formed in the via opening 5, and a filled via (via connecting portion) 6 is formed as shown in FIG.
To form.
【０００５】こうして、配線パターン層間を電気的に接
続するフィルドビア６を形成してから、前記パターニン
グマスクとして機能させた感光性樹脂層３，３′を除去
する一方、感光性樹脂層３，３′の除去で露出した導電
体層２をエッチング除去する。この工程によって、図15
に要部を断面的に示すように、第１の配線パターン４な
どが露出される。次いで、前記第１の配線パターン４な
どの露出面に、図16に要部を断面的に示すごとく、層間
絶縁体層として機能するたとえばポリイミド樹脂層（第
１の絶縁樹脂層）７を被着，形成する。そして、この状
態では、第１の絶縁樹脂層７によって、前記フィルドビ
ア接続６の配線パターン層間を電気的に接続する機能が
損なわれているため、前記第１の絶縁樹脂層７の突出部
7aに、たとえば機械的な研磨加工もしくはフォトリソ加
工を施して平坦化し、図17に要部を断面的に示すごと
く、フィルドビア接続６の端面を露出させる。In this way, after the filled vias 6 for electrically connecting the wiring pattern layers are formed, the photosensitive resin layers 3 and 3'functioning as the patterning mask are removed, while the photosensitive resin layers 3 and 3'are removed. The conductor layer 2 exposed by removing is removed by etching. By this step, FIG.
The first wiring pattern 4 and the like are exposed so that a main part is shown in cross section. Next, for example, a polyimide resin layer (first insulating resin layer) 7 functioning as an interlayer insulating layer is adhered to the exposed surface of the first wiring pattern 4 or the like, as shown in a sectional view of the main part in FIG. ,Form. In this state, the function of electrically connecting the wiring pattern layers of the filled via connection 6 is impaired by the first insulating resin layer 7, so that the protruding portion of the first insulating resin layer 7 is formed.
The surface 7a is subjected to, for example, mechanical polishing or photolithography to be flattened, and the end surface of the filled via connection 6 is exposed as shown in FIG.
【０００６】前記フィルドビア６の端面を露出させた第
１の絶縁樹脂層７面上に、前記の工程を繰り返し施すこ
とによって、所望の薄膜多層配線基板が得られる。By repeating the above steps on the surface of the first insulating resin layer 7 where the end surface of the filled via 6 is exposed, a desired thin film multilayer wiring board can be obtained.
【０００７】[0007]
【発明が解決しようとする課題】前記したように、従来
の薄膜多層配線基板の製造方法の場合は、層間絶縁樹脂
層７の形成に先立って、フィルドビア接続６を形成して
おき、層間絶縁樹脂層７を形成した後、層間絶縁樹脂層
７の一部を研磨加工して、フィルドビア６の端面を露出
させる必要がある。しかし、このような工程を採ること
は、実用上、次のような不都合な問題を提起する。すな
わち、多層配線部の構成において、メッキ配線パターン
層４およびフィルドビア接続６の膜厚さを大きくする一
方、配線パターン幅や配線ピッチを微細化して、高アス
ペクト比を得ようとした場合、前記層間絶縁層７を膜厚
に形成する必要がある。つまり、所要膜厚の層間絶縁層
７を形成するためには、必然的に粘度の高いポリイミド
樹脂などをコーティングすることになる。ところで、前
記粘度の高いポリイミド樹脂などをコーティングする
と、狭ピッチで高アスペクト比の配線パターンやフィル
ドビア接続６領域を、樹脂で緻密に充填することが困難
で、所要の絶縁性、ひいては最終的に構成したマルチチ
ップモジュールの特性を十分に確保し得ないという問題
がある。As described above, in the case of the conventional method of manufacturing a thin film multilayer wiring board, the filled via connection 6 is formed prior to the formation of the interlayer insulating resin layer 7, and the interlayer insulating resin is formed. After forming the layer 7, it is necessary to polish part of the interlayer insulating resin layer 7 to expose the end face of the filled via 6. However, taking such a step poses the following inconvenient problems in practical use. That is, in the structure of the multilayer wiring part, when the thickness of the plated wiring pattern layer 4 and the filled via connection 6 is increased while the wiring pattern width and the wiring pitch are miniaturized, a high aspect ratio is obtained. It is necessary to form the insulating layer 7 to a film thickness. That is, in order to form the interlayer insulating layer 7 having a required film thickness, it is inevitable that a high-viscosity polyimide resin or the like is coated. By the way, when the high-viscosity polyimide resin or the like is coated, it is difficult to densely fill the wiring pattern having a narrow pitch and a high aspect ratio and the filled via connection 6 region with the resin, and the required insulating property, and eventually the final configuration, are formed. There is a problem that the characteristics of the multi-chip module cannot be sufficiently secured.
【０００８】本発明は上記事情に対処してなされたもの
で、配線パターンの膜厚化や狭ピッチ化、高アスペクト
比化など容易に達成でき、信頼性の高いマルチチップモ
ジュールなどの構成に適する薄膜多層配線基板の製造方
法の提供を目的とする。The present invention has been made in consideration of the above circumstances and is suitable for a highly reliable multi-chip module or the like that can easily achieve a wiring pattern having a thin film thickness, a narrow pitch, and a high aspect ratio. An object of the present invention is to provide a method for manufacturing a thin film multilayer wiring board.
【０００９】[0009]
【課題を解決するための手段】本発明に係る薄膜多層配
線基板の製造方法は、ベース基板主面に層間絶縁層を成
す第１の薄膜絶縁樹脂パターンを形成する工程と、前記
第１の薄膜絶縁樹脂パターン形成面に導体膜を設け、こ
の導体膜を一方の電極とし、薄膜絶縁樹脂パターン上面
と略同一平面を成すように電気メッキで導体を肉盛りし
て第１の薄膜配線パターン層を形成する工程と、前記第
１の薄膜配線パターン層を形成した面に、所要のビアホ
ールを備えた層間絶縁層を成す第２の薄膜絶縁樹脂パタ
ーンを形成配置する工程と、前記第２薄膜絶縁樹脂パタ
ーン形成面に導体膜を設け、この導体膜を一方の電極と
し、ビアホール部を電気メッキによって導体を肉盛りし
て薄膜絶縁樹脂パターン上面と略同一平面を成すフィル
ドビア接続を形成する工程とを具備して成ることを特徴
とする。さらに要すれば、ベース基板主面に低誘電率の
耐熱性樹脂層を設け、この耐熱性樹脂層をパターニング
し、層間絶縁層を成す第１の薄膜絶縁樹脂パターンを形
成する工程と、前記第１の薄膜絶縁樹脂パターン形成面
に導体膜を設け、この導体膜を一方の電極とし、薄膜絶
縁樹脂パターン上面と略同一平面を成すように電気メッ
キで導体を肉盛りして第１の薄膜配線パターン層を形成
する工程と、前記第１の薄膜配線パターン層を形成した
面に、低誘電率の耐熱性樹脂層を設け、この耐熱性樹脂
層をパターニングして、所要のビアホールを備えた層間
絶縁層を成す第２の薄膜絶縁樹脂パターンを形成配置す
る工程と、前記第２薄膜絶縁樹脂パターン形成面に導体
膜を設け、この導体膜を一方の電極とし、ビアホール部
を電気メッキによって導体を肉盛りして薄膜絶縁樹脂パ
ターン上面と略同一平面を成すフィルドビア接続を形成
する工程とを具備して成ることを特徴とする。A method of manufacturing a thin film multilayer wiring board according to the present invention comprises a step of forming a first thin film insulating resin pattern forming an interlayer insulating layer on a main surface of a base substrate, and the first thin film. A conductor film is provided on the surface on which the insulating resin pattern is formed, and the conductor film is used as one electrode, and the conductor is electroplated to form a first thin film wiring pattern layer so as to be substantially flush with the upper surface of the thin film insulating resin pattern. A step of forming, a step of forming and arranging a second thin film insulating resin pattern forming an interlayer insulating layer having a required via hole on the surface on which the first thin film wiring pattern layer is formed, and the second thin film insulating resin A conductor film is provided on the pattern formation surface, and this conductor film is used as one electrode, and the via hole portion is electroplated to form a filled via connection that is substantially flush with the upper surface of the thin-film insulating resin pattern. Characterized in that formed by and a that step. Further, if necessary, a step of forming a low dielectric constant heat resistant resin layer on the main surface of the base substrate and patterning the heat resistant resin layer to form a first thin film insulating resin pattern forming an interlayer insulating layer; A conductor film is provided on the thin-film insulating resin pattern forming surface of No. 1, and the conductor film is used as one electrode, and the conductor is padded by electroplating so as to be substantially flush with the upper surface of the thin-film insulating resin pattern. A step of forming a pattern layer, a heat-resistant resin layer having a low dielectric constant is provided on the surface on which the first thin film wiring pattern layer is formed, and the heat-resistant resin layer is patterned to form an interlayer having a required via hole. A step of forming and arranging a second thin film insulating resin pattern forming an insulating layer; a conductor film is provided on the second thin film insulating resin pattern forming surface, and the conductor film is used as one electrode, and the via hole is electroplated. Padding to be characterized by formed by a step of forming a filled via connection forming the thin film insulating resin pattern top and substantially the same plane.
【００１０】本発明において、ベース基板としては、た
とえばSi板，Al2 O 3 板，AlN 板，SiN 板，SiC 板など
が挙げられる。また配線層間の絶縁層を成す樹脂層は、
たとえばポリイミド樹脂，感光性ポリイミド樹脂，ポリ
イミドエーテル樹脂，ビスベンゾシクロブテン系樹脂，
ポリフェニルキノキサリン樹脂，フロロカーボン系樹
脂，ポリベンゾキサゾール系樹脂など、低誘電率で耐熱
性を有するものが挙げられる。In the present invention, examples of the base substrate include Si plate, Al 2 O 3 plate, AlN plate, SiN plate and SiC plate. The resin layer that forms the insulating layer between the wiring layers is
For example, polyimide resin, photosensitive polyimide resin, polyimide ether resin, bisbenzocyclobutene resin,
Examples thereof include those having a low dielectric constant and heat resistance, such as polyphenylquinoxaline resin, fluorocarbon resin, and polybenzoxazole resin.
【００１１】一方、導体膜，薄膜配線パターン層，フィ
ルドビア接続などの形成は、一般的に、化学メッキおよ
び電気メッキの組み合わせが、作業性や高精度の確保な
どの点から望まれる。ここで、導体膜の形成は化学Cuメ
ッキや化学Niメッキ、あるいはCu，Niなどのスパッタリ
ングや蒸着でどて行われる。また，薄膜配線パターン層
は、前記導体膜を一方の電極とし、さらに要すればたと
えばTiやCrを下地層として介在させて、電気メッキによ
ってCu層，Au層などを設け、要すれば、Niなどのバリヤ
層もしくはTi層やCr層などの接着性層を設けることによ
って形成されるが、コスト面や加工性などを考慮する
と、電気Cuメッキ層が好ましい。On the other hand, in order to form the conductor film, the thin film wiring pattern layer, the filled via connection, etc., a combination of chemical plating and electroplating is generally desired in terms of workability and high accuracy. Here, the conductor film is formed by chemical Cu plating, chemical Ni plating, or sputtering or vapor deposition of Cu, Ni, or the like. In the thin film wiring pattern layer, the conductor film is used as one electrode, and if necessary, for example, Ti or Cr is interposed as a base layer, and a Cu layer, an Au layer, or the like is provided by electroplating. It is formed by providing a barrier layer such as or an adhesive layer such as a Ti layer or a Cr layer, but an electric Cu plating layer is preferable in consideration of cost and processability.
【００１２】[0012]
【作用】本発明によれば、多層配線部を構成する配線パ
ターン、配線パターン層間の層間絶縁層、および配線パ
ターン層間を電気的に接続するフィルドビア（ビア接続
部）を備えた多層配線印刷基板の製造において、配線パ
ターンおよびフィルドビアの存否に拘らず、層間絶縁層
の平坦面が確保されるため、配線回路の高性能化が容易
に図られる。つまり、配線回路の信号伝幡特性などの向
上を確保するため、配線パターンの厚膜化，高アスペク
ト比化，狭配線ピッチ化などを容易に達成し得る。According to the present invention, there is provided a multilayer wiring printed circuit board having a wiring pattern forming a multilayer wiring portion, an interlayer insulating layer between wiring pattern layers, and a filled via (via connecting portion) electrically connecting the wiring pattern layers. In manufacturing, the flat surface of the interlayer insulating layer is ensured regardless of the presence or absence of the wiring pattern and the filled via, so that the performance of the wiring circuit can be easily improved. That is, in order to ensure the improvement of the signal transfer characteristics of the wiring circuit, it is possible to easily achieve a thicker wiring pattern, a higher aspect ratio, and a narrower wiring pitch.
【００１３】[0013]
【実施例】以下、図１〜図10を参照して本発明の一実施
例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
【００１４】図１〜図10は、本発明に係る薄膜多層配線
基板の製造方法の実施態様例を模式的に示したもので、
先ず、第１図に断面的に示すごとく、絶縁性支持基板
（ベース基板）８、たとえばAl2 O 3 系板面上に、所要
の配線パターン化した第１の樹脂絶縁体層としてポリイ
ミド樹脂層9aを形成，配置する。なお、前記配線パター
ン化した第１の樹脂絶縁体層9aは、たとえば感光性ポリ
イミド樹脂層を設け、これに選択的な露光，および現像
処理を施すことによって形成される。次いで、前記ベー
ス基板８の第１の樹脂絶縁体層9a形成面に、スパッター
リング，蒸着，もしくは化学メッキによって、たとえば
Ni，Cuなどから成る導体層 10aを形成する。つまり図２
に断面的に示すように、電気メッキの電極として機能す
る導体層 10aを全面的に形成する。1 to 10 are schematic views showing an embodiment of the method for manufacturing a thin film multilayer wiring board according to the present invention.
First, as shown in a sectional view in FIG. 1, a polyimide resin layer is formed on a surface of an insulating support substrate (base substrate) 8, for example, an Al 2 O 3 system plate as a first resin insulator layer having a required wiring pattern. Form and place 9a. The wiring-patterned first resin insulator layer 9a is formed, for example, by providing a photosensitive polyimide resin layer and subjecting it to selective exposure and development. Then, on the surface of the base substrate 8 on which the first resin insulator layer 9a is formed, by sputtering, vapor deposition, or chemical plating, for example,
A conductor layer 10a made of Ni, Cu, etc. is formed. That is, FIG.
As shown in a sectional view in FIG. 3, a conductor layer 10a that functions as an electrode for electroplating is formed over the entire surface.
【００１５】次に、図３に断面的に示すごとく、前記導
体層 10aを形成した面に、配線パターン形成領域を露出
させる形のパターニングを行う。すなわち、導体層 10a
を形成した面に、感光性樹脂層を塗布，被着し、選択的
な露光，現像処理を施して、前記第１の樹脂絶縁体層9a
面に、メッキレジストパターン 11aを設ける。その後、
前記導体層 10aをメッキ電極として、たとえば電気Cuメ
ッキおよび電気Niメッキを行って、図４に断面的に示す
ように、配線パターン形成領域を、前記第１の樹脂絶縁
体層9a面と略同一平面をなす程度に導電体を肉盛りし、
第１の配線パターン層 12aを形成する。Next, as shown in a sectional view in FIG. 3, patterning is performed on the surface on which the conductor layer 10a is formed so that the wiring pattern forming region is exposed. That is, the conductor layer 10a
A photosensitive resin layer is applied to and adhered to the surface on which the first resin insulating layer 9a has been formed.
A plating resist pattern 11a is provided on the surface. afterwards,
Using the conductor layer 10a as a plating electrode, for example, electroplating with Cu and electroplating with Ni are performed, and as shown in a sectional view in FIG. 4, the wiring pattern forming region is substantially the same as the surface of the first resin insulation layer 9a. Build up a conductor to a flat surface,
The first wiring pattern layer 12a is formed.
【００１６】次いで、図５に断面的に示すように、第１
の配線パターン層 12aを形成した面のメッキレジストパ
ターン 11aを除去してから、第１の配線パターン層 12a
をマスクとして、前記第１の樹脂絶縁体層9a面上の不要
な導体層 10aエッチング除去する。こうして、第１の樹
脂絶縁体層9a面とほぼ同一平面を成す第１の配線パター
ン層 12aを設けた後、図６に断面的に示すごとく、ビア
接続部（フィルドビア接続）を形成する開口9b′を備え
た第２の樹脂絶縁体層9bとして、ポリイミド樹脂層を形
成，配置する。なお、前記パターン化した第２の樹脂絶
縁体層9bは、たとえば感光性ポリイミド樹脂層を設け、
これに選択的な露光，および現像処理を施すことによっ
て形成される。Then, as shown in a sectional view in FIG.
Of the first wiring pattern layer 12a after removing the plating resist pattern 11a on the surface on which the wiring pattern layer 12a of
Using the as a mask, the unnecessary conductor layer 10a on the surface of the first resin insulator layer 9a is removed by etching. In this way, after the first wiring pattern layer 12a that is substantially flush with the surface of the first resin insulator layer 9a is provided, the opening 9b for forming a via connection portion (filled via connection) is formed, as shown in a sectional view in FIG. A polyimide resin layer is formed and arranged as the second resin insulator layer 9b provided with '. The patterned second resin insulation layer 9b is provided with, for example, a photosensitive polyimide resin layer,
It is formed by subjecting it to selective exposure and development.
【００１７】その後、前記第２の樹脂絶縁体層9b形成面
に、スパッターリング，蒸着，もしくは化学メッキによ
って、たとえばNi，Cuなどから成る導体層 10bを形成す
る。つまり図７に断面的に示すように、電気メッキの電
極として作用させる導体層 10bを全面的に形成する。次
に、図８に断面的に示すごとく、前記導体層 10bを形成
した面に、ビア接続を形成する領域を露出させる形のパ
ターニングを行う。すなわち、導体層 10bを形成した面
に、感光性樹脂層を塗布，被着し、選択的な露光，現像
処理を施して、前記第２の樹脂絶縁体層9b面に、メッキ
レジストパターン 11bを設ける。Then, a conductor layer 10b made of, for example, Ni, Cu or the like is formed on the surface on which the second resin insulation layer 9b is formed by sputtering, vapor deposition, or chemical plating. That is, as shown in a sectional view in FIG. 7, a conductor layer 10b which acts as an electrode for electroplating is entirely formed. Next, as shown in a sectional view in FIG. 8, patterning is performed on the surface on which the conductor layer 10b is formed so as to expose a region for forming a via connection. That is, a photosensitive resin layer is applied and deposited on the surface on which the conductor layer 10b is formed, and a selective exposure and development process is performed to form a plating resist pattern 11b on the surface of the second resin insulation layer 9b. Set up.
【００１８】前記メッキレジストパターン 11b形成後、
導体層 10bをメッキ電極として、たとえば電気Cuメッキ
および電気Niメッキを行って、図９に断面的に示すよう
に、ビア接続形成領域を、前記第２の樹脂絶縁体層9b面
と略同一平面をなす程度に導電体を肉盛りし、所要のビ
ア接続部（フィルドビア接続）13を形成する。このよう
に、所要のビア接続部13を形成してから、メッキレジス
トパターン 11bを除去し、さらにビア接続部13をマスク
として、前記第２の樹脂絶縁体層9b面上の不要な導体層
10bエッチング除去する。この工程によって、図10に断
面的に示すように、第２の樹脂絶縁体層9b面とほぼ同一
平面を成してビア接続部13端面が露出する構成が形成さ
れるので、この段階で、第２の樹脂絶縁体層9bに対し
て、たとえば研削加工など施さずに、次層の配線パター
ン形成，配線パターン層間を絶縁する層間絶縁樹脂層の
形成を繰り返し進めることが可能となる。つまり、層間
絶縁樹脂層に対する研削加工など不要となるので、その
分工程の簡略化を図りながら、信頼性の点でもすぐれた
多層薄膜配線基板を、容易にかつ歩留まりよく製造し得
ることになる。After forming the plating resist pattern 11b,
Using the conductor layer 10b as a plating electrode, for example, electroplating with Cu and electroplating with Ni are performed, and as shown in a cross-sectional view in FIG. 9, the via connection formation region is substantially flush with the surface of the second resin insulation layer 9b. The conductor is piled up to such an extent that the desired via connection portion (filled via connection) 13 is formed. As described above, after forming the required via connection portion 13, the plating resist pattern 11b is removed, and the via connection portion 13 is used as a mask to remove unnecessary conductor layers on the surface of the second resin insulator layer 9b.
10b Etch away. As a result of this step, as shown in a sectional view in FIG. 10, a configuration is formed in which the end face of the via connection portion 13 is exposed so as to be substantially flush with the second resin insulation layer 9b surface, so at this stage, It is possible to repeat the formation of the wiring pattern of the next layer and the formation of the interlayer insulating resin layer that insulates the wiring pattern layers from each other without performing, for example, grinding on the second resin insulator layer 9b. That is, since it is not necessary to grind the interlayer insulating resin layer, a multilayer thin film wiring board excellent in reliability can be easily manufactured with a high yield while simplifying the process accordingly.
【００１９】なお、前記層間絶縁樹脂層を研削加工など
せずに平坦面を容易に確保し得ることは、微細な配線パ
ターンの形成を可能とする一方、層間絶縁体層の膜厚の
一様性（一定膜厚）による高周波特性など電気的特性の
向上，改善を意味する。また、所要の配線パターンおよ
びフィルドビア接続を、層間絶縁体層に形設された開口
部を埋め込み，形成する形態を採ったことに伴って、配
線パターンの膜厚化，高アスペクト比化および微細ピッ
チ化も可能となる。つまり、高速 LSIの性能に十分対応
できる高密度で、高機能なマルチチップモジュール用の
多層印刷配線基板を提供し得ることになる。The fact that the flat surface can be easily ensured without grinding the interlayer insulating resin layer enables formation of a fine wiring pattern, while the thickness of the interlayer insulating layer is uniform. It means improvement and improvement of electrical characteristics such as high frequency characteristics due to the property (constant film thickness). In addition, since the required wiring pattern and the filled via connection are formed by embedding the opening formed in the interlayer insulating layer, the wiring pattern becomes thicker, the aspect ratio becomes higher, and the fine pitch becomes smaller. It becomes possible. In other words, it is possible to provide a high-density, high-performance multilayer printed wiring board for a multi-chip module that can sufficiently support the performance of a high-speed LSI.
【００２０】さらに、前記配線パターンおよびフィルド
ビア接続の形成に当たって、Niメッキ膜で被覆した形を
採った場合は、これらの導体部と層間絶縁樹脂層との間
にバリア層を介在させた構成となるため、たとえばCuと
ポリイミド樹脂との作用によるマイグレーションなどが
回避されるので、高信頼性化が図られる。Further, when the wiring pattern and the filled via connection are formed by covering with a Ni plating film, a barrier layer is interposed between these conductors and the interlayer insulating resin layer. Therefore, for example, migration and the like due to the action of Cu and the polyimide resin are avoided, and thus high reliability is achieved.
【００２１】本発明は、前記実施例に限定されるもので
なく、発明の趣旨を逸脱しない範囲、換言すると、層間
絶縁樹脂層をマスクとして利用し、この層間絶縁樹脂層
の開口した領域を電気メッキなどにより肉盛りして、層
間絶縁樹脂層の膜厚に対応させて、所要の配線パターン
およびフィルドビア接続を形成することを骨子とする限
り、たとえばベース基板や層間絶縁樹脂層を、前記例示
以外の他の材質を選択することもできる。The present invention is not limited to the above-described embodiment, but is not limited to the scope of the present invention. In other words, the interlayer insulating resin layer is used as a mask, and the open region of the interlayer insulating resin layer is electrically connected. As long as the essence is to build up the required wiring pattern and filled via connection in accordance with the film thickness of the interlayer insulating resin layer by plating or the like, for example, a base substrate or an interlayer insulating resin layer other than the above examples Other materials can also be selected.
【００２２】[0022]
【発明の効果】以上説明したように、本発明に係る薄膜
多層配線基板の製造方法によれば、微細な配線化，配線
の膜厚化，高アスペクト比化など容易に、また高周波特
性なども良好で、たとえば高速 LSIの性能に充分対応し
得る信頼性の高い薄膜多層配線基板を得ることが可能と
なる。つまり、製造工程の煩雑化など招来することな
く、むしろ従来の製造手段に較べて、メカニカル加工な
どを不要とするなど、工程の簡略化を図りながら、マル
チチップモジュール用などに適する電気的な特性を有す
る薄膜多層配線基板を得ることができる。As described above, according to the method of manufacturing a thin-film multilayer wiring board of the present invention, it is possible to easily make fine wiring, increase the film thickness of the wiring, increase the aspect ratio, and obtain high frequency characteristics. It is possible to obtain a thin film multilayer wiring board that is good and has high reliability that can sufficiently cope with, for example, the performance of a high-speed LSI. In other words, without complicating the manufacturing process, rather than mechanical processing compared to conventional manufacturing means, while simplifying the process, electrical characteristics suitable for multi-chip module etc. It is possible to obtain a thin film multilayer wiring board having
【図１】本発明に係る製造方法の実施態様例を模式的に
示すもので、ベース基板面に第１の層間絶縁樹脂パター
ンを形成した状態を示す断面図。FIG. 1 is a cross-sectional view schematically showing an embodiment of a manufacturing method according to the present invention, showing a state in which a first interlayer insulating resin pattern is formed on a base substrate surface.
【図２】本発明に係る製造方法の実施態様例を模式的に
示すもので、第１の層間絶縁樹脂パターン形成面に導体
膜を形成した状態を示す断面図。FIG. 2 is a cross-sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which a conductor film is formed on the first interlayer insulating resin pattern forming surface.
【図３】本発明に係る製造方法の実施態様例を模式的に
示すもので、第１の層間絶縁樹脂パターン面にメッキレ
ジストパターンを形成した状態を示す断面図。FIG. 3 is a sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which a plating resist pattern is formed on the first interlayer insulating resin pattern surface.
【図４】本発明に係る製造方法の実施態様例を模式的に
示すもので、電気メッキして第１の層間絶縁樹脂パター
ンの開口部を導電体で埋め第１の配線パターンを形成し
た状態を示す断面図。FIG. 4 schematically shows an example of an embodiment of the manufacturing method according to the present invention, in which the first wiring pattern is formed by electroplating to fill the openings of the first interlayer insulating resin pattern with a conductor. FIG.
【図５】本発明に係る製造方法の実施態様例を模式的に
示すもので、第１の配線パターンを形成後、メッキレジ
ストパターンおよび不要な導体膜を除去した状態を示す
断面図。FIG. 5 is a cross-sectional view schematically showing an embodiment of a manufacturing method according to the present invention, showing a state in which a plating resist pattern and an unnecessary conductor film are removed after the first wiring pattern is formed.
【図６】本発明に係る製造方法の実施態様例を模式的に
示すもので、第１の配線パターン形成面に第２の層間絶
縁樹脂パターンを形成した状態を示す断面図。FIG. 6 is a sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which a second interlayer insulating resin pattern is formed on the first wiring pattern forming surface.
【図７】本発明に係る製造方法の実施態様例を模式的に
示すもので、第２の層間絶縁樹脂パターン形成面に導体
膜を形成した状態を示す断面図。FIG. 7 is a cross-sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which a conductor film is formed on the second interlayer insulating resin pattern forming surface.
【図８】本発明に係る製造方法の実施態様例を模式的に
示すもので、第２の層間絶縁樹脂パターン面にメッキレ
ジストパターンを形成した状態を示す断面図。FIG. 8 is a cross-sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which a plating resist pattern is formed on the second interlayer insulating resin pattern surface.
【図９】本発明に係る製造方法の実施態様例を模式的に
示すもので、電気メッキして第２の層間絶縁樹脂パター
ン形の開口部を導電体で埋めフィルドビア接続を形成し
た状態を示す断面図。FIG. 9 is a schematic view showing an example of an embodiment of the manufacturing method according to the present invention, showing a state in which a second via hole for the second interlayer insulating resin pattern is filled with a conductor to form a filled via connection by electroplating. Sectional view.
【図１０】本発明に係る製造方法の実施態様例を模式的
に示すもので、フィルドビア接続形成後、メッキレジス
トパターンおよび不要な導体膜を除去した状態を示す断
面図。FIG. 10 is a cross-sectional view schematically showing an embodiment of the manufacturing method according to the present invention, showing a state in which the plating resist pattern and the unnecessary conductor film are removed after the filled via connection is formed.
【図１１】従来の製造方法の実施態様を模式的に示すも
ので、ベース基板の導体膜形成面上に第１のメッキレジ
ストパターンを形成した状態を示す断面図。FIG. 11 is a cross-sectional view schematically showing an embodiment of a conventional manufacturing method, showing a state in which a first plating resist pattern is formed on a conductor film formation surface of a base substrate.
【図１２】従来の製造方法の実施態様を模式的に示すも
ので、電気メッキして第１のメッキレジストパターンの
開口部を導電体で埋め第１の配線パターンを形成した状
態を示す断面図。FIG. 12 is a cross-sectional view schematically showing an embodiment of a conventional manufacturing method, showing a state in which an opening of a first plating resist pattern is filled with a conductor to form a first wiring pattern by electroplating. .
【図１３】従来の製造方法の実施態様を模式的に示すも
ので、第１の配線パターンを形成面に第２のメッキレジ
ストパターンを形成した状態を示す断面図。FIG. 13 is a sectional view schematically showing an embodiment of a conventional manufacturing method, showing a state in which a second plating resist pattern is formed on the surface on which the first wiring pattern is formed.
【図１４】従来の実施態様を模式的に示すもので、電気
メッキして第２のメッキレジストパターンの開口部を導
電体で埋めフィルドビア接続を形成した状態を示す断面
図。FIG. 14 is a cross-sectional view schematically showing a conventional embodiment, showing a state where electroplating is performed to fill the opening of the second plating resist pattern with a conductor to form a filled via connection.
【図１５】従来の実施態様を模式的に示すもので、第
１，第２のメッキレジストパターン、および不要な導体
膜を除去した状態を示す断面図。FIG. 15 is a cross-sectional view schematically showing a conventional embodiment, showing a state in which first and second plating resist patterns and an unnecessary conductor film are removed.
【図１６】従来の実施態様を模式的に示すもので、第１
の配線パターンおよびフィルドビア接続を形成した面に
第１の層間絶縁樹脂層を形成した状態を示す断面図。FIG. 16 is a schematic view showing a conventional embodiment.
3 is a cross-sectional view showing a state in which a first interlayer insulating resin layer is formed on the surface on which the wiring pattern and the filled via connection are formed.
【図１７】従来の実施態様を模式的に示すもので、第１
の層間絶縁樹脂層を平坦面化に加工した状態を示す断面
図。FIG. 17 is a schematic view showing a conventional embodiment.
Sectional drawing which shows the state which processed the interlayer insulation resin layer of FIG.
１，８…絶縁性支持基板 ２， 10a， 10b…導体膜
（層） ３，３′…感光性樹脂層（配線パターニング
用マスク） ４， 12a…第１の配線パターン ５，9b′…ビアホール（開口部） ６，13…フィール
ドビア接続（ビア接続部） ７，9a…第１の層間絶縁
樹脂層（配線パターンマスク） 7a…突出部 9b……第１の層間絶縁樹脂層（配線パターンマスク）
11a…メッキレジストパターン1, 8 ... Insulating support substrate 2, 10a, 10b ... Conductor film (layer) 3, 3 '... Photosensitive resin layer (wiring patterning mask) 4, 12a ... First wiring pattern 5, 9b' ... Via hole ( Opening) 6,13 ... Field via connection (via connection) 7, 9a ... First interlayer insulating resin layer (wiring pattern mask) 7a ... Projection 9b ... First interlayer insulating resin layer (wiring pattern mask)
11a ... Plating resist pattern
Claims (2)
の薄膜絶縁樹脂パターンを形成する工程と、 前記第１の薄膜絶縁樹脂パターン形成面に導体膜を設
け、この導体膜を一方の電極とし、薄膜絶縁樹脂パター
ン上面と略同一平面を成すように電気メッキで導体を肉
盛りして第１の薄膜配線パターン層を形成する工程と、 前記第１の薄膜配線パターン層を形成した面に、所要の
ビアホールを備えた層間絶縁層を成す第２の薄膜絶縁樹
脂パターンを形成配置する工程と、 前記第２薄膜絶縁樹脂パターン形成面に導体膜を設け、
この導体膜を一方の電極とし、ビアホール部を電気メッ
キによって導体を肉盛りして薄膜絶縁樹脂パターン上面
と略同一平面を成すフィルドビア接続を形成する工程と
を具備して成ることを特徴とする薄膜多層配線基板の製
造方法。1. A first interlayer insulating layer is formed on a main surface of a base substrate.
And the step of forming a thin film insulating resin pattern, and a conductive film is provided on the first thin film insulating resin pattern forming surface, and this conductive film is used as one electrode, and is formed so as to be substantially flush with the upper surface of the thin film insulating resin pattern. A step of forming a first thin film wiring pattern layer by overlaying a conductor by plating, and a second thin film forming an interlayer insulating layer having a required via hole on the surface on which the first thin film wiring pattern layer is formed. Forming and arranging an insulating resin pattern, and providing a conductor film on the second thin film insulating resin pattern forming surface,
This conductive film is used as one electrode, and a step of forming a filled via connection is formed by electroplating the via hole portion by electroplating to form a filled via connection substantially flush with the upper surface of the thin film insulating resin pattern. Manufacturing method of multilayer wiring board.
層を設け、この耐熱性樹脂層をパターニングし、層間絶
縁層を成す第１の薄膜絶縁樹脂パターンを形成する工程
と、 前記第１の薄膜絶縁樹脂パターン形成面に導体膜を設
け、この導体膜を一方の電極とし、薄膜絶縁樹脂パター
ン上面と略同一平面を成すように電気メッキで導体を肉
盛りして第１の薄膜配線パターン層を形成する工程と、 前記第１の薄膜配線パターン層を形成した面に、低誘電
率の耐熱性樹脂層を設け、この耐熱性樹脂層をパターニ
ングして、所要のビアホールを備えた層間絶縁層を成す
第２の薄膜絶縁樹脂パターンを形成配置する工程と、 前記第２薄膜絶縁樹脂パターン形成面に導体膜を設け、
この導体膜を一方の電極とし、ビアホール部を電気メッ
キによって導体を肉盛りして薄膜絶縁樹脂パターン上面
と略同一平面を成すフィルドビア接続を形成する工程と
を具備して成ることを特徴とする薄膜多層配線基板の製
造方法。2. A step of providing a heat resistant resin layer having a low dielectric constant on a main surface of a base substrate, patterning the heat resistant resin layer to form a first thin film insulating resin pattern forming an interlayer insulating layer, A conductor film is provided on the thin-film insulating resin pattern forming surface of No. 1, and the conductor film is used as one electrode, and the conductor is padded by electroplating so as to be substantially flush with the upper surface of the thin-film insulating resin pattern. A step of forming a pattern layer, and a heat-resistant resin layer having a low dielectric constant is provided on the surface on which the first thin film wiring pattern layer is formed, and the heat-resistant resin layer is patterned to form an interlayer having a required via hole. A step of forming and arranging a second thin film insulating resin pattern forming an insulating layer, and providing a conductor film on the second thin film insulating resin pattern forming surface,
This conductive film is used as one electrode, and a step of forming a filled via connection is formed by electroplating the via hole portion by electroplating to form a filled via connection substantially flush with the upper surface of the thin film insulating resin pattern. Manufacturing method of multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2796294A JPH07235768A (en) | 1994-02-25 | 1994-02-25 | Production process for thin film multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2796294A JPH07235768A (en) | 1994-02-25 | 1994-02-25 | Production process for thin film multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07235768A true JPH07235768A (en) | 1995-09-05 |
Family
ID=12235524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2796294A Pending JPH07235768A (en) | 1994-02-25 | 1994-02-25 | Production process for thin film multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07235768A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5901050A (en) * | 1996-08-21 | 1999-05-04 | Ngk Spark Plug Co., Ltd. | Wired base plate and package for electronic parts |
| JPH11243277A (en) * | 1998-02-26 | 1999-09-07 | Ibiden Co Ltd | Multilayer printed wiring board having filled via structure |
| JPH11243278A (en) * | 1998-02-26 | 1999-09-07 | Ibiden Co Ltd | Multilayer printed wiring board having filled via structure |
| JPH11243280A (en) * | 1998-02-26 | 1999-09-07 | Ibiden Co Ltd | Multilayer printed wiring board having filled via structure |
| JP2002271027A (en) * | 2001-03-14 | 2002-09-20 | Ibiden Co Ltd | Multi-layer printed board |
| JP2002280739A (en) * | 2001-03-16 | 2002-09-27 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2005277385A (en) * | 2004-02-27 | 2005-10-06 | Tdk Corp | Laminate chip inductor forming member and method of manufacturing laminate chip inductor comonent |
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-
1994
- 1994-02-25 JP JP2796294A patent/JPH07235768A/en active Pending
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| US8020291B2 (en) | 1998-09-28 | 2011-09-20 | Ibiden Co., Ltd. | Method of manufacturing a printed wiring board |
| JP2002271027A (en) * | 2001-03-14 | 2002-09-20 | Ibiden Co Ltd | Multi-layer printed board |
| US8030579B2 (en) | 2001-03-14 | 2011-10-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
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| JP2002280739A (en) * | 2001-03-16 | 2002-09-27 | Ibiden Co Ltd | Multilayer printed wiring board |
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