JPH03228351A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03228351A JPH03228351A JP2024606A JP2460690A JPH03228351A JP H03228351 A JPH03228351 A JP H03228351A JP 2024606 A JP2024606 A JP 2024606A JP 2460690 A JP2460690 A JP 2460690A JP H03228351 A JPH03228351 A JP H03228351A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input terminal
- terminal
- switch
- signal input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、外部との接続部を複数個有する半導体装置
に係り、特に接続部の選択に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device having a plurality of connection parts with the outside, and particularly relates to selection of connection parts.
［従来の技術］
第４図（ａ）、（ｂ）、（ｃ）に従来の半導体装置の概
略を示す。図において、１．ｌａ、ｌｂは半導体内部回
路と外部とを接続する接続部、２は半導体チップ、３は
ＩＣチップ、４は信号配線を示す。[Prior Art] A conventional semiconductor device is schematically shown in FIGS. 4(a), 4(b), and 4(c). In the figure, 1. la and lb are connection parts that connect the semiconductor internal circuit to the outside, 2 is a semiconductor chip, 3 is an IC chip, and 4 is a signal wiring.
次にそれぞれの違いについて説明する。Next, the differences between them will be explained.
第４図（ａ）の例は外部接続部が品種の形状により異な
る場合で、接続部１ａおよび１ｂを共通に接続し、どち
らに外部からの接続があっても良いようにした例であろ
うまた、第４図（ｂ）、（Ｃ）はそれぞれ独立した素子
として別チップに仕上げた時の状態を示す。The example in Fig. 4(a) is a case where the external connection parts differ depending on the shape of the product, and the connection parts 1a and 1b are connected in common, so that it is possible to connect from the outside to either one. Moreover, FIGS. 4(b) and 4(C) show the state when each chip is finished as an independent element.
上記のような従来の半導体装置は、２つ以上の外部との
接続部１，１ａ、ｌｂが内部で接続されたり、独立した
チップとして別々に構成されているので、それぞれ別々
にＩＣ作成マスクを作らなければならないほか、内部で
接続することで通常の２倍近くの容量を持つようになる
ため特性上問題があった。In the conventional semiconductor device as described above, two or more external connections 1, 1a, and lb are connected internally or are configured separately as independent chips, so it is necessary to create separate IC masks for each. In addition to the fact that it had to be manufactured internally, it had a capacity that was nearly twice that of the normal one, which caused problems in terms of characteristics.
この発明は、上記のような問題点を解消するためになさ
れたもので、内部容量が増加することなく、また、同−
ＩＣチップにより多種、多様の仕様を設計でき、特性の
向上および生産性の効率化が可能な半導体装置を得るこ
とを目的とする。This invention was made in order to solve the above-mentioned problems, and without increasing the internal capacity, the same
The object of the present invention is to obtain a semiconductor device that can be designed with a wide variety of specifications using an IC chip, and that can improve characteristics and streamline productivity.
この発明に係る半導体装置は、複数個の接続部と内部回
路間に電源レベルの切換信号によって接続状態を切り換
える切換回路を設け、切換信号の入力端子を電源端子の
近傍に配設したものである。The semiconductor device according to the present invention is provided with a switching circuit that switches the connection state between the plurality of connection parts and the internal circuit using a power level switching signal, and an input terminal for the switching signal is arranged near the power supply terminal. .
この発明においては、切換信号の入力端子と電源端子（
ＧＮＤ端子を含む）とが接続されることにより、使用さ
れる外部との接続部が特定される。In this invention, the switching signal input terminal and the power supply terminal (
(including the GND terminal), the external connection part to be used is specified.
第１図はこの発明の半導体装置の一実施例を説明するた
めの回路図である。第１図において、１１．１２はそれ
ぞれ前記接続部１ａ、ｌｂと接続される信号入力端子、
１３ａ、１３ｂは前記信号入力端子１１．１２から入力
される信号の切換えを制御する切換信号用入力端子、１
４．１５はＮチャネルＭＯ３＋−ランジスタからなるプ
ルダウン１−ランンスタ、１６，１７Ｌｔｌ・ランスミ
ツンヨンゲ−１・、２０は前記入力端子１３ａ、１３ｂ
からの信号により切換えを行う切換回路ブロックを示す
。また、第２図はＩＣチップ３上の配置の一例を示す平
面図で、５は電源端子、６はＧＮＤ端子、７はフレーム
のグイパッド部、８は７し一ムのワイヤボンディング端
子である。FIG. 1 is a circuit diagram for explaining one embodiment of the semiconductor device of the present invention. In FIG. 1, 11.12 are signal input terminals connected to the connection parts 1a and lb, respectively;
13a and 13b are switching signal input terminals for controlling switching of signals input from the signal input terminals 11 and 12;
4.15 is a pull-down 1-run transistor consisting of an N-channel MO3+- transistor, 16, 17 Ltl, 1-1, 20 are the input terminals 13a, 13b.
This shows a switching circuit block that performs switching based on signals from. Further, FIG. 2 is a plan view showing an example of the arrangement on the IC chip 3, in which 5 is a power terminal, 6 is a GND terminal, 7 is a pad portion of the frame, and 8 is a wire bonding terminal of 7 and 1.
次に、第２図を参照して第１図に示した回路の動作につ
いて説明する。Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG.
この回路では、入力端子１３ａを電源端子５と、または
入力端子１３ｂｅＧＮＤ端子６と接続する２ｂ式が考え
られる。In this circuit, a 2b type in which the input terminal 13a is connected to the power supply terminal 5 or the input terminal 13be to the GND terminal 6 can be considered.
まず、入力端子１３ａを電源端子５と接続した場合は、
信号入力端子１２に接続されているプルダウントランジ
スタ１５を“ＯＮ”状態とし、信号入力端子１１に接続
されているプルダウントランジスタ１４を“ＯＦＦ”状
態とする。また、切換回路ブロック２０は信号入力端子
１１からの接続上にあるトランスミッションゲ−１・１
ＳをＯＮ Ｉ＋状態にし、逆に信号入力端子１２からの
接続上にあるトランスミッションゲート
Ｆ”状態とし、信号入力端子１１からの信号を内部に伝
えることができる。First, when the input terminal 13a is connected to the power supply terminal 5,
The pull-down transistor 15 connected to the signal input terminal 12 is turned on, and the pull-down transistor 14 connected to the signal input terminal 11 is turned off. The switching circuit block 20 also connects transmission gates 1 and 1 connected to the signal input terminal 11.
S is set to the ON I+ state, and conversely, the transmission gate on the connection from the signal input terminal 12 is set to the F'' state, so that the signal from the signal input terminal 11 can be transmitted internally.
次に入力端子１３ｂをＧＮＤ端子６に接続した場合、上
記の場合とは逆に信号入力端子１２に接続されているプ
ルダウントランジスタ１５がＯＦＦ”、信号入力端子１
１に接続されているプルダウン１−ランジスタ１４が’
ＯＮ” また、切換回路プロ・ツク２０内のトランスミ
ッンヨンゲ−１・１６がＯＦＦ” トランスミッシ
ョンゲート１７が゛ＯＮ″状態となり、信号入力端子１
２からの信号を内部に伝えることができる。Next, when the input terminal 13b is connected to the GND terminal 6, the pull-down transistor 15 connected to the signal input terminal 12 is turned OFF, contrary to the above case, and the signal input terminal 1
Pull-down 1-transistor 14 connected to '
"ON" Also, the transmission gates 1 and 16 in the switching circuit program 20 are "OFF" and the transmission gate 17 is in the "ON" state, and the signal input terminal 1
Signals from 2 can be transmitted internally.
すなわち、この発明によれば、入力端子１３ａ。That is, according to the invention, the input terminal 13a.
１３ｂの一方を電源端子５またはＧＮＤ端子６に接続す
ることによって、信号入力端子１１．１２のうちの一方
が選択される構成としているので、あらかじめ信号入力
端子１１．１２をそれぞれ接続部１ａ，ｌｂに接続して
おけば、ワイヤボンディング端子８の形状を変更してワ
イヤボンディングするだけで容易に一方の接続部１ａま
たは１ｂを選択で゛き、接続部１ａの位置からの接続と
、接続部１ｂからの接続を同一チップを用いて行える。Since one of the signal input terminals 11.12 is selected by connecting one of the signal input terminals 11.13b to the power supply terminal 5 or the GND terminal 6, the signal input terminals 11.12 are connected in advance to the connection parts 1a and 1b, respectively. If the connection is made in advance, one of the connection parts 1a or 1b can be easily selected by simply changing the shape of the wire bonding terminal 8 and performing wire bonding, and the connection from the position of the connection part 1a and the connection from the connection part 1b can be easily selected. can be connected using the same chip.
また、接続部ｌａ，ｌｂに接続されることになるプルダ
ウントランジスタ１４．１５は使用しない側の信号入力
端子１１または１２をフローティングにしないように固
定している。Further, the pull-down transistors 14 and 15 to be connected to the connection portions la and lb are fixed so that the unused signal input terminal 11 or 12 is not floating.
なお、上記実施例では、１本の内部信号を２本の入力端
子１３ａ，１３ｂから選択できる構成のものを示したが
、第３図に示すように、信号入力端子１１，１２に入力
される信号の組合せと信号入力端子１２．１８に入力さ
れる信号の組合せから選択する回路を構成することもで
きることはいうまでもない。In the above embodiment, one internal signal can be selected from two input terminals 13a and 13b, but as shown in FIG. It goes without saying that it is also possible to configure a circuit that selects from a combination of signals and a combination of signals input to the signal input terminals 12.18.
この発明は以上説明したとおり、複数個の接続部と内部
回路間に電源レベルの切換信号によって接続状態を切り
換える切換回路を設け、切換信号の入力端子を電源端子
の近傍に配設したので、切換信号の入力端子と電源端子
（Ｇ Ｎ Ｄ端子を含む）とを接続するだけで使用され
る外部との接続部が特定できることになり、同一ＩＣチ
ップにより多種，多様の仕様を設計でき、特性の向上お
よび生産性の効率化を図ることができるという効果があ
リ、また、内部容量が増加することもない。As explained above, in this invention, a switching circuit is provided between a plurality of connection parts and an internal circuit to switch the connection state using a power level switching signal, and the input terminal for the switching signal is disposed near the power supply terminal. By simply connecting the signal input terminal and the power supply terminal (including the GND terminal), you can specify the external connection part to be used, allowing you to design a wide variety of specifications using the same IC chip, and making it possible to design various specifications with the same IC chip. This has the effect of improving efficiency and productivity, and the internal capacity does not increase.
第１図はこの発明の半導体装置の一実施例を説明するた
めに回路図、第２図はＩＣチップ上の配置の一例を示す
平面図、第３図はこの発明の他の実施例を示す回路図、
第４図は従来の半導体装置の概略を示す平面図である。
図において、１ａ、１ｂは接続部、３はＩＣチップ、５
は電源端子、６ばＧＮＤ端子、７はダイパ・フド部、８
はワイヤボンデ、ｒング端子、１１゜１２．１８は信号
入力端子、１３ａ、１３ｂは切換信号用入力端子、１４
．１５はプルダウントランジスタ、１６．１７＋ｉ＋・
ランスミッションゲート、２０は切換回路ブロックであ
る。
なお、各図中の同一符号は同一または相当部分をボす、
。FIG. 1 is a circuit diagram for explaining one embodiment of the semiconductor device of the present invention, FIG. 2 is a plan view showing an example of the arrangement on an IC chip, and FIG. 3 is a diagram showing another embodiment of the invention. circuit diagram,
FIG. 4 is a plan view schematically showing a conventional semiconductor device. In the figure, 1a and 1b are connection parts, 3 is an IC chip, and 5
is the power supply terminal, 6 is the GND terminal, 7 is the dieper hood part, 8
11゜12.18 is a signal input terminal, 13a, 13b is a switching signal input terminal, 14 is a wire bonding terminal,
．． 15 is a pull-down transistor, 16.17+i+・
The transmission gate 20 is a switching circuit block. In addition, the same symbols in each figure indicate the same or corresponding parts.
.
Claims (1)
記複数個の接続部と内部回路間に電源レベルの切換信号
によって接続状態を切り換える切換回路を設け、前記切
換信号の入力端子を電源端子の近傍に配設したことを特
徴とする半導体装置。In a semiconductor device having a plurality of connection parts with the outside, a switching circuit is provided between the plurality of connection parts and the internal circuit to switch the connection state by a power level switching signal, and the input terminal of the switching signal is connected near the power supply terminal. A semiconductor device characterized by being arranged in a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024606A JPH03228351A (en) | 1990-02-02 | 1990-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024606A JPH03228351A (en) | 1990-02-02 | 1990-02-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03228351A true JPH03228351A (en) | 1991-10-09 |
Family
ID=12142811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024606A Pending JPH03228351A (en) | 1990-02-02 | 1990-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03228351A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009193658A (en) * | 2008-02-14 | 2009-08-27 | Hynix Semiconductor Inc | Input circuit of semiconductor memory apparatus and controlling method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01280923A (en) * | 1988-05-07 | 1989-11-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1990
- 1990-02-02 JP JP2024606A patent/JPH03228351A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01280923A (en) * | 1988-05-07 | 1989-11-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009193658A (en) * | 2008-02-14 | 2009-08-27 | Hynix Semiconductor Inc | Input circuit of semiconductor memory apparatus and controlling method thereof |
| US8477557B2 (en) | 2008-02-14 | 2013-07-02 | SK Hynix Inc. | Input circuit of semiconductor memory apparatus and controlling method thereof |
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