JPH01266718A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPH01266718A JPH01266718A JP9443888A JP9443888A JPH01266718A JP H01266718 A JPH01266718 A JP H01266718A JP 9443888 A JP9443888 A JP 9443888A JP 9443888 A JP9443888 A JP 9443888A JP H01266718 A JPH01266718 A JP H01266718A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact window
- barrier
- metal
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000004065 semiconductor Substances 0.000 title description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000011368 organic material Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 2
- 230000003014 reinforcing effect Effects 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GOQFGEHFZBDYEC-UHFFFAOYSA-N [AlH2+] Chemical compound [AlH2+] GOQFGEHFZBDYEC-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造方法、特に半導体装置の電極形成にお
いて、バリアメタルの形成に平坦化工程を用いることに
より電極配線を形成する方法に関し、
半導体装置の電極形成において、バリア性が大きく、微
細化構造に適した半導体装置の電極の製造方法を提供す
ることを目的とし、
下地との電気的接触を形成する領域にコンタクト窓を形
成する工程と、
このコンタクト窓に成長したバリアメタル表面を有機材
の膜により平坦化し異方性エツチングによる平坦化工程
を１回以上繰返すことを特徴とする半導体装置の製造方
法を含み構成する。[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing a semiconductor device, particularly a method of forming an electrode wiring by using a planarization process for forming a barrier metal in forming an electrode of a semiconductor device. The purpose of the present invention is to provide a method for manufacturing an electrode for a semiconductor device that has a high barrier property and is suitable for a miniaturized structure, and includes a process for forming a contact window in a region where electrical contact with a base is to be formed; The present invention includes a method for manufacturing a semiconductor device, characterized in that the surface of a barrier metal grown on the surface is flattened with a film of an organic material, and a flattening process by anisotropic etching is repeated one or more times.
本発明は、半導体装置の製造方法、特にバリアメタルの
形成に平坦化工程を用いることにより電極配線を形成す
る方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming electrode wiring by using a planarization process for forming a barrier metal.
従来、半導体装置の製造において、素子の微細化ととも
に動作速度が向上してきており、それにともない接合が
浅くなってきている。そのために電極配線の形成には、
配線金属とシリコンとの間の相互拡散により生じる接合
破壊などを防止するために、相互拡散の防止用のバリア
メタルが用いられている。Conventionally, in the manufacture of semiconductor devices, operating speeds have improved as elements have become smaller and junctions have become shallower. For this reason, in the formation of electrode wiring,
In order to prevent junction breakdown caused by mutual diffusion between wiring metal and silicon, a barrier metal for preventing mutual diffusion is used.
第５図はこのような従来の電極配線部分を示す断面図で
ある。同図に示す如く、シリコン基板１に形成された拡
散領域２上には、酸化シリコン（ＳｉＯ□）膜３を除去
してコンタクト窓４が形成され、このコンタクト窓４内
にコンタクトメタル５、バリアメタル６がスパッタリン
グ法などにより形成され、そのバリアメタル６上にアル
ミニュウム（ｉ）、金（Ａｕ）などの配線用の導電メタ
ル７が形成されている。このコンタクトメタル５は、下
地のシリコン基板１とのオーミックコンタクトなどの電
気的接触を形成するために設けられるものである。また
、バリアメタル６は、下地のシリコンと導電メタル７で
あるＡ１、Ａｕなどとの間の相互拡散を防止し、接合破
壊が生じないようにするため設けられるものである。こ
のバリアメタル６としては、例えば、窒化チタン（チタ
ンナイトライド：ＴｉＮ）などが多用されている。FIG. 5 is a sectional view showing such a conventional electrode wiring portion. As shown in the figure, a contact window 4 is formed on a diffusion region 2 formed in a silicon substrate 1 by removing a silicon oxide (SiO□) film 3, and a contact metal 5, a barrier A metal 6 is formed by sputtering or the like, and a conductive metal 7 for wiring such as aluminum (i) or gold (Au) is formed on the barrier metal 6. This contact metal 5 is provided to form an electrical contact such as an ohmic contact with the underlying silicon substrate 1. Further, the barrier metal 6 is provided to prevent mutual diffusion between the underlying silicon and the conductive metal 7 such as A1, Au, etc., and to prevent junction breakdown from occurring. As this barrier metal 6, for example, titanium nitride (TiN) is often used.
しかし、従来のバリアメタル６は、コンタクト窓４の段
差となる側壁部分での膜厚が薄くなり、かつ膜質か弱く
、バリア性が不完全となる欠点があった。これは、バリ
アメタル６がスパッタリング法などにより堆積されるた
め、側壁部分の膜質が平坦部分の膜質より悪く、かつ側
壁部分の膜と平坦部分の膜の成長方向に違いが生じ、そ
の境界に不連続線ができることによるものである。この
ため、従来はバリアメタル６を厚く堆積したり、あるい
は種々の熱処理などを施していたが、必ずしもバリア性
は十分ではなく、微細化の支障になっていた。However, the conventional barrier metal 6 has the disadvantage that the film thickness is thinner at the side wall portion where the contact window 4 is stepped, and the film quality is weak, resulting in incomplete barrier properties. This is because the barrier metal 6 is deposited by a sputtering method, etc., so the film quality on the sidewall part is worse than the film quality on the flat part, and there is a difference in the growth direction of the film on the sidewall part and the film on the flat part, and there is a problem at the boundary. This is due to the formation of continuous lines. For this reason, in the past, the barrier metal 6 was deposited thickly or various heat treatments were performed, but the barrier properties were not always sufficient and this became an obstacle to miniaturization.
本発明は、半導体装置の電極形成において、バリア性が
大きく、微細化構造に適した半導体装置の製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that has a high barrier property and is suitable for a miniaturized structure in forming electrodes of the semiconductor device.
上記目的は、下地との電気的接触を形成する領域にコン
タクト窓を形成する工程と、このコンタクト窓に成長し
たバリアメタル表面を有機材の膜により平坦化し異方性
エツチングによる平坦化工程を１回以上繰返すことを特
徴とする半導体装置の製造方法によって解決される。The above purpose is to form a contact window in the area where electrical contact with the base is to be made, and to planarize the surface of the barrier metal grown on the contact window with an organic material film and then perform anisotropic etching. The problem is solved by a semiconductor device manufacturing method characterized by repeating the process more than once.
すなわち、本発明はコンタクト窓に成長したバリアメタ
ルの異方性エツチングによる平坦化工程を行うため、コ
ンタクト窓の側壁部分のバリアメタルの膜厚が厚くなり
、膜質が強くなり、バリア性が向上する。That is, since the present invention performs a planarization process by anisotropic etching of the barrier metal grown on the contact window, the film thickness of the barrier metal on the side wall portion of the contact window becomes thicker, the film quality becomes stronger, and the barrier properties are improved. .
以下、本発明を図示の一実施例により具体的に説明する
。Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.
第１図（ａ）〜（ｅ）は本発明実施例の電極配線部分の
製造工程断面図である。FIGS. 1(a) to 1(e) are cross-sectional views of the manufacturing process of the electrode wiring portion according to the embodiment of the present invention.
まず、同図（ａ）に示す如く、電気的な接触などのコン
タクト部分を形成する例えばシリコン基板１１の拡散領
域１２上には、図示しない工程により酸化シリコン（Ｓ
ｉＯ□）膜１３を除去して幅が１μｍ程度のコンタクト
窓１４が形成される。このコンタクト窓１４内にバリア
メタルとして、第１のＴｉＮ膜１５を反応性マグネトロ
ンスパッタリング法により２０００人程度０膜厚に堆積
する。この反応性マグネトロンスパッタリング法による
第１のＴｉＮ膜１５の形成条件は、例えば、圧力が５
Ｘ １０” ’ ｔｏｒｒ、アルゴンと窒素ガス（Ａｒ
＋Ｎｚ）が流量比で１：１の割合の雰囲気中で、大きさ
が直径２０ｃｍ、厚さ５ ｍｍ程度の円形のチタン（Ｔ
ｉ）ターゲットに、３に一程度のエネルギーを投入し、
対向する１０ｃｍ離れた上記シリコン基板１１で２分間
程度成長して、約２００００程度の膜厚の第１のＴｉＮ
膜１５を得る。次に、同図（ｂ）に示す如く、上記第１
のＴｉＮ膜１膜上５上平坦部分において、膜厚が３００
０人程度０なるように有機材の膜例えばレジスト膜１６
を塗布する。これによりコンタクト窓１４は流動性をも
ったレジスト膜１６により表面がほぼ平坦に埋められる
。First, as shown in FIG. 3A, silicon oxide (S
By removing the iO□) film 13, a contact window 14 with a width of about 1 μm is formed. A first TiN film 15 is deposited as a barrier metal in this contact window 14 to a thickness of about 2000 by reactive magnetron sputtering. The conditions for forming the first TiN film 15 by this reactive magnetron sputtering method are, for example, a pressure of 5
X 10” torr, argon and nitrogen gas (Ar
+ Nz) in an atmosphere with a flow rate ratio of 1:1, a circular titanium (T
i) Inject about 1 in 3 energy into the target,
The first TiN film is grown for about 2 minutes on the opposing silicon substrates 11 10 cm apart to have a film thickness of about 20,000.
A membrane 15 is obtained. Next, as shown in FIG.
The film thickness is 300 mm at the flat part on the TiN film 1 film 5.
A film of organic material, for example, a resist film 16, is applied so that the number of people becomes about 0.
Apply. As a result, the surface of the contact window 14 is filled with a fluid resist film 16 so that the surface thereof is substantially flat.
次に、同図（Ｃ）に示す如く、平行平板型の反応性イオ
ンエツチング（ＲＩＥ）により、平坦部分の第１のＴｉ
Ｎ膜１５はぼが除去される程度に、エツチングする（エ
ッチバック）。このエツチング条件は、例えば、枚葉式
ＲＩＥ装置により、フレオン（ＣＦ、）に５χ程度の酸
素ガス（０□）を加えた雰囲気中で、圧力が０．１５ｔ
ｏｒｒ、５０〇−程度のエネルギーを投入し、５分程度
実施する。これにより、表面がほぼ平坦化される。Next, as shown in FIG.
The N film 15 is etched (etched back) to the extent that the warps are removed. This etching condition is, for example, performed using a single-wafer type RIE apparatus in an atmosphere in which about 5χ of oxygen gas (0□) is added to Freon (CF) at a pressure of 0.15 t.
Input about 500 orr of energy and carry out for about 5 minutes. This makes the surface substantially flat.
次に、同図（ｄ）に示す如く、コンタクト窓１４内のレ
ジスト膜１６を剥離する。この剥離条件は、ドライエツ
チングでは、例えば、枚葉式アッシャ−により、酸素ガ
ス（０□）１００χの雰囲気中で、圧力が１ｔｏｒｒ
、５００Ｗ程度のエネルギーを投入し、１００分程実施
する。そして、次に、スパッタ装置により表面を１００
人程０、高周波（ＲＦ）エッチクリーニングを行う。こ
のクリーニング条件は、アルゴン（Ａｒ）ガスの雰囲気
中で、圧力がＩ Ｘ １０−”ｔｏｒｒ、０．２Ｗ／ｃ
ｍ”程度のエネルギーを投入し、３分程度行う。Next, as shown in FIG. 4(d), the resist film 16 within the contact window 14 is peeled off. In dry etching, this peeling condition is, for example, a single wafer type asher in an atmosphere of oxygen gas (0□) 100χ at a pressure of 1 torr.
, input about 500W of energy and carry out the test for about 100 minutes. Then, the surface is coated with 100% by sputtering equipment.
Perform radio frequency (RF) etch cleaning at 0°C. The cleaning conditions are as follows: In an argon (Ar) gas atmosphere, the pressure is I x 10-” torr, 0.2 W/c.
Input about 300 m of energy and do it for about 3 minutes.
次に、同図（ｅ）に示す如（、上記同図（ａ）に示す工
程と同様の条件により、第２のＴｉＮ膜１７を２０００
人程度０膜厚に堆積する。Next, the second TiN film 17 is coated at a temperature of 2,000 mL under the same conditions as in the process shown in FIG.
The film is deposited to a thickness of about 0.
上記電極部分の製造方法によれば、コンタクト窓１４内
に第１のＴｉＮ膜１５を形成し、エッチバック後に平坦
化後に第２のＴｉＮ膜１７を形成することにより、コン
タクト窓４内にバリアメタルが形成される。このバリア
メタルは、コンタクト窓４の段差となる側壁部分の膜厚
が厚く補強され、膜質が強くなる。従って、バリア性も
大きくなる。そして、上記したエッチバックを後述する
如くに複数回繰返すことによって、特性の良い電極を形
成することが可能になる。According to the method for manufacturing the electrode portion, the first TiN film 15 is formed within the contact window 14, and the second TiN film 17 is formed after etchback and planarization, thereby forming the barrier metal within the contact window 4. is formed. This barrier metal is reinforced with a thick film at the side wall portion that forms the step of the contact window 4, and the film quality is strengthened. Therefore, the barrier properties are also increased. Then, by repeating the above-described etch-back multiple times as described later, it becomes possible to form an electrode with good characteristics.
第２図は上記方法により製造される電極部分の断面図で
ある。上記方法によりエッチバックで形成されたＴｉＮ
膜２膜上１上、純アルミニュウム配線膜２２が７０００
人程度０膜厚に形成される。なお、第１図に対応する部
分は同一の符号を記す。FIG. 2 is a sectional view of an electrode portion manufactured by the above method. TiN formed by etching back by the above method
On film 2, on film 1, pure aluminum wiring film 22 has a thickness of 7000
The film is formed to a thickness of about 0. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.
第３図（ａ）及び（ｂ）は本発明のバリア性を試験する
ために形成された電極部分の断面図である。FIGS. 3(a) and 3(b) are cross-sectional views of electrode portions formed to test the barrier properties of the present invention.
まず、同図（ａ）に示す如く、バリア性を試験するため
に、１００個程度のコンタクト窓１４を形成し、このコ
ンタクト窓１４に上記第２図に示すように、エッチバッ
クによりＴｉＮ膜２１を形成し、その上に純アルミニュ
ウム配線膜２２を７０００人程度０膜厚に形成した。そ
して、４８０°Ｃ１３０分間の熱処理を３回はど繰り返
した。この熱処理によりＴｉＮ膜２１に欠陥があると、
純アルミニュウム配線膜２２とシリコン基板１１との間
の相互拡散が生じる。First, as shown in FIG. 2A, in order to test the barrier property, about 100 contact windows 14 are formed, and as shown in FIG. A pure aluminum wiring film 22 was formed thereon to a thickness of about 7,000. Then, heat treatment at 480° C. for 130 minutes was repeated three times. If there is a defect in the TiN film 21 due to this heat treatment,
Mutual diffusion occurs between the pure aluminum wiring film 22 and the silicon substrate 11.
その後、同図（ｂ）に示す如く、王水で純アルミニュウ
ム配線膜２２と、ＴｉＮ膜２１を除去して、下地である
シリコン基板１１のくわれ（不良箇所）を観察した。Thereafter, as shown in FIG. 4B, the pure aluminum wiring film 22 and the TiN film 21 were removed with aqua regia, and the cracks (defective spots) in the underlying silicon substrate 11 were observed.
第４図は本発明実施例によるバリア性の試験結果を示す
図である。同図において、横軸はエッチバックの回数、
すなわち、ＴｉＮ膜２１を形成するときのエツチングの
繰り返し回数であり、縦軸はサンプル数に対する不良箇
所数の割合（χ）で、バリア性を示す。同図に示す如く
、バリア性は、エッチバック回数の増加とともに徐々に
向上し、５回のエッチバック回数では７０χを示してい
る。この結果は、エッチバック回数の増加でコンタクト
窓１４側壁のＴｉＮ膜２１の膜厚が厚くなり、膜質が強
くなり、バリア性が向上することを示す。FIG. 4 is a diagram showing the test results of barrier properties according to examples of the present invention. In the figure, the horizontal axis is the number of etchbacks,
That is, it is the number of repetitions of etching when forming the TiN film 21, and the vertical axis is the ratio (χ) of the number of defective locations to the number of samples, which indicates the barrier property. As shown in the figure, the barrier property gradually improves as the number of etchbacks increases, and shows 70χ after 5 etchbacks. This result shows that as the number of times of etch-back increases, the thickness of the TiN film 21 on the side wall of the contact window 14 becomes thicker, the film quality becomes stronger, and the barrier properties are improved.
なお、本発明においては、少なくとも１回以上のエッチ
バックによる平坦化工程によりコンタクト窓１４にＴｉ
Ｎ膜を形成すればよく、複数回行えばさらに膜厚が厚く
なり、膜質が強くなり、バリア性が向上する。コンタク
ト窓１４は、下地と電気的な接触を形成する領域に形成
されればよい。In addition, in the present invention, Ti is deposited on the contact window 14 by a planarization process by etching back at least once.
It is only necessary to form an N film, and if the process is repeated multiple times, the film thickness will become even thicker, the film quality will become stronger, and the barrier properties will improve. The contact window 14 may be formed in a region where electrical contact is to be made with the underlying layer.
また、実施例においては、チタンナイトライド（ＴｉＮ
）を用いているが、通常用いられるバリアメタルにも適
用できる。In addition, in the examples, titanium nitride (TiN
), but it can also be applied to commonly used barrier metals.
さらに、バリアメタルの膜厚、成形条件は配線金属ある
いは、トランジスタの特性などに応じて任意にでき、実
施例に限定されない。Further, the film thickness of the barrier metal and the forming conditions can be arbitrarily determined depending on the wiring metal, the characteristics of the transistor, etc., and are not limited to the examples.
以上説明したように本発明によれば、下地と電気的接触
を形成する領域上にコンタクト窓を形成し、このコンタ
クト窓に異方性エツチングによる平坦化工程を用いるこ
とによりバリアメタルを形成するため、コンタクト窓の
側壁部分のバリアメタルの膜厚が厚くなり、膜質が強（
なり、バリア性が向上する。As explained above, according to the present invention, a contact window is formed on a region where electrical contact is to be made with a base, and a barrier metal is formed on this contact window by using a planarization process using anisotropic etching. , the thickness of the barrier metal on the side wall of the contact window becomes thicker, and the film quality becomes stronger (
and the barrier properties are improved.
第１図（ａ）〜（ｅ）は本発明実施例の製造工程断面図
、第２図は本発明実施例の電極部分の断面図、第３図（
ａ）及び（ｂ）は本発明実施例のバリア性を試験するた
めの電極部分の断面図、
第４図は本発明実施例のバリア性の試験結果を示す図、
第５図は従来の電極配線部分を示す断面図である。
図中、
１１はシリコン基板、
１２は拡散領域、
１３は酸化シリコン（ＳｉＯｚ）膜、
１４はコンタクト窓、
１５は第１のＴｉＮ膜、
１６はレジスト膜、
１７はＴｉＮ膜、
２１はＴｉＮ膜、
２２は純アルミニュウム配線膜、
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰
−Ｎ（イ）ぐＬｒ１■ト
メ１−２ メー＼
、−２１１ａ
−Ｏｕ
一〇 〇Figures 1 (a) to (e) are sectional views of the manufacturing process of the embodiment of the present invention, Figure 2 is a sectional view of the electrode portion of the embodiment of the present invention, and Figure 3 (
a) and (b) are cross-sectional views of the electrode portion for testing the barrier properties of the examples of the present invention, Figure 4 is a diagram showing the test results of the barrier properties of the examples of the present invention, and Figure 5 is the conventional electrode. FIG. 3 is a cross-sectional view showing a wiring portion. In the figure, 11 is a silicon substrate, 12 is a diffusion region, 13 is a silicon oxide (SiOz) film, 14 is a contact window, 15 is a first TiN film, 16 is a resist film, 17 is a TiN film, 21 is a TiN film, 22 represents a pure aluminum wiring film. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Kukimoto-N(i)gu Lr1 ■ Tome 1-2 Me ＼
, -211a
-Ou 10 〇
Claims (1)
１４）を形成する工程と、 このコンタクト窓（１４）に成長したバリアメタル表面
を有機材の膜により平坦化し異方性エッチングによる平
坦化工程を１回以上繰返すことを特徴とする半導体装置
の製造方法。[Claims] A contact window (
14) and the step of flattening the surface of the barrier metal grown on the contact window (14) with a film of an organic material and flattening by anisotropic etching are repeated one or more times. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094438A JP2750860B2 (en) | 1988-04-19 | 1988-04-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63094438A JP2750860B2 (en) | 1988-04-19 | 1988-04-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01266718A true JPH01266718A (en) | 1989-10-24 |
| JP2750860B2 JP2750860B2 (en) | 1998-05-13 |
Family
ID=14110261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63094438A Expired - Lifetime JP2750860B2 (en) | 1988-04-19 | 1988-04-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2750860B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5427980A (en) * | 1992-12-02 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Method of making a contact of a semiconductor memory device |
| US5693562A (en) * | 1996-06-28 | 1997-12-02 | Vanguard International Semiconductor Corporation | Method for forming a barrier metal film with conformal step coverage in a semiconductor integrated circuit |
| US5717250A (en) * | 1994-08-15 | 1998-02-10 | Micron Technology, Inc. | Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug |
| US5904561A (en) * | 1996-06-28 | 1999-05-18 | Vanguard International Semiconductor Corporation | Method for forming a barrier metal film with conformal step coverage in a semiconductor intergrated circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61295628A (en) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Method for forming barrier metal in contact hole |
| JPS6321855A (en) * | 1986-07-15 | 1988-01-29 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPH01230269A (en) * | 1988-03-09 | 1989-09-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1988
- 1988-04-19 JP JP63094438A patent/JP2750860B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61295628A (en) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Method for forming barrier metal in contact hole |
| JPS6321855A (en) * | 1986-07-15 | 1988-01-29 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPH01230269A (en) * | 1988-03-09 | 1989-09-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5427980A (en) * | 1992-12-02 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Method of making a contact of a semiconductor memory device |
| US5717250A (en) * | 1994-08-15 | 1998-02-10 | Micron Technology, Inc. | Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug |
| US6093615A (en) * | 1994-08-15 | 2000-07-25 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
| US6313031B1 (en) | 1994-08-15 | 2001-11-06 | Micron Technology, Inc. | Method of fabricating a contract structure having a composite barrier layer between a platinum layer and a polysilicon plug |
| US6589867B2 (en) | 1994-08-15 | 2003-07-08 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
| US6930039B2 (en) | 1994-08-15 | 2005-08-16 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
| US5693562A (en) * | 1996-06-28 | 1997-12-02 | Vanguard International Semiconductor Corporation | Method for forming a barrier metal film with conformal step coverage in a semiconductor integrated circuit |
| US5904561A (en) * | 1996-06-28 | 1999-05-18 | Vanguard International Semiconductor Corporation | Method for forming a barrier metal film with conformal step coverage in a semiconductor intergrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2750860B2 (en) | 1998-05-13 |
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