GB2136203A - Through-wafer integrated circuit connections - Google Patents
Through-wafer integrated circuit connections Download PDFInfo
- Publication number
- GB2136203A GB2136203A GB08305761A GB8305761A GB2136203A GB 2136203 A GB2136203 A GB 2136203A GB 08305761 A GB08305761 A GB 08305761A GB 8305761 A GB8305761 A GB 8305761A GB 2136203 A GB2136203 A GB 2136203A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- wafer
- circuit package
- device components
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Integrated circuit device components are provided at a first surface of a semiconductor wafer either by formation directly within the wafer (1 - Fig. 2) or bonding a separate chip (15) to the wafer (12 - Fig. 3). The wafer is provided with discrete electrical connections (13 - Fig. 3) extending therethrough from the first to the opposite surface either by diffusion and etching (Figs. 2 and 3), or forming dielectrically insulated conductive islands. The device components are electrically connected to the discrete connections at the first surface and external metallisation, forming contact pads (8), is provided at the second surface so that the overall package can be directly mounted to a substrate. The device components are encapsulated by a passivating layer (11) on the first surface (Fig. 2), or a cover (16) bonded to the first surface (Fig. 3). The packaging technique is particularly applicable to very high power integrated circuits of large areas and high pin count. <IMAGE>
Description
SPECIFICATION integrated circuit packaging
This invention relates to integrated circuit packages and packaging methods and in particular, but not exclusively, to packaging for very high power dissipation devices.
Conventional low power VLSI devices use packaging techniques, such as standard DIL packages, which are not readily extendible to the large area devices with large pin counts that are proposed for the VLSI within the VHPIC (Very High
Power Integrated Circuits) programme. Typically that programme envisages single devices, up to 1 cm square silicon, with a 100 to 200 input/output pin count and a power dissipation of up to 10 watts, and large area devices, up to 4 cm square silicon on which there are discrete areas of devices, with a pin count of up to 1000 and a power dissipation of up to 100 watts.Packaging for such VHPIC devices is unlikely to be achieved by extension of conventional packaging techniques, primarily because of yield limitations on bonding and feedthrough connections, but also due to thermal resistance problems, particularly as a result of voids introduced when bonding large area chips to mounts therefor, such as by friction alloying. Conventionally chips may be mounted to a substrate, interconnections to lead frame terminals made by wire bonding techniques and the chips encapsulated. Other known methods employ "flip chips", or bonding applied to chip carriers, which introduce passivation problems and reduce chip power dissipation capabilities.
According to one aspect of the present invention there is provided an integrated circuit package including a semiconductor wafer having a first surface at which integrated circuit device components are arranged, a second surface and at least one discrete electrical connection extending through the wafer between the first and second surfaces.
According to another aspect of the present invention there is provided an integrated circuit packaging method including the steps of providing integrated circuit device components at a first surface of a semiconductor wafer and providing at least one discrete electrical connection extending through the wafer between the first surface and a second surface thereof.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which:~
Fig. 1 shows a section through a portion of a semiconductor wafer having a through connection according to one embodiment of the present invention:
Fig. 2 shows the wafer of Fig. 1 after further processing;
Fig. 3 shows a section through an encapsulated integrated circuit device employing a semiconductor substrate with through connections as shown in Fig. 1 as a mount;
Fig. 4 shows a section through a portion of a semiconductor wafer or element provided with cooling channels, and
Fig. 5 shows a section through an encapsulated integrated circuit device employing a semiconductor substrate, with an alternative form of through connections, as a mount.
Referring firstly to Fig. 1, an n-type < 100 > orientation silicon wafer or element 1 is provided with a silicon dioxide layer 2 on one side. Window areas such as 3 are opened in the oxide layer 2 and the underlying wafer is heavily doped, for example with boron, to provide p-type regions or wells as at 4. Thus there are provided low resistivity wells of, for example 10-2 ohm cm and 10 micrometre deep at positions corresponding to required connection feedthrough points. The other side of wafer 1 which has a silicon dioxide layer 5 thereon is then masked and etched to open windows such as 6 in alignment with windows such as 3. Chemical etching is then employed to remove the silicon of water 1 exposed by opening windows 6. The silicon is etched away up to the wells, such as 4, which heavily doped regions act as effective etch stops.The etching of the silicon is thus a self-stopping process and provides direct - access to the underside of the doped well 4. The aspect ratio of the well, that is its effective area relative to the corresponding window area, provides a further large reduction factor in the through connection resistance, bringing it down to less than 1 milliohm. In order to make the connection area provided by well 4 accessible for metallisation and patterning at the underside of wafer 1, a further p-type diffusion 7 into the walls of the etched opening in the wafer may be made.
Which further diffusion 7 is contiguous with that of the well 4. Metallisation as indicated at 8 is then provided. The process steps involved in the above, such as oxide growing, masking, etching, diffusion, metallisation, patterning, may be entirely conventional.
The wafer with through connections as illustrated in Fig. 1 may be employed in two basic ways. Either the VLSI device components may be formed directly in the wafer (Fig. 2) or the VLSI device components may be formed in a separate chip which is then bonded to the throughconnected wafer (Fig. 3).
In the case of integral VLSI formation, a VLSI device indicated generally at 9 (Fig. 2) is formed by conventional techniques in the upper surface of the wafer 1. Interconnection between the VLSI device terminals and the through connection provided at wells 4 is by way of metallic tracks 10, for example, etched aluminium interconnections provided in a conventional manner. A continuous passivating layer of, for example, silicon nitride 11 is then provided over the upper surface of the wafer as shown. The VLSI circuit thus produced requires no additional packaging and can, for example, be directly mounted to a suitable circuit board.
In the case of a separate chip for the VLSI device, as illustrated in Fig. 3, a semiconductor element 12 with through connections such as 13 is manufactured as described above with reference to Fig. 1. The silicon dioxide layer 2 is removed except where it is required for insulation purposes such as adjacent wells 4. A thin glass bonding layer 14, such as Pyrex glass, is deposited on the element 12 at positions which will subsequently be under a VLSI chip 15 and the edge of a cover 16. The VLSI chip 15 is then diffusion bonded to the element 12 via layer 14 which comprises a glass which is conductive at the temperatures employed for diffusion bonding, typically 200#4000 C, which employs a high electric field, for example 500 volts.Diffusion bonding is particularly applicable to the mounting of VLSI chips of large area to silicon wafers since it is best suited for joining very flat surfaces and results in intimate contact of the elements to be joined, due to diffusion across the barrier therebetween, and the complete absence of voids therebetween. Subsequently to the bonding of the chip 15 to the element 12, wire bond connections, such as 17, are made between aluminium contacts, such as 18, deposited over the wells, such as 4 and part of the surrounding oxide layer -2, and the connection pads, such as 19, on the chip 15. To seal the chip 15 the cover 16, for example of nickel iron alloy, is positioned to extend thereover and its flange 20 is diffusion bonded around its entire periphery to the element 12 via layer 14.This results in an hermetically sealed package which can then be employed without further processing.
The through connection via the doped well or region 4 is isolated by the injunction formed, and the voltage breakdown an capacitance is governed in the usual manner by the relative resistivities of the two regions between which the junction is formed. Typically the silicon wafer 1 (Fig. 1) is 0.5 mm and the well is 0.25 mm square.
With a water resistivity of 102 ohm cm and a well resistivity of 10-2 ohm cm there result capacitance values around 1 pF at 10 volts, which is comparable with the capacitance between pins is a DIL package.
For thermal dissipation purposes the semiconductor wafter 1 (Fig. 2), or 12 (Fig. 3), may be provided with channels 21 etched in its under surface as indicated in Fig. 4. Silicon has remarkably good thermal properties, approximately one third the thermal conductivity of copper. Channels etched in the manner illustrated can increase the surface area available for thermal dissipation purposes. The channels 21 may be closed by means of a member 22 bonded to the oxide 4 on the underside of wafer 1 as shown in order to facilitate forced cooling by water or air circulated through the channels.
Dramatic improvement in heat sinking using such etched channels has already been demonstrated (see IEEE Electron Device Letters Vol. EDL2, No. 5,
May 1981~High Performance Heat Sinking for
VLSI. D. B. Tuckerman and R. F. W. Pease). Using forced water cooling, a power density of 790 W/cm2 was dissipated with a maximum substrate temperature rise of 71 0C above the input water temperature.
Whereas the arrangements so far described have employed highly doped region through connections, other feed through techniques may alternatively be employed, for example dielectricisolated islands in the wafer achieved by employing anistropic silicon etching techniques.
Fig. 5 shows a section through an arrangement including a VLSI chip 23 diffusion bonded via a thin glass layer 33 to a < 110 > silicon wafer 24 having two dielectric-isolated islands 25 and 26, the latter providing electrical connection between metallisation 27 on the underside of wafer 24 and metallisation 28 on the chip 23 via a wire bond 29 and an aluminium film 30. A cover 31 is diffusion bonded to wafer 24 in a manner similar to that described for Fig. 3.
The process steps for manufacturing the isolated islands 25 and 26 basically comprises forming a silicon etch resist layer for example of over the entire surface of the water 24; masking and etching the etch resist layer in order to open annular, square frame or rectangular frame, for example, windows in the etch resist on one side of the wafer, the window shape corresponding to the required island boundary shape; anisotropically etching the silicon thus exposed for a time compatible with etching approximately threequarter of the way through the wafer to provide moat-like apertures therein; removing the etch resist; filling the moats or holes thus etched in the silicon with silicon dioxide 34; lapping the underside of the wafer 24 until the deposited silicon dioxide is exposed thereat; and providing appropriate portions of the lapped underside of the wafer 24, and appropriate portions of its upperside, with a silicon dioxide layer 32.
The isolated island technique for providing discrete electrical connections between opposite faces of a wafer is described above in terms of bonding a VLSI chip to the wafer, alternatively, however, the VLSI device may be formed integrally with the wafer as described with reference to Fig. 2.
Claims (31)
1. An integrated circuit package including a semiconductor wafer having a first surface at which integrated circuit device components are arranged, a second surface and at least one discrete electrical connection extending through the wafer between the first and second surfaces.
2. An integrated circuit package as claimed in claim 1 , wherein the integrated circuit device components are disposed in the wafer and have electrical terminal regions accessible at the first surface.
3. An integrated circuit package as claimed in claim 2, wherein at least one electrical terminal region is electrically connected to a respective discrete electrical connection via a respective electrically conductive member disposed on the first surface.
4. An integrated circuit package as claimed in claim 2 or claim 3, wherein the first surface, and any members dispersed thereon, is covered by a passivating layer.
5. An integrated circuit package as claimed in claim 1 , wherein the integrated circuit device components are disposed in a separate semiconductor element, which element is bonded to the first surface of the semiconductor wafer.
6. An integrated circuit package as claimed in claim 5, wherein the semiconductor element is diffusion bonded to the semiconductor wafer.
7. An integrated circuit package as claimed in claim 5 or claim 6, wherein at least one electrical terminal region of the semiconductor element is electrically connected to a respective discrete electrical connection via a wire bond connection
8. An integrated circuit package as claimed in any one of claims 5 to 7 including a cover bonded to the first surface and encapsulating the semiconductor element and any electrical connections at the first surface between the semiconductor element and the discrete electrical connections.
9. An integrated circuit package as claimed in any one of the preceding claims including cooling channels extending into the semiconductor wafers from the second surface.
10. An integrated circuit package as claimed in any one of the preceding claims, wherein the at least one discrete electrical connection is comprised by a highly doped region of the opposite conductivity type to that of the semiconductor wafer.
11. An integrated circuit package as claimed in claim 10, wherein the highly doped region comprises a well diffused into the wafer from the first surface and accessible from the second surface via an aperture etched into the semiconductor wafer from the second surface.
12. An integrated circuit package as claimed in claim 1 wherein the walls of the aperture are highly doped and of the same conductivity type as the well, the highly doped walls and the well being contiguous.
13. An integrated circuit package as claimed in claim 12, including external contact metallisation for the at least one discrete electrical connection disposed on an insulating layer surrounding the aperture at the second surface, which external contact metallisation extends into the aperture and contacts the highly doped walls thereof.
14. An integrated circuit package as claimed in any one of claims 10 to 13, wherein the semiconductor wafer is comprised by n-type silicon and the highly doped region is comprised by boron diffusion.
15. An integrated circuit package as claimed in any one of claims 1 to 9, wherein the at least one discrete electrical connection is comprised by a conductive island extending through the wafer between the first and second surfaces and electrically isolated from the surrounding wafer.
16. An integrated circuit package as claimed in claim 15, wherein the semiconductor wafer is comprised of silicon and the or each conductive island therethrough is insulated therefrom by silicon dioxide.
17. An integrated circuit packaging method including the steps of providing integrated circuit device components at a first surface of a semiconductor wafer and providing at least one discrete electrical connection extending through the wafer between the first surface and a second surface thereof.
18. A method as claimed in claim 17, wherein the at least one discrete electrical connection is provided in the wafer before the provision of the integrated circuit device components.
19. A method as claimed in claim 17 or 18, wherein the at least obe electrical connection is provided by highly doping a well region of the wafer by diffusion of dopant into the first surface, the well region being of the opposite conductivity type to the semiconductor wafer, and etching an aperture into the wafer from the second surface and in alignment with the well region whereby to expose the well region at the second surface.
20. A method as claimed in claim 19, including the step of diffusing dopant of the same conductivity as that employed to provide the well region into walls of the aperture.
21. A method as claimed in claim 20, including the step of providing metallisation in contact with the doped aperture wall and on an insulating layer at the second surrface.
22. A method as claimed in claim 17 or 18, wherein the at least one electrical connection is provided by forming a conductive island, extending between the first and second surfaces, which is electrically isolated from the surrounding wafer.
23. A method as claimed in claim 22, including the steps of etching part-way through the wafer, whereby to separate an island region therefrom by a moat-like aperture, and lapping the unetched surface of the wafer until the insulating material deposited on the moat-like aperture is exposed.
24. A method as claimed in claim 23, wherein the wafer is of silicon and the insulating material is of silicon dioxide.
25. A method as claimed in any one of claims 17 to 24, wherein the integrated circuit device components are diposed in a separate semiconductor element, and including the step of bonding the element to the first surface of the semiconductor wafer.
26. A method as claimed in claim 25, wherein the bonding comprises diffusion bonding.
27. A method as claimed in claim 25 or claim 26, including the step of electrically connecting the integrated circuit device components terminals to respective discrete.electrical connections and bonding a cover to the first surface whereby to encapsulate the semiconductor element and the electrical connections between the terminals and the discrete electrical connections.
28. A method as claimed any one of claims 17 to 24, including the step of forming the integrated circuit device components in the wafer whereby the components terminals are accessible at the first surface, electrically connecting the terminals to the discrete electrical connections and covering the first surface, and any member disposed thereon, with a passivating layer.
29. A method as claimed in any one of claims 17 to 28, including the step of etching cooling channels into the semiconductor wafer from the second surface.
30. An integrated circuit package substantially as herein described with reference to and as illustrated in Figs. 1 and 2, Figs. 1 and 3, Fig. 5, with or without reference to Fig. 4.
31. An integrated circuit packaging method substantially as herein described with reference to
Figs. 1 and 2, Figs. 1 and 3, or Fig. 5, with or without reference to Fig. 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08305761A GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08305761A GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8305761D0 GB8305761D0 (en) | 1983-04-07 |
| GB2136203A true GB2136203A (en) | 1984-09-12 |
| GB2136203B GB2136203B (en) | 1986-10-15 |
Family
ID=10538872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08305761A Expired GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2136203B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2160707A (en) * | 1984-05-14 | 1985-12-24 | Gigabit Logic Inc | Integrated circuit package |
| EP0171662A2 (en) * | 1984-08-13 | 1986-02-19 | International Business Machines Corporation | Method of fabricating a chip interposer |
| EP0335783A1 (en) * | 1988-03-30 | 1989-10-04 | Siemens Aktiengesellschaft | Casing for an electronic circuit |
| US5051811A (en) * | 1987-08-31 | 1991-09-24 | Texas Instruments Incorporated | Solder or brazing barrier |
| GB2221344B (en) * | 1988-07-01 | 1992-12-23 | Mitsubishi Electric Corp | Semiconductor device and production method therefor |
| EP0628999A1 (en) * | 1993-06-02 | 1994-12-14 | Philips Patentverwaltung GmbH | Sealed feedthrough for a thickfilm ceramic substrate and method of making the same |
| WO2004061973A1 (en) * | 2003-01-02 | 2004-07-22 | Cree, Inc. | Group iii nitride based flip-chip integrated circuit and method for fabricating |
| EP1962344A1 (en) * | 2007-02-25 | 2008-08-27 | Rohm and Haas Electronic Materials LLC | Electronic device packages and methods of formation |
| DE10229711B4 (en) * | 2002-07-02 | 2009-09-03 | Curamik Electronics Gmbh | Semiconductor module with microcooler |
| US8993450B2 (en) | 2003-09-15 | 2015-03-31 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
| US10319654B1 (en) | 2017-12-01 | 2019-06-11 | Cubic Corporation | Integrated chip scale packages |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1111438A (en) * | 1964-12-28 | 1968-04-24 | Ibm | Electrical connection through a body of semiconductor material |
| GB1130711A (en) * | 1965-01-27 | 1968-10-16 | Texas Instruments Inc | Electrical interconnections |
| GB1254795A (en) * | 1968-07-05 | 1971-11-24 | Ibm | Electrical connector assembly |
| GB1272788A (en) * | 1968-07-05 | 1972-05-03 | Honeywell Inf Systems | Improvements in and relating to a semi-conductor wafer for integrated circuits and a method of forming the wafer |
| GB1493814A (en) * | 1973-10-30 | 1977-11-30 | Gen Electric | Semiconductor devices |
-
1983
- 1983-03-02 GB GB08305761A patent/GB2136203B/en not_active Expired
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1111438A (en) * | 1964-12-28 | 1968-04-24 | Ibm | Electrical connection through a body of semiconductor material |
| GB1130711A (en) * | 1965-01-27 | 1968-10-16 | Texas Instruments Inc | Electrical interconnections |
| GB1254795A (en) * | 1968-07-05 | 1971-11-24 | Ibm | Electrical connector assembly |
| GB1272788A (en) * | 1968-07-05 | 1972-05-03 | Honeywell Inf Systems | Improvements in and relating to a semi-conductor wafer for integrated circuits and a method of forming the wafer |
| GB1493814A (en) * | 1973-10-30 | 1977-11-30 | Gen Electric | Semiconductor devices |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2160707A (en) * | 1984-05-14 | 1985-12-24 | Gigabit Logic Inc | Integrated circuit package |
| EP0171662A2 (en) * | 1984-08-13 | 1986-02-19 | International Business Machines Corporation | Method of fabricating a chip interposer |
| EP0171662A3 (en) * | 1984-08-13 | 1987-01-14 | International Business Machines Corporation | Method of fabricating a chip interposer |
| US5051811A (en) * | 1987-08-31 | 1991-09-24 | Texas Instruments Incorporated | Solder or brazing barrier |
| EP0335783A1 (en) * | 1988-03-30 | 1989-10-04 | Siemens Aktiengesellschaft | Casing for an electronic circuit |
| FR2629665A1 (en) * | 1988-03-30 | 1989-10-06 | Bendix Electronics Sa | HOUSING FOR ELECTRONIC CIRCUIT |
| US4931908A (en) * | 1988-03-30 | 1990-06-05 | Siemens Aktiengesellschaft | Housing for an electronic circuit |
| GB2221344B (en) * | 1988-07-01 | 1992-12-23 | Mitsubishi Electric Corp | Semiconductor device and production method therefor |
| US5324981A (en) * | 1988-07-01 | 1994-06-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor device with contact in groove |
| US5434094A (en) * | 1988-07-01 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a field effect transistor |
| EP0628999A1 (en) * | 1993-06-02 | 1994-12-14 | Philips Patentverwaltung GmbH | Sealed feedthrough for a thickfilm ceramic substrate and method of making the same |
| DE10229711B4 (en) * | 2002-07-02 | 2009-09-03 | Curamik Electronics Gmbh | Semiconductor module with microcooler |
| US8803313B2 (en) | 2003-01-02 | 2014-08-12 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| WO2004061973A1 (en) * | 2003-01-02 | 2004-07-22 | Cree, Inc. | Group iii nitride based flip-chip integrated circuit and method for fabricating |
| US9226383B2 (en) | 2003-01-02 | 2015-12-29 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| US6825559B2 (en) | 2003-01-02 | 2004-11-30 | Cree, Inc. | Group III nitride based flip-chip intergrated circuit and method for fabricating |
| US7354782B2 (en) | 2003-01-02 | 2008-04-08 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| US7851909B2 (en) | 2003-01-02 | 2010-12-14 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| US8274159B2 (en) | 2003-01-02 | 2012-09-25 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| US8993450B2 (en) | 2003-09-15 | 2015-03-31 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
| US9410799B2 (en) | 2003-09-15 | 2016-08-09 | Nuvotronics, Inc. | Device package and methods for the fabrication and testing thereof |
| US9647420B2 (en) | 2003-09-15 | 2017-05-09 | Nuvotronics, Inc. | Package and methods for the fabrication and testing thereof |
| US9817199B2 (en) | 2003-09-15 | 2017-11-14 | Nuvotronics, Inc | Device package and methods for the fabrication and testing thereof |
| US8203207B2 (en) | 2007-02-25 | 2012-06-19 | Samsung Electronics Co., Ltd. | Electronic device packages and methods of formation |
| TWI387065B (en) * | 2007-02-25 | 2013-02-21 | Samsung Electronics Co Ltd | Electronic device packages and methods of formation |
| US20090256251A1 (en) * | 2007-02-25 | 2009-10-15 | Rohm And Haas Electronic Materials Llc | Electronic device packages and methods of formation |
| EP1962344A1 (en) * | 2007-02-25 | 2008-08-27 | Rohm and Haas Electronic Materials LLC | Electronic device packages and methods of formation |
| US10319654B1 (en) | 2017-12-01 | 2019-06-11 | Cubic Corporation | Integrated chip scale packages |
| US10553511B2 (en) | 2017-12-01 | 2020-02-04 | Cubic Corporation | Integrated chip scale packages |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2136203B (en) | 1986-10-15 |
| GB8305761D0 (en) | 1983-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6124179A (en) | Inverted dielectric isolation process | |
| US5767578A (en) | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation | |
| US7892884B2 (en) | High performance multi-chip flip chip package | |
| US6114768A (en) | Surface mount die by handle replacement | |
| US5757081A (en) | Surface mount and flip chip technology for total integrated circuit isolation | |
| US3903590A (en) | Multiple chip integrated circuits and method of manufacturing the same | |
| JP4308904B2 (en) | Surface mounting and flip chip technology | |
| US20050167801A1 (en) | Structure and method for improved heat conduction for semiconductor devices | |
| US6404048B2 (en) | Heat dissipating microelectronic package | |
| GB2039144A (en) | Semiconductor housing | |
| US6157076A (en) | Hermetic thin pack semiconductor device | |
| GB2150749A (en) | Integrated circuits | |
| GB2136203A (en) | Through-wafer integrated circuit connections | |
| JP4091669B2 (en) | How to make a multichip package | |
| US3878553A (en) | Interdigitated mesa beam lead diode and series array thereof | |
| US7105910B2 (en) | Semiconductor device having SOI construction | |
| US5146310A (en) | Thermally enhanced leadframe | |
| CN111564420B (en) | High-resistance chip with heat dissipation structure and manufacturing method thereof | |
| US5517058A (en) | Semiconductor package and method with vertically extended electrode leads | |
| US3581166A (en) | Gold-aluminum leadout structure of a semiconductor device | |
| EP0244767A2 (en) | Hermetic semiconductor enclosure and process of manufacture | |
| EP3872848A1 (en) | Metal tab for chip assembly | |
| EP4148777A1 (en) | Semiconductor device | |
| EP0662715A1 (en) | Package for parallel subelement semiconductor devices and method | |
| KR930005488B1 (en) | Resin sealed semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |