JPH01184849A - Manufacture of multilayer interconnection - Google Patents
Manufacture of multilayer interconnectionInfo
- Publication number
- JPH01184849A JPH01184849A JP467288A JP467288A JPH01184849A JP H01184849 A JPH01184849 A JP H01184849A JP 467288 A JP467288 A JP 467288A JP 467288 A JP467288 A JP 467288A JP H01184849 A JPH01184849 A JP H01184849A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- interlayer insulating
- conductor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、超ＬＳＩの金属配線技術として期待されてい
る多層配線の製造方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a method for manufacturing multilayer wiring, which is expected to be used as a metal wiring technology for VLSI.
〈従来の技術〉
集積回路の高集積、高密度化に伴って、多層配線技術が
重要となって来ている。しかし層間絶縁層に形成するス
ルーホールの微細化と共に、従来の多層配線技術では、
スルーホール内の配線の膜厚が薄くなり、多層配線の信
頼性が低下するという問題が発生している。<Prior Art> Multilayer wiring technology has become important as integrated circuits become more highly integrated and densely packed. However, with the miniaturization of through holes formed in interlayer insulation layers, conventional multilayer wiring technology
A problem has arisen in that the film thickness of the wiring inside the through hole becomes thinner, and the reliability of the multilayer wiring decreases.
このため、最近第２図［ａｌ乃至（ｃｌに示すように、
半導体基板２１上に第１層の配線２２を形成した後、第
１の層間絶縁膜２８を形成し、更にその上に第２の配線
２４を形成した後、第２の眉間絶縁膜２５を形成し、次
にこれらの層間絶縁膜２３゜２５にそれぞれ第１層及び
第２層の配線２２．２４に通じるスルーホール２６．２
７を開けた後、スルーホール２６．２７内にタングステ
ン２８．２８を選択的に形成し、更にその後に第３の配
線２９を形成する方法が提案されている。For this reason, recently, as shown in Fig. 2 [al to (cl),
After forming the first layer of wiring 22 on the semiconductor substrate 21, forming the first interlayer insulating film 28, and further forming the second wiring 24 thereon, forming the second glabellar insulation film 25. Then, through holes 26.2 are formed in these interlayer insulating films 23 and 25, respectively, leading to the wirings 22 and 24 of the first and second layers.
A method has been proposed in which after opening the through holes 26, 27, tungsten 28, 28 is selectively formed in the through holes 26, 27, and then the third wiring 29 is formed.
〈発明が解決しようとする問題点〉
しかしながら、上記した従来の方法では、３層以上の多
層配線構造において、深さの異なるスルーホールを督す
る場合、スルーホールの深さの違いがその中に導体を埋
め込む工程である選択成長後の平坦性に反映され、深い
スルーホール２６で第３層の配線２９の被覆特性が低下
し、多層配線の信頼性が低下するという問題が発生して
いた。<Problems to be Solved by the Invention> However, in the conventional method described above, when managing through holes of different depths in a multilayer wiring structure of three or more layers, the difference in the depth of the through holes is This is reflected in the flatness after selective growth, which is the process of embedding a conductor, and the covering characteristics of the third layer wiring 29 deteriorate in the deep through hole 26, resulting in a problem that the reliability of the multilayer wiring deteriorates.
本発明は上記の点に鑑みて創案され念ものであり、深さ
の異なるスルーホールに導体材料を選択的かつ平坦に成
長させ、多層配線の信頼性の向上を図り得る新規な多層
配線の製造方法を提供することを目的としている。The present invention has been devised in view of the above points, and is a novel method for producing multilayer interconnections that can improve the reliability of multilayer interconnections by selectively and flatly growing conductor material in through holes of different depths. The purpose is to provide a method.
く問題点を解決するための手段〉
上記の目的を達成するため、本発明の多層配線の製造方
法は、半導体基板上に第１層の導体配線を形成する工程
と、この第１層の導体配線上に第１の層間絶縁膜を介し
て第２層の導体配線を形成する工程と、この第２層の導
体配線上に第２の層間絶縁膜を形成する工程と、上記の
第２の層間絶縁膜及び第１の層間絶縁膜にそれぞれ上記
の第１層及び第２層の導体配線に通じる第１及び第２の
スルーホールを形成する工程と、この第１及び第２のス
ルーホールに選択成長により導体を埋め込む工程と、上
記の第２の層間絶縁膜上に上記の第１−及び第２のスル
ーホールに埋め込まれた導体に接続される第３の導体配
線を形成する工程と、を含んでなり、上記の第１層及び
第２層の導体配線にそれぞれ異なる種類の不純物イオン
を注入するようになしており、特に第１層の導体配線及
び第２層の導体配線にそれぞれ異種の不純物イオンを注
入することによって、例えばスルーホールに埋め込むタ
ングステン等の導体材料の選択成長速度を制御し、深さ
の異なるスルーホールにも選択的かつ平坦にタングステ
ン等の導体材料を成長し、多層配線の信頼性を向上させ
るようになしている。Means for Solving the Problems In order to achieve the above object, the method for manufacturing a multilayer wiring of the present invention includes a step of forming a first layer of conductor wiring on a semiconductor substrate, and a step of forming a first layer of conductor wiring on a semiconductor substrate. a step of forming a second layer of conductive wiring on the wiring via a first interlayer insulating film; a step of forming a second interlayer insulating film on the second layer of conductive wiring; forming first and second through holes in the interlayer insulating film and the first interlayer insulating film that communicate with the conductor wiring in the first and second layers, respectively; a step of embedding a conductor by selective growth; a step of forming a third conductor wiring on the second interlayer insulating film to be connected to the conductor embedded in the first and second through holes; In this method, different types of impurity ions are implanted into the first layer and second layer conductor wiring, and in particular, different types of impurity ions are implanted into the first layer conductor wiring and the second layer conductor wiring. By implanting impurity ions of This is intended to improve the reliability of wiring.
く作 用〉
例えば、本発明の実施例において用いるタングステンの
選択成長では、下地材料への不純物イオン注入の不純物
種１表面濃度等により、タングステンの成長速度が異な
る。例えばＷＳ（ｘに不純物イオンを注入しない場合に
比へ、 Ｂｔ？注入エネルギー４０ｋｅＶで３ Ｘ １
０ ” ａｓ−”注入した場合には、５０％程度成長速
度が増大する。一方３１ｐ＋を１００ ｋｅＶで５ Ｘ
１０ ”ｆｉ−”注入した場合には、１０％程度成長
速度が低下する。For example, in the selective growth of tungsten used in the embodiments of the present invention, the growth rate of tungsten differs depending on the surface concentration of the impurity species 1 in the impurity ion implantation into the underlying material. For example, when no impurity ions are implanted into WS (
When 0 "as-" is implanted, the growth rate increases by about 50%. On the other hand, 31p+ at 100 keV 5X
When 10 "fi-" is implanted, the growth rate decreases by about 10%.
したがって、各層の導体配線に種類の異なる不純物イオ
ンを注入することにより、コンタクト用のスルーホール
の深さに限定されることなく、スルーホールにタングス
テン等の導体材料を選択的かつ平坦に成長させることが
出来、その結果、多層配線の信頼性が向上する。Therefore, by implanting different types of impurity ions into the conductor wiring in each layer, it is possible to grow conductive materials such as tungsten selectively and flatly in the through holes without being limited to the depth of the through holes for contacts. As a result, the reliability of multilayer wiring is improved.
〈実施例〉
以下、図面を参照して本発明の一実施例全詳細に説明す
る。<Embodiment> Hereinafter, an embodiment of the present invention will be described in full detail with reference to the drawings.
第１図［ａｌ乃至（ｉｌは各々本発明に係る多層配線の
製造方法の一実施例を示す工程図である。FIG. 1 [al to (il) are process diagrams each showing an embodiment of the method for manufacturing a multilayer interconnection according to the present invention.
まず、第１図（ａＪに示すように半導体基板１にスパッ
タ法によりＷＳｉｘ’ｒ０．５μ霞厚で被着し、第１層
ＷＳｉｘ配線２を形成する。次に第１図［ｂｌに示すよ
うに上記の第１層Ｗ Ｓ ｉｘ配線２の全面に、イオン
注入法により Ｂ １５０ｋｅＶで３ Ｘ １０ ”
ｍ−”注入して不純物イオン注入層（Ｂ”）ｌを形成
する。次に第１図（ｄに示すようにＣＶＤ法等の慣用手
法により層間絶縁膜４を０．８μｍ被着した後、第１図
（ｄｌに示すようにスパッタ法によりＷ Ｓ ｉｘを０
．５μ町、厚：！７ｒｉ被着して第２層ＷＳｉｘ配線５
″ｆ：形成する。First, as shown in FIG. 1 (aJ), WSix'r is deposited to a thickness of 0.5 μm on a semiconductor substrate 1 by sputtering to form a first layer WSix wiring 2.Next, as shown in FIG. Then, the entire surface of the first layer WSix wiring 2 was injected with 3×10” B at 150 keV by ion implantation.
m-'' is implanted to form an impurity ion implantation layer (B'')l. Next, as shown in FIG. 1 (d), an interlayer insulating film 4 of 0.8 μm is deposited by a conventional method such as CVD, and then W S ix is reduced to 0 by sputtering as shown in FIG. 1 (dl).
．． 5μ town, thickness:! 7ri deposited and second layer WSix wiring 5
″f: Form.
次に第１図ｆｅｌに示すように上記の第２層Ｗ Ｓ ｔ
ｘ配線５の全面に、イオン注入法により Ｐ、全１０
０ ｋｅＶで５ Ｘ １０１６ｅａ−”注入して、不純
物イオン注入層（Ｐ ）６を形成する。次に第１図げ）
に示すようにＣＶＤ法等の慣用手法により層間絶縁膜７
を１．２μｍ被着した後、第１図１に示すように、上記
した層間絶縁膜４゜７の所定の位置に、それぞれ上記し
た第１層及び第２層配線２．５に達する深さの異なるス
ルーホール８．９に形成する。その後、第１図ｆｈ）に
示すようにそれぞれ深さの異なるスルーホール８．９に
、例えばＷ Ｆ ｓのＨ２還元法によるタングステンの
選択ＣＶＤ法により、タングステン１０を選択的に埋込
み形成する。その後第１図Ｇ）に示すように第３層Ａ１
−５ｉ配線１１を形成する。Next, as shown in FIG. 1, the above second layer W S t
P, total 10
5 x 1016ea-'' is implanted at 0 keV to form an impurity ion implantation layer (P) 6. Next, in Figure 1)
As shown in FIG.
After depositing 1.2 μm of the above-mentioned interlayer insulating film 4°7, as shown in FIG. Through holes 8 and 9 are formed with different numbers. Thereafter, as shown in FIG. 1 (fh), tungsten 10 is selectively embedded in the through holes 8.9 having different depths, for example, by selective CVD of tungsten using the H2 reduction method of W F s. Then, as shown in Figure 1G), the third layer A1
-5i wiring 11 is formed.
以上のように、各層の導体配線に種類の異なる不純物イ
オン全注入することにより、深さの異なるスルーホール
に、タングステンを選択的かつ平坦に成長させることが
出来、多層配線の信頼性が向上する。As described above, by fully implanting different types of impurity ions into the conductor wiring in each layer, tungsten can be grown selectively and flatly in through holes of different depths, improving the reliability of multilayer wiring. .
なお、本発明は上記した実施例に限定されるものではな
く、その主旨を逸脱しない範囲で種々の変形で実施する
ことが出来、例えば各層の導体配線に注入する不純物イ
オン種、注入量、注入エネルギーあるいは注入の有無１
層間絶縁膜の膜厚は適宜決定することが出来ることは言
うまでもない。It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the spirit thereof. Energy or injection presence 1
It goes without saying that the thickness of the interlayer insulating film can be determined as appropriate.
また４層以上の多層配線にも適用し得ることは言うまで
もない。更に導体材料としてもＷ Ｓ ｒ ｘ配線に代
えてＭ ＯＳ ｓ ｘ 、ＡノーＳｉなどの他の導体材
料を用いても良いことは言うまでもない。It goes without saying that the present invention can also be applied to multilayer wiring of four or more layers. Furthermore, it goes without saying that other conductive materials such as MOS s x and A-no-Si may be used instead of the W S r x wiring.
〈発明の効果〉
以上のように本発明によれば、深さの異なるスルーホー
ル内にタングステン等の導体材料を選択的かつ平坦に成
長させることが出来、その結果、多層配線の信頼性？著
しく向上させることが出来る。<Effects of the Invention> As described above, according to the present invention, conductor materials such as tungsten can be selectively and flatly grown in through holes of different depths, and as a result, the reliability of multilayer wiring can be improved. It can be significantly improved.
第１図（ａｌ乃至ｆｉｌはそれぞれ本発明に係る多層配
線の製造方法の一実施例の工程を説明するための図、第
２図（ａｌ乃至（ｃｌはそれぞれ従来の多層配線の製造
方法の工程を説明するための図である。
１・・・半導体基板、２・・・第１層Ｗ Ｓ ｉｘ配線
、８・・・不純物イオン注入層（Ｂ＋）、４・・・層間
絶縁膜Ｉ、５・・・第２層ＷＳｉｘ配線、６・・・不純
物イオン注入層（Ｐ＋）、７・・・層間絶縁膜■、８．
９・・・スルーホール、１０・・・選択成長タングステ
ン（導体）、１１・・・第３層ＡノーＳｉ配線。FIG. 1 (al to fil are diagrams for explaining the steps of an embodiment of the multilayer wiring manufacturing method according to the present invention, respectively, and FIG. 2 (al to (cl) are diagrams for explaining the steps of the conventional multilayer wiring manufacturing method, respectively. 1... Semiconductor substrate, 2... First layer W S ix wiring, 8... Impurity ion implantation layer (B+), 4... Interlayer insulating film I, 5 . . . second layer WSix wiring, 6 . . . impurity ion implantation layer (P+), 7 . . . interlayer insulating film ■, 8.
9...Through hole, 10...Selectively grown tungsten (conductor), 11...3rd layer A no-Si wiring.
Claims (1)
、 該第１層の導体配線上に第１の層間絶縁膜を介して第２
層の導体配線を形成する工程と、該第２層の導体配線上
に第２の層間絶縁膜を形成する工程と、 上記第２の層間絶縁膜及び第１の層間絶縁膜にそれぞれ
上記第１層及び第２層の導体配線に通じる第１及び第２
のスルーホールを形成する工程と、 該第１及び第２のスルーホールに選択成長により導体を
埋め込む工程と、 上記第２の層間絶縁膜上に上記第１及び第２のスルーホ
ールに埋め込まれた導体に接続される第３層の導体配線
を形成する工程と、 を含んでなり、 上記第１層及び第２層の導体配線にそれぞれ異なる種類
の不純物イオンを注入してなることを特徴とする多層配
線の製造方法。 ２、前記第１及び第２のスルーホールに選択成長により
埋め込まれる導体材料をタングステンとなした第１項記
載の多層配線の製造方法。 ３、前記第１層の導体配線に注入する不純物イオンがボ
ロンであり、前記第２層の導体配線に注入する不純物イ
オンがリンである第１項記載の多層配線の製造方法。[Claims] 1. A step of forming a first layer of conductive wiring on a semiconductor substrate, and forming a second layer of conductive wiring on the first layer of conductive wiring via a first interlayer insulating film.
a step of forming a conductor wiring layer, a step of forming a second interlayer insulating film on the conductor wiring of the second layer, and a step of forming the first interlayer insulating film on the second interlayer insulating film and the first interlayer insulating film, respectively. The first and second layers lead to the conductor wiring of the layer and the second layer.
a step of embedding a conductor in the first and second through holes by selective growth; and a step of embedding a conductor in the first and second through holes on the second interlayer insulating film. forming a third layer of conductor wiring connected to the conductor, and implanting different types of impurity ions into the first and second layer conductor wirings, respectively. A method for manufacturing multilayer wiring. 2. The method for manufacturing a multilayer wiring according to item 1, wherein the conductive material buried in the first and second through holes by selective growth is tungsten. 3. The method for manufacturing a multilayer wiring according to item 1, wherein the impurity ions implanted into the first layer conductor wiring are boron, and the impurity ions implanted into the second layer conductor wiring are phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004672A JPH0618196B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004672A JPH0618196B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01184849A true JPH01184849A (en) | 1989-07-24 |
| JPH0618196B2 JPH0618196B2 (en) | 1994-03-09 |
Family
ID=11590396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63004672A Expired - Lifetime JPH0618196B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618196B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH043934A (en) * | 1990-04-20 | 1992-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| DE4021516A1 (en) * | 1990-07-06 | 1992-01-16 | Samsung Electronics Co Ltd | Differential tungsten growth by CVD - by controlling reaction gas ratio for improved step coverage e.g. in DRAM mfr. |
| JPH0425075A (en) * | 1990-05-16 | 1992-01-28 | Takehide Shirato | Semiconductor device |
| US5671674A (en) * | 1994-11-16 | 1997-09-30 | Kabushiki Kaisha Tokyo Kikai Seisakusho | Printing plate support device and printing plate removal mounting apparatus as well as methods of operating the same |
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294870B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US7880304B2 (en) * | 2004-10-12 | 2011-02-01 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
-
1988
- 1988-01-14 JP JP63004672A patent/JPH0618196B2/en not_active Expired - Lifetime
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH043934A (en) * | 1990-04-20 | 1992-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0425075A (en) * | 1990-05-16 | 1992-01-28 | Takehide Shirato | Semiconductor device |
| DE4021516A1 (en) * | 1990-07-06 | 1992-01-16 | Samsung Electronics Co Ltd | Differential tungsten growth by CVD - by controlling reaction gas ratio for improved step coverage e.g. in DRAM mfr. |
| US5671674A (en) * | 1994-11-16 | 1997-09-30 | Kabushiki Kaisha Tokyo Kikai Seisakusho | Printing plate support device and printing plate removal mounting apparatus as well as methods of operating the same |
| US5715751A (en) * | 1994-11-16 | 1998-02-10 | Kabushiki Kaisha Tokyo Kikai Seisakusho | Printing plate support device and printing plate removably mounting apparatus as well as methods of operating the same |
| US7372155B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7384864B2 (en) | 1998-12-21 | 2008-06-10 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7329954B2 (en) | 1998-12-21 | 2008-02-12 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7368376B2 (en) | 1998-12-21 | 2008-05-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7372085B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7294870B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US7420276B2 (en) | 1998-12-21 | 2008-09-02 | Megica Corporation | Post passivation structure for semiconductor chip or wafer |
| US7422976B2 (en) | 1998-12-21 | 2008-09-09 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US8350386B2 (en) * | 1998-12-21 | 2013-01-08 | Megica Corporation | Top layers of metal for high performance IC's |
| US8022546B2 (en) * | 1998-12-21 | 2011-09-20 | Megica Corporation | Top layers of metal for high performance IC's |
| US8035227B2 (en) * | 1998-12-21 | 2011-10-11 | Megica Corporation | Top layers of metal for high performance IC's |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
| US7880304B2 (en) * | 2004-10-12 | 2011-02-01 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0618196B2 (en) | 1994-03-09 |
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