JPH01184848A - Manufacture of multilayer interconnection - Google Patents
Manufacture of multilayer interconnectionInfo
- Publication number
- JPH01184848A JPH01184848A JP467188A JP467188A JPH01184848A JP H01184848 A JPH01184848 A JP H01184848A JP 467188 A JP467188 A JP 467188A JP 467188 A JP467188 A JP 467188A JP H01184848 A JPH01184848 A JP H01184848A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- conductor
- holes
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010937 tungsten Substances 0.000 claims abstract description 19
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 14
- 230000003287 optical effect Effects 0.000 claims description 8
- 229910018125 Al-Si Inorganic materials 0.000 abstract 3
- 229910018520 Al—Si Inorganic materials 0.000 abstract 3
- 238000001579 optical reflectometry Methods 0.000 abstract 1
- 229910016006 MoSi Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 2
- -1 WSix Chemical compound 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、超ＬＳＩの金属配線技術として期待されてい
る多層配線の製造方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a method for manufacturing multilayer wiring, which is expected to be used as a metal wiring technology for VLSI.
〈従来の技術〉
集積回路の高集積、高密度化に伴って、多層配線技術が
重要となって来ている。しかし層間絶縁層に形成するス
ルーホールの微細化と共に、従来の多層配線技術では、
スルーホール内の配線の膜厚が薄くなシ、多層配線の信
頼性が低下するという問題が発生している。<Prior Art> Multilayer wiring technology has become important as integrated circuits become more highly integrated and densely packed. However, with the miniaturization of through holes formed in interlayer insulation layers, conventional multilayer wiring technology
A problem has arisen in that the reliability of multilayer wiring is reduced because the thickness of the wiring inside the through hole is thin.
このため、最近第２図（ａ）乃至（Ｃ）に示すように、
半導体基板２１上に第１層の配線２２を形成した後、第
１の層間絶縁膜２３を形成し、更にその上に第２層の配
線２４を形成した後、第２の層間絶縁膜２５を形成し、
次にこれらの層間絶縁膜２３゜２５にそれぞれ第１層及
び第２層の配線２２．２４に通じるスルーホール２６．
２７を開けた後、スルーホール２６．２７内にタングス
テン２８．２８を選択的に形成し、更にその後に第３層
の配線２９を形成する方法が提案されている。For this reason, recently, as shown in Figures 2(a) to (C),
After forming the first layer wiring 22 on the semiconductor substrate 21, forming the first interlayer insulating film 23, and further forming the second layer wiring 24 thereon, the second interlayer insulating film 25 is formed. form,
Next, through holes 26.26 are formed in these interlayer insulating films 23.25, leading to the first and second layer interconnections 22.24, respectively.
A method has been proposed in which after opening the through holes 27, tungsten 28, 28 is selectively formed in the through holes 26, 27, and then the third layer wiring 29 is formed.
〈発明が解決しようとする問題点〉
しかしながら、上記した従来の方法では、３層以上の多
層配線溝造において、深さの異なるスルーホールを有す
る場合、スルーホールの深さの違いがその中に導体を埋
め込む工程である選択成長後の平坦性に反映され、深い
スルーホール２６で第３層の配線２９の被覆特性が底下
し、多層配線の信頼性が低下するという問題が発生して
いた。<Problems to be Solved by the Invention> However, in the above-mentioned conventional method, when there are through holes of different depths in a multilayer wiring groove structure of three or more layers, the difference in the depth of the through holes is This is reflected in the flatness after selective growth, which is the process of embedding a conductor, and the coating characteristics of the third layer wiring 29 bottom out in the deep through holes 26, resulting in a problem that the reliability of the multilayer wiring deteriorates.
本発明は上記の点に濫みて創案されたものであり、異さ
の異なるスルーホールに導体材料を選択的かつ平坦に形
成し、多層配線の信頼性の向上を図シ得る新規な多層配
線の製造方法を提供することを目的としている。The present invention has been devised in view of the above-mentioned points, and provides a novel multilayer interconnection structure in which conductive materials are selectively and flatly formed in through-holes of different shapes, thereby improving the reliability of multilayer interconnections. The purpose is to provide a manufacturing method.
く問題点を解決するための手段〉
上記の目的を達成するため、本発明の多層配線の製造方
法は、半導体基板上に第１層の導体配線を形成する工程
と、この第１層の導体配線上に第１の層間絶縁膜を介し
て第２層の導体配線を形成する工程と、この第２層の導
体配線上に第２の眉間絶縁膜を形成する工程と、上記の
第２の層間絶縁膜及び第１の層間絶縁膜にそれぞれ上記
の第１層及び第２層の導体配線に通じる第１及び第２の
スルーホールを形成する工程と、この第１及び第２のス
ルーホーｐに選択成長により導体を埋め込む工程と、上
記の第２の層間絶縁膜上に上記の第１及び第２のスルー
ホールに埋め込まれた導体に接続される第３層の導体配
線を形成する工程とを含んでなり、上記の第１層及び第
２層の導体配線をそれぞれ光学的に射率の異なる導体材
料で形成するようになしており、特に第１層の導体配線
に第２層の導体配線に用いた導体材料の光学的反射率よ
フも低い材料を用いることによフ、例えばタングステン
等のスルーホールに埋め込む導体材料の選択成長速度を
制御し、深さの異なるスルーホールにも選択的かつ平坦
にタングステン等の導体材料を成長し、多層配線の信頼
性を向上させるようになしている。Means for Solving the Problems In order to achieve the above object, the method for manufacturing a multilayer wiring of the present invention includes a step of forming a first layer of conductor wiring on a semiconductor substrate, and a step of forming a first layer of conductor wiring on a semiconductor substrate. A step of forming a second layer of conductive wiring on the wiring via a first interlayer insulating film, a step of forming a second glabella insulating film on the second layer of conductive wiring, and the above-mentioned second forming first and second through holes in the interlayer insulating film and the first interlayer insulating film that lead to the conductor wiring in the first and second layers, respectively; a step of embedding a conductor by selective growth; and a step of forming a third layer of conductor wiring on the second interlayer insulating film to be connected to the conductor embedded in the first and second through holes. The conductor wiring in the first layer and the second layer are formed of conductive materials having optically different emissivities, and in particular, the conductor wiring in the first layer and the conductor wiring in the second layer are formed of conductive materials having optically different emissivities. By using a material with an optical reflectance lower than that of the conductive material used in the process, the selective growth rate of the conductive material, such as tungsten, to be buried in the through hole can be controlled, and the growth rate can be controlled selectively even in through holes of different depths. In addition, a conductive material such as tungsten is grown flatly to improve the reliability of multilayer wiring.
く作 用〉
例えば、本発明の実施例において用いるタングステンの
選択成長では、選択性を向上させるため、ウェハに光エ
ネルギービームを短時間照射してタングステンを成長さ
せる方法が採用されている。For example, in the selective growth of tungsten used in the embodiments of the present invention, in order to improve the selectivity, a method is adopted in which the wafer is irradiated with a light energy beam for a short time to grow tungsten.
この方法では、下地材料の光学的反射率によりウェハの
温度が異なって来るため、タングステンの成長速度が異
なることになる。例えばＷ Ｓ Ｉ ＸとＭｏＳｉｘ上
のタングステンの成長速度の温度依存性は第３図に示す
ようになり、光学的反射率の低いＭｏ５ｉ）（上にタン
グステンを選択成長させた場合、ＷＳｉｘ上にタングス
テンを選択成長させた場合に比べ、Ｍｏ Ｓ ｉ）（の
方が温度が高くなる結果、３０〜４０％の成長速度の増
大がある。In this method, the wafer temperature varies depending on the optical reflectance of the underlying material, resulting in different tungsten growth rates. For example, the temperature dependence of the growth rate of tungsten on WSix and MoSix is shown in Figure 3. As a result of the higher temperature of MoSi), the growth rate increases by 30 to 40% compared to selective growth of MoSi).
また、光学的反射率の低いＷＳｉｘなどのシリサイドに
比べて光学的反射率の高いＡＪ膜等はタングステンの成
長速度が５０％程度低くなる。Furthermore, compared to silicide such as WSix, which has a low optical reflectance, the growth rate of tungsten is about 50% lower in the AJ film, etc., which has a high optical reflectance.
したがって、各層の導体配線に光学的反射率の配線の信
頼性が向上する。Therefore, the reliability of the optical reflectance of the conductor wiring in each layer is improved.
〈実施例〉
以下、図面を参照して本発明の一実施例を詳細に説明す
る。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）乃至（ｇ）は各々本発明に係る多層配線の
製造方法の一実施例の工程説明図である。FIGS. 1(a) to 1(g) are process explanatory diagrams of an embodiment of a method for manufacturing a multilayer wiring according to the present invention.
まず、第１図（ａ）に示すように半導体基板１上だスパ
ッタ法によりＭｏ５ｉ）（を０．５μｍ厚で被着し、第
１層ＭｏＳｉｘ配線２を形成する。次に第１図（ｂ）に
示すようにＣＶＤ法等の慣用手法により層間絶縁膜３を
１．０μｍ被着した後、第１図（Ｃ）に示すようにスパ
ッタ法により１ｇ−５ｉ膜を１．０μｍ厚で被着して第
２層ｋｌ−５ｉ配線４を形成する。次に、更に第１図（
ｄ）に示すようにＣＶＤ法等の慣用手法により層間絶縁
膜５を１．２μｍ厚に被着した後、第１図（ｅ）に示す
ように上記した層間絶縁膜３．５の所定の位置に、それ
ぞれ上記した第１層Ｍｏ５ｉ）（配線２及び第２層Ａ６
−５ｉ配線４に達するスルーホーｉＶ６及び７を形成す
る。その後、第１図（ｆ）に示すようにそれぞれ深さの
異なるスルーホール６及び７に例えばＷ Ｆ ａのＨ２
還元法によるタングステンの選択ＣＶＤ法によ）タング
ステン８を選択的に成長させる。この場合、下地配線２
，４の光学的反射率の相違により深いヌル−ホール６に
おける成膜速度の方が他方より遠くなシ、結果として深
さの異なるスルーホール６．７にタングステン８が平坦
性良く埋込み形成されることになる。First, as shown in FIG. 1(a), Mo5i) is deposited to a thickness of 0.5 μm on a semiconductor substrate 1 by sputtering to form a first layer MoSix wiring 2.Next, as shown in FIG. ), an interlayer insulating film 3 of 1.0 μm is deposited by a conventional method such as CVD, and then a 1g-5i film is deposited with a thickness of 1.0 μm by sputtering as shown in FIG. 1(C). Then, the second layer kl-5i wiring 4 is formed.Next, further as shown in FIG.
After depositing the interlayer insulating film 5 to a thickness of 1.2 μm by a conventional method such as CVD as shown in d), the interlayer insulating film 3.5 is deposited at a predetermined position as shown in FIG. 1(e). , the above-mentioned first layer Mo5i) (wiring 2 and second layer A6)
Through-holes iV6 and 7 reaching the -5i wiring 4 are formed. Thereafter, as shown in FIG. 1(f), for example, H2 of W F a is inserted into the through holes 6 and 7 having different depths.
Selective growth of tungsten (by CVD method) by reduction method Tungsten 8 is selectively grown. In this case, the base wiring 2
, 4, the film formation rate in the deep null hole 6 is farther than that in the other, and as a result, the tungsten 8 is embedded with good flatness in the through holes 6 and 7 having different depths. It turns out.
その後、第１図（ｇ）に示すように第３層Ａｌ−５ｉ配
線９を形成する。Thereafter, a third layer Al-5i wiring 9 is formed as shown in FIG. 1(g).
以上のように、各層の導体配線を指定することにより、
深さの異なるスルーホールにタングステンを選択的かつ
平坦に埋め込み形成することが出来、多層配線の信頼性
が向上する。As mentioned above, by specifying the conductor wiring for each layer,
Tungsten can be selectively and flatly buried in through holes of different depths, improving the reliability of multilayer wiring.
なお、本発明は上記した実施例に限定されるものではな
く、その主旨を逸脱しない範囲で種々の変形で実施する
ことが出来、例えば各層の導体配線の種類及び組合せ、
層間絶縁膜の膜厚等は、その導体材料の光学的反射率に
より適宜決定することが出来ることは言うまでもない。Note that the present invention is not limited to the above-described embodiments, and can be implemented in various modifications without departing from the spirit thereof. For example, the types and combinations of conductor wiring in each layer,
It goes without saying that the thickness of the interlayer insulating film can be appropriately determined depending on the optical reflectance of the conductive material.
また４層以上の多層配線にも適用し得ることは言うまで
もない。It goes without saying that the present invention can also be applied to multilayer wiring of four or more layers.
〈発明の効果〉
以上のように本発明によれば、深さの異なるスルーホー
ル内にタングステン等の導体材料を選択的に、かつ平坦
に埋込み成長することが出来、その結果多層配線の信頼
性を著しく向上させることが出来る。<Effects of the Invention> As described above, according to the present invention, conductive materials such as tungsten can be selectively and evenly grown in through holes of different depths, and as a result, the reliability of multilayer wiring can be improved. can be significantly improved.
第１図（ａ）乃至（ｇ）はそれぞれ本発明に係る多層配
線の製造方法の一実施例の工程を説明するための図、第
２図（ａ）乃至（Ｃ）はそれぞれ従来の方法により製造
される多層配線形成工程を説明するための図、第３図は
ＷＳ ｉ）（＋ ＭｏＳ ｉｘ上のタングステンの成長
速度の温度依存性を示す図である。
１・・・半導体基板、 ２・・・第１層ＭｏＳｉ配線、
３・・・層間絶縁膜１． ４・・・第２層Ａｌ−５ｉ配
線、５・・・層間絶縁膜■、 ６，７・・リルーホール
、８・・・選択成長タングステン（導体）、 ９・・・
第１層ＭｏＳｉ配線。
呂願人 工業技術院長
萬１図
１２図
Ｔ（’ｃ）
萬３図FIGS. 1(a) to (g) are diagrams for explaining the steps of an embodiment of the method for manufacturing a multilayer wiring according to the present invention, and FIGS. FIG. 3 is a diagram illustrating the process of forming multilayer wiring to be manufactured, and is a diagram showing the temperature dependence of the growth rate of tungsten on WS i) (+ MoS ix. 1... Semiconductor substrate, 2.・First layer MoSi wiring,
3... Interlayer insulating film 1. 4... Second layer Al-5i wiring, 5... Interlayer insulating film ■, 6, 7... Relou hole, 8... Selective growth tungsten (conductor), 9...
First layer MoSi wiring. Ro Ganjin Director of the Agency of Industrial Science and Technology 1 Figure 12 Figure T('c) 3 Figures
Claims (1)
、 該第１層の導体配線上に第１の層間絶縁膜を介して第２
層の導体配線を形成する工程と、該第２層の導体配線上
に第２の層間絶縁膜を形成する工程と、 上記第２の層間絶縁膜及び第１の層間絶縁膜にそれぞれ
上記第１層及び第２層の導体配線に通じる第１及び第２
のスルーホールを形成する工程と、 該第１及び第２のスルーホールに選択成長により導体を
埋め込む工程と、 上記第２の層間絶縁膜上に上記第１及び第２のスルーホ
ールに埋め込まれた導体に接続される第３層の導体配線
を形成する工程と、 を含んでなり、 上記第１層及び第２層の導体配線をそれぞれ光学的反射
率の異なる導体材料で形成するようになしたことを特徴
とする多層配線の製造方法。 ２、前記第１及び第２のスルーホールに選択成長により
埋め込まれる導体材料をタングステンとなした第１項記
載の多層配線の製造方法。 ３、前記第１層の導体配線として、前記第２層の導体配
線に用いた導体材料の光学的反射率より低い導体材料を
用いて形成してなる第１項記載の多層配線の製造方法。[Claims] 1. A step of forming a first layer of conductive wiring on a semiconductor substrate, and forming a second layer of conductive wiring on the first layer of conductive wiring via a first interlayer insulating film.
a step of forming a conductor wiring layer, a step of forming a second interlayer insulating film on the conductor wiring of the second layer, and a step of forming the first interlayer insulating film on the second interlayer insulating film and the first interlayer insulating film, respectively. The first and second layers lead to the conductor wiring of the layer and the second layer.
a step of embedding a conductor in the first and second through holes by selective growth; and a step of embedding a conductor in the first and second through holes on the second interlayer insulating film. forming a third layer of conductor wiring to be connected to the conductor, the first layer and the second layer of conductor wiring being formed of conductor materials having different optical reflectances, respectively. A method for manufacturing multilayer wiring, characterized by the following. 2. The method for manufacturing a multilayer wiring according to item 1, wherein the conductive material buried in the first and second through holes by selective growth is tungsten. 3. The method of manufacturing a multilayer wiring according to item 1, wherein the first layer conductor wiring is formed using a conductor material whose optical reflectance is lower than that of the conductor material used for the second layer conductor wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004671A JPH0611045B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004671A JPH0611045B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01184848A true JPH01184848A (en) | 1989-07-24 |
| JPH0611045B2 JPH0611045B2 (en) | 1994-02-09 |
Family
ID=11590368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63004671A Expired - Lifetime JPH0611045B2 (en) | 1988-01-14 | 1988-01-14 | Manufacturing method of multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611045B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
-
1988
- 1988-01-14 JP JP63004671A patent/JPH0611045B2/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7294870B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7329954B2 (en) | 1998-12-21 | 2008-02-12 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7368376B2 (en) | 1998-12-21 | 2008-05-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7372085B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7372155B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7384864B2 (en) | 1998-12-21 | 2008-06-10 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US7420276B2 (en) | 1998-12-21 | 2008-09-02 | Megica Corporation | Post passivation structure for semiconductor chip or wafer |
| US7422976B2 (en) | 1998-12-21 | 2008-09-09 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0611045B2 (en) | 1994-02-09 |
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| EXPY | Cancellation because of completion of term |