JPH01181438A - Manufacture of dielectric-isolation semiconductor substrate - Google Patents
Manufacture of dielectric-isolation semiconductor substrateInfo
- Publication number
- JPH01181438A JPH01181438A JP210388A JP210388A JPH01181438A JP H01181438 A JPH01181438 A JP H01181438A JP 210388 A JP210388 A JP 210388A JP 210388 A JP210388 A JP 210388A JP H01181438 A JPH01181438 A JP H01181438A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- wafer
- silicon wafer
- silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000002955 isolation Methods 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 235000012431 wafers Nutrition 0.000 claims abstract description 121
- 238000000034 method Methods 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 70
- 229910052710 silicon Inorganic materials 0.000 claims description 70
- 239000010703 silicon Substances 0.000 claims description 70
- 238000005530 etching Methods 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 8
- 239000012298 atmosphere Substances 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000005498 polishing Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000008602 contraction Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、２枚のシリコンウェハを熱酸化膜を介して接
着した半導体基板に係わり、特に素子間分離を絶縁体で
行った誘電体分離型半導体基板の製造方法に関する。[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a semiconductor substrate in which two silicon wafers are bonded together via a thermal oxide film, and in particular, the invention relates to a semiconductor substrate in which two silicon wafers are bonded together via a thermal oxide film, and in particular, isolation between elements is achieved using an insulator. The present invention relates to a method for manufacturing a dielectrically isolated semiconductor substrate.
（従来の技術）
従来、半導体装置の素子間分離技術の一つとして、絶縁
体を用いた誘電体分離技術が知られている−この誘電体
分離技術はｐｎ接合分離技術に比べて
■高温動作時においても漏れ電流が少なく、ラッチアッ
プがない。(Prior art) Dielectric isolation technology using an insulator has been known as one of the element isolation technologies for semiconductor devices.This dielectric isolation technology has higher temperature operation than pn junction isolation technology. Leakage current is low and there is no latch-up.
■高耐圧素子を分離する際でも、分離に必要な面積が少
ない。■Even when separating high-voltage elements, the area required for separation is small.
■電圧印加の極性を考慮する必要がない。■There is no need to consider the polarity of voltage application.
■寄生容量が少ない。■Low parasitic capacitance.
等の特徴を持っている。誘電体分離を実現する技術とし
ては、ＳＯ８と呼ばれるサファイヤ基板上にシリコンを
気相成長させる方法、絶縁膜上に堆積した非晶質シリコ
ンを再結晶させる方法、シリコンウェハの直接接着を利
用した方法等が知られている。また、シリコンウェハの
一部をエツチングし酸化膜を形成した後多結晶シリコン
を堆積し、裏側から研磨することで多結晶シリコンで保
持されて島状に分離された単結晶シリコンを得る方法も
知られている。It has the following characteristics. Technologies for achieving dielectric separation include a method of vapor phase growth of silicon on a sapphire substrate called SO8, a method of recrystallizing amorphous silicon deposited on an insulating film, and a method of using direct bonding of silicon wafers. etc. are known. We also know of a method of etching a part of a silicon wafer to form an oxide film, then depositing polycrystalline silicon, and polishing it from the back side to obtain single-crystalline silicon that is held by polycrystalline silicon and separated into islands. It is being
これらのうちで、直接接着法を利用した誘電体分離型半
導体基板の製造は、従来、第４図のようにして行われて
いた。まず、第４図（ａ）に示す如く、シリコンウェハ
４１，４２の少なくとも一方の表面に熱酸化膜４３を形
成し、これらを直接接着して一体化する。その後、第４
図（ｂ）に示す如く、上側のウェハ４１を規定の厚さま
で研磨する。Among these, manufacturing of dielectrically isolated semiconductor substrates using the direct bonding method has conventionally been carried out as shown in FIG. First, as shown in FIG. 4(a), a thermal oxide film 43 is formed on at least one surface of silicon wafers 41 and 42, and these are directly bonded and integrated. Then the fourth
As shown in Figure (b), the upper wafer 41 is polished to a specified thickness.
次いで、第４図（ｃ）に示す如く、素子形成領域を横方
向に分離するためにウェハ４１の表面から熱酸化膜４３
まで素子分離用の溝４５を形成し、その後向図（ｄ）に
示す如く溝４５の側面に酸化膜４６を形成する。最後に
、この溝４５を多結晶シリコン膜４６等により埋め、必
要があれば表面の平坦化を行い、誘電体分離型半導体基
板を得る。Next, as shown in FIG. 4(c), a thermal oxide film 43 is removed from the surface of the wafer 41 in order to horizontally separate the element formation regions.
A groove 45 for element isolation is formed up to the point 45, and an oxide film 46 is formed on the side surface of the groove 45 as shown in the rear view (d). Finally, the trench 45 is filled with a polycrystalline silicon film 46 or the like, and the surface is planarized if necessary to obtain a dielectrically isolated semiconductor substrate.
この直接接着を利用した方法は、厚くて良質の単結晶シ
リコン層を素子を形成する部分として得ることができ、
また多結晶シリコンを厚く堆積する必要がないのでの基
板の反りが比較的少ない等の利点を有する。This method using direct adhesion makes it possible to obtain a thick, high-quality single crystal silicon layer as part of the device.
Further, since there is no need to deposit polycrystalline silicon thickly, there are advantages such as relatively little warping of the substrate.
しかしながら、この種の方法にあっては次のような問題
があった。即ち、直接接着において２枚のウェハは熱処
理によって一体化されるが、熱処理後室温に戻る際にシ
リコンと酸化膜との熱収縮差により両者に応力が発生す
る。シリコンの方が酸化膜よりも熱収縮率が大きいので
、室温においてシリコンには引張り応力が働き縮もうと
している。また、酸化膜には圧縮応力が働き伸びようと
している。However, this type of method has the following problems. That is, in direct bonding, two wafers are integrated by heat treatment, but when the wafers return to room temperature after heat treatment, stress is generated in both due to the difference in thermal contraction between silicon and oxide film. Since silicon has a higher thermal shrinkage rate than an oxide film, tensile stress acts on silicon at room temperature, causing it to shrink. In addition, compressive stress acts on the oxide film, causing it to expand.
第５図は研磨工程まで済んだ基板の断面図で、−点鎖線
は断面上下方向の中心線を示している。FIG. 5 is a sectional view of the substrate after the polishing process, and the dashed-dot line indicates the center line in the vertical direction of the cross section.
この図で明らかなように研磨の結果、素子形成用ウェハ
４１と台ウェハ４２とを分離している酸化膜４３は中心
より上にある。そして、この酸化膜４３は伸びようとし
ているので、基板は研磨したウェハ４１側、即ち上側が
凸に反る。この反りは、１枚のウェハの片面に熱酸化膜
を形成したときと同じく熱収縮差による弾性変形で、酸
化膜が非対称の位置にある限り避けられないものである
。このような基板の反りは、ウェハの大口径化や素子の
微細化が進むに連れてＰＥＰ工程等に支障を来たし、従
って解決すべき大きな問題である。As is clear from this figure, as a result of polishing, the oxide film 43 separating the element forming wafer 41 and the base wafer 42 is located above the center. Since this oxide film 43 is about to stretch, the substrate is warped in a convex manner on the polished wafer 41 side, that is, on the upper side. This warpage is caused by elastic deformation due to the difference in thermal contraction, similar to when a thermal oxide film is formed on one side of a single wafer, and is unavoidable as long as the oxide film is in an asymmetric position. Such warpage of the substrate becomes a problem in the PEP process and the like as the diameter of wafers becomes larger and the size of elements becomes smaller, and therefore it is a major problem that needs to be solved.
一方、前記素子分離用溝の形成は、サイドエツチングな
く溝のパターンを制御し易い異方性エツチングと呼ばれ
る方法で行われている。この溝形成工程を第６図を参照
して説明する。前記第４図（ｂ）に示す工程ののち、第
６図（ａ）に示す如く、シリコンウェハ４１の上面（基
板表面）にエツチングマスクとなる酸化膜５２を形成す
る。このとき、シリコンウェハ４２の下面（基板裏面）
にも酸化膜５１が形成される。次いで、第６図（ｂ）に
示す如く、酸化膜５２上にレジスト５３を塗布しパター
ニングを行い、同図（Ｃ）に示す如くレジスト５３をマ
スクにして酸化膜５２を弗酸等でエツチングし、酸化膜
５２の溝を掘る部分を開口する。On the other hand, the formation of the element isolation trenches is performed by a method called anisotropic etching, which allows easy control of the trench pattern without side etching. This groove forming step will be explained with reference to FIG. After the step shown in FIG. 4(b), an oxide film 52 serving as an etching mask is formed on the upper surface (substrate surface) of the silicon wafer 41, as shown in FIG. 6(a). At this time, the bottom surface of the silicon wafer 42 (back surface of the substrate)
An oxide film 51 is also formed thereon. Next, as shown in FIG. 6(b), a resist 53 is applied and patterned on the oxide film 52, and as shown in FIG. 6(c), the oxide film 52 is etched with hydrofluoric acid or the like using the resist 53 as a mask. , the portion of the oxide film 52 where the trench is to be dug is opened.
次いで、第６図（ｄ）に示す如く、酸化膜５２をマスク
として、異方性エツチングによりシリコンウェハ４１に
溝４５を形成する。Next, as shown in FIG. 6(d), grooves 45 are formed in the silicon wafer 41 by anisotropic etching using the oxide film 52 as a mask.
以上の工程で問題となるのは、第６図（ｂ）から同図（
Ｃ）における工程でマスク酸化膜５２を開口する際に、
裏面の酸化［５１がなくならないようにすることである
。裏面に酸化膜５１がないと溝エツチングの際に基板の
裏面がエツチングされてしまう。従って従来は、マスク
酸化膜５２を弗酸′等でエツチングして開口する時に、
基板裏面の保護を必要としていた。この保護は、例えば
基板裏面にワックスで耐酸性の板を張付ける等して行っ
ていた。The problems in the above process are as shown in Figures 6(b) to 6(b).
When opening the mask oxide film 52 in step C),
The purpose is to prevent oxidation [51] from disappearing on the back surface. If there is no oxide film 51 on the back surface, the back surface of the substrate will be etched during trench etching. Therefore, conventionally, when opening the mask oxide film 52 by etching it with hydrofluoric acid or the like,
It was necessary to protect the back side of the board. This protection has been achieved, for example, by attaching an acid-resistant plate made of wax to the back surface of the substrate.
しかしながら、ワックスで板を張付ける工程は、板を張
付ける以外に板を剥がす工程、ワックスを除去する工程
を必要とし、多大の時間とコストを必要としていた。さ
らに、ワックスがウェハや装置の汚染の原因となる問題
もあった。However, the process of pasting the board with wax requires a process of peeling off the board and removing the wax in addition to pasting the board, which requires a great deal of time and cost. Furthermore, there was also the problem that wax caused contamination of wafers and equipment.
（発明が解決しようとする問題点）
このように従来、２枚のシリコンウェハを酸化膜を介し
て直接接着した半導体基板においては、シリコンと酸化
膜との熱収縮率の差により基板に反りが発生する問題が
あった。また、素子形成に供される側のウェハに素子分
離用の溝を形成する際に基板の裏面側がエツチングされ
る虞れがあり、これを防止するには基板裏面側にワック
スで板を張付ける等の面倒な工程が必要となった。(Problems to be Solved by the Invention) Conventionally, in a semiconductor substrate in which two silicon wafers are directly bonded via an oxide film, the substrate warps due to the difference in thermal contraction rate between the silicon and the oxide film. There was a problem that occurred. Additionally, when forming grooves for device isolation on the wafer used for device formation, there is a risk that the back side of the substrate may be etched, so to prevent this, a plate is pasted with wax on the back side of the substrate. This necessitated such troublesome processes.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、シリコンと酸化膜との熱収縮差に起因
する基板の反りを防止することができ、基板の大口径化
及び素子の微細化にも十分対処し得る誘電体分離型半導
体基板の製造方法を提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to prevent warping of the substrate caused by the difference in thermal contraction between silicon and oxide films, to increase the diameter of the substrate, and to An object of the present invention is to provide a method for manufacturing a dielectrically isolated semiconductor substrate that can sufficiently cope with the miniaturization of semiconductor substrates.
また本発明は、素子分離用溝形成時における裏面のエツ
チングを防止することができ、且つ裏面にワックスで板
を張付ける等の面倒な工程を不要とし、工程の複雑化を
招くことなく裏面保護を行い得る誘電体分離型半導体基
板の製造方法を提供することにある。Furthermore, the present invention can prevent etching of the back surface when forming grooves for element isolation, and eliminates the need for troublesome processes such as pasting a plate with wax on the back surface, thereby protecting the back surface without complicating the process. An object of the present invention is to provide a method for manufacturing a dielectrically isolated semiconductor substrate that can perform the following steps.
［発明の構成］
（問題点を解決するための手段）
本発明の骨子は、厚さが薄い方のシリコンウェハ（素子
形成用ウェハ）と酸化膜との界面をシリコンを熱酸化し
た界面とし、厚さが厚い方のシリコンウェハ（台ウェハ
）と酸化膜との界面を直接接着した界面とすることにあ
る。[Structure of the Invention] (Means for Solving Problems) The gist of the present invention is that the interface between the thinner silicon wafer (element forming wafer) and the oxide film is an interface obtained by thermally oxidizing silicon; The purpose is to make the interface between the thicker silicon wafer (pedestal wafer) and the oxide film a directly bonded interface.
即ち本発明は、素子形成に供される第１のシリコンウェ
ハとこのウェハよりも厚さの厚い第２のシリコンウェハ
とを酸化膜を介して一体化し、第１のシリコンウェハの
素子分離領域に絶縁体を形成して素子分離を行う誘電体
分離型半導体基板の製造方法において、第１のシリコン
ウェハの表面に熱酸化膜を形成したのち、この熱酸化膜
を介して第１及び第２のシリコンウェハを接触させ、該
熱酸化膜が柔らかくなる温度以上で第１及び第２のシリ
コンウェハを接着するようにした方法である。That is, the present invention integrates a first silicon wafer used for element formation with a second silicon wafer thicker than this wafer through an oxide film, and then integrates a first silicon wafer used for element formation with a second silicon wafer through an oxide film. In a method for manufacturing a dielectrically isolated semiconductor substrate in which elements are isolated by forming an insulator, a thermal oxide film is formed on the surface of a first silicon wafer, and then a first and a second silicon wafer are formed through the thermal oxide film. In this method, silicon wafers are brought into contact and the first and second silicon wafers are bonded at a temperature higher than that at which the thermal oxide film becomes soft.
また本発明は、上記誘電体分離型半導体基板の製造方法
において、第１のシリコンウェハの表面に熱酸化膜を形
成したのち、該熱酸化膜を介して第１及び第２のシリコ
ンウェハを接触させ、酸化性雰囲気中で熱処理して第１
及び第２のシリコンウェハを接着すると共に、第２のシ
リコンウェハの表面に保護用酸化膜を形成し、次いで第
１のシリコンウェハの第２のシリコンウェハ接若面と反
対側をエツチングしてウェハ厚みを薄くシ、次いで第１
のシリコン基板のエツチングした面に保護用酸化膜より
も薄いマスク酸化膜を形成するようにした方法である。The present invention also provides the method for manufacturing a dielectrically isolated semiconductor substrate, in which a thermal oxide film is formed on the surface of the first silicon wafer, and then the first and second silicon wafers are brought into contact with each other through the thermal oxide film. and then heat treated in an oxidizing atmosphere to form the first
and a second silicon wafer are bonded together, a protective oxide film is formed on the surface of the second silicon wafer, and then the side of the first silicon wafer opposite to the surface to which the second silicon wafer is attached is etched to form a wafer. Reduce the thickness, then the first
In this method, a mask oxide film, which is thinner than the protective oxide film, is formed on the etched surface of the silicon substrate.
（作 用）
本発明によれば、２枚のシリコンウェハ間の酸化膜がウ
ェハ接着方向の中心よりも第１のウェハ側に位置するの
で、シリコンと酸化膜との界面の差を考慮しないと、基
板は第１のウェハ側が凸になるように反る。一方、シリ
コンと酸化膜との界面は第１のシリコンウェハでは熱酸
化した界面であり、第２のシリコンウェハでは直接接着
による界面である。熱酸化による界面はシリコンとの結
合が直接接着によるシリコンとの結合よりも強固である
。従って、ウェハの厚みを考慮しないと、これらの界面
の差により、基板は第１のシリコンウェハ側が凹になる
ように反る。この２つの作用が相乗されることにより、
っまりウェハ厚みの差による凸状の反りと界面の違いに
よる凹状の反りとが相殺されることにより、基板の反り
は極めて小さいものとなる。(Function) According to the present invention, since the oxide film between the two silicon wafers is located closer to the first wafer than the center in the wafer adhesion direction, the difference in the interface between the silicon and the oxide film must be taken into account. , the substrate is warped so that the first wafer side becomes convex. On the other hand, the interface between silicon and the oxide film is a thermally oxidized interface in the first silicon wafer, and is a directly bonded interface in the second silicon wafer. The bond with silicon formed by thermal oxidation is stronger than that formed by direct adhesion. Therefore, unless the thickness of the wafer is taken into account, the difference in these interfaces causes the substrate to warp so that the first silicon wafer side becomes concave. By synergizing these two effects,
Since the convex warpage due to the difference in wafer thickness and the concave warpage due to the difference in interface cancel each other out, the warpage of the substrate becomes extremely small.
また、２枚のシリコンウェハの接着を酸化性雰囲気中で
行うことにより、特別に酸化工程を要することなく基板
の裏面側に酸化膜を形成することができる。そして、こ
の酸化膜を溝エツチング時の保護膜として用いれば、溝
エツチングにおける基板裏面のエツチングを防止するこ
とが可能となる。Further, by bonding two silicon wafers in an oxidizing atmosphere, an oxide film can be formed on the back side of the substrate without requiring a special oxidation step. If this oxide film is used as a protective film during trench etching, it is possible to prevent the back surface of the substrate from being etched during trench etching.
（実施例）
まず、実施例を説明する前に本発明の基本原理について
説明する。(Example) First, before describing an example, the basic principle of the present invention will be explained.
本発明者等は、表面を熱酸化したウェハと酸化していな
いウェハとを直接接着し、外側の酸化膜を除去して第３
図（ａ）に示す構造を持つ基板を作成した。ここで、１
１．１２はシリコンウェハ、１３は熱酸化膜であり、１
１．１３の界面は熱酸化による界面、１２．１３の界面
は直接接着による界面である。この構造においては、上
下対称にも拘らず図で上側、即ち熱酸化したウェハ１１
側が凹に反ることを見出した。The present inventors directly bonded a wafer whose surface had been thermally oxidized and a wafer whose surface had not been oxidized, removed the outer oxide film, and
A substrate having the structure shown in Figure (a) was created. Here, 1
1.12 is a silicon wafer, 13 is a thermal oxide film, 1
The interface 1.13 is an interface created by thermal oxidation, and the interface 12.13 is an interface created by direct adhesion. In this structure, despite the vertical symmetry, the upper side in the figure, that is, the thermally oxidized wafer 11
It was discovered that the sides curved in a concave manner.
基板が反る理由は以下のように考えられる。前述したよ
うに酸化膜とシリコンには、直接接着後熱収縮差により
応力が発生する。直接接着界面では接着熱処理中に滑り
が起こる等して応力が緩和されるが、熱酸化界面では応
力の緩和はない。従って、熱酸化したウェハ１１にはよ
り強い引張り応力が働きより強く縮もうとする。その結
果、ウェハ１１側が凹に反ることになる。The reason why the board warps can be considered as follows. As mentioned above, stress is generated between the oxide film and silicon due to the difference in thermal shrinkage after direct bonding. At the directly bonded interface, stress is relaxed due to slipping during adhesive heat treatment, but at the thermally oxidized interface, stress is not relaxed. Therefore, stronger tensile stress acts on the thermally oxidized wafer 11, causing it to shrink more strongly. As a result, the wafer 11 side is warped in a concave manner.
また、上記の基板を第３図（ｂ）に示す如くウェハ１１
側を研磨して薄くすると、前記第５図を用いて説明した
ように薄くした方が凸に反るような力が働く。しかし、
本構造では、研磨前にウェハ１１側が凹に反っているた
め、反りが相殺され、その結果研磨後の反りが小さくな
る。つまり、ウェハ厚みの差による凸状の反りと界面の
違いによる凹状の反りとを相殺させることにより、基板
の反りを極めて小さくすることができる。Further, the above substrate is placed on a wafer 11 as shown in FIG. 3(b).
When the side is polished to make it thinner, a force is exerted that causes the thinner side to warp in a convex manner, as explained using FIG. 5 above. but,
In this structure, since the wafer 11 side is warped in a concave manner before polishing, the warp is canceled out, and as a result, the warp after polishing is reduced. In other words, by canceling out the convex warpage due to the difference in wafer thickness and the concave warpage due to the difference in the interface, the warpage of the substrate can be extremely reduced.
なお、直接接着後の熱収縮差による応力は、酸化膜が一
旦柔らかくなるから生じるものであり、酸化膜が柔らか
くなる温度（９５０℃）以下で熱処理した場合には、反
りの発生はない。しかしながら、直接接着を十分で且つ
良好なものとするには、熱処理温度を高くした方が望ま
しく、熱収縮差による反りの問題が発生するのである。Note that the stress due to the difference in thermal shrinkage after direct bonding occurs because the oxide film becomes soft once, and if the heat treatment is performed at a temperature below the temperature at which the oxide film becomes soft (950° C.), no warping occurs. However, in order to achieve sufficient and good direct adhesion, it is desirable to increase the heat treatment temperature, which causes the problem of warping due to the difference in thermal shrinkage.
また、溝エツチングにおける基板裏面側のエツチングを
防止するには、第１のシリコンウェハの代りに第２のシ
リコンウェハの表面を熱酸化して、これらを直接接着す
ればよい。この場合、基板裏面側に酸化膜が形成される
ことになるので、これをエツチング保護膜として用いる
ことが可能である。しかしながら、この方法では反りの
問題は解決されないばかりか、上述した理由からより大
きな反りが発生する。そこで本発明では、ウニ／＼の接
着における熱処理を酸化性雰囲気で行うことにより、第
２のシリコンウェハの表面に酸化膜を形成し、これを裏
面エツチングの保護膜として用いることを可能としてい
る。Furthermore, in order to prevent etching of the back side of the substrate during groove etching, the surface of a second silicon wafer may be thermally oxidized instead of the first silicon wafer, and these may be directly bonded. In this case, since an oxide film is formed on the back side of the substrate, it is possible to use this as an etching protection film. However, this method not only does not solve the warpage problem, but also causes greater warpage for the reasons mentioned above. Therefore, in the present invention, by performing the heat treatment for bonding the sea urchin/\ in an oxidizing atmosphere, an oxide film is formed on the surface of the second silicon wafer, and this can be used as a protective film for back side etching.
以下、本発明の一実施例を図面を参照して説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例に係わる誘電体分離型半
導体基板の製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing the manufacturing process of a dielectrically isolated semiconductor substrate according to a first embodiment of the present invention.
まず、第１図（ａ）に示す如く、片面を鏡面研磨したｎ
型の第１及び第２のシリコンウェハ１１゜１２を各々２
０枚用意した。それぞれのウェハは全く同じものであり
、比抵抗は２０Ωａｍ、厚さは５００μｍ１面方位は（
１Ｏ０）面である。First, as shown in Figure 1(a), one side of the n
The first and second silicon wafers 11 and 12 of the mold are each 2
I prepared 0 pieces. Each wafer is exactly the same, with a specific resistance of 20 Ωam, a thickness of 500 μm, and a plane orientation of (
1O0) plane.
次いで、第１図（ｂ）に示す如く、将来研磨される第１
のシリコンウェハ１１を熱処理して、該ウェハ１１の表
面に熱酸化膜１３．１４を１μｍ形成した。ここで、熱
酸化膜１３は鏡面研磨した面に形成され、熱酸化膜１４
はその反対側面に形成されたものである。Next, as shown in FIG. 1(b), the first
The silicon wafer 11 was heat-treated to form thermal oxide films 13 and 14 with a thickness of 1 μm on the surface of the wafer 11. Here, the thermal oxide film 13 is formed on a mirror-polished surface, and the thermal oxide film 14
is formed on the opposite side.
次いで、第１図（Ｃ）に示す如く、両ウェハ１１゜１２
をクリーンな雰囲気下で鏡面同士を張合わせ、１１００
℃で１時間熱処理を行い、これらを直接接着した。その
後、外側にある酸化膜１４を除去したのち、基板の反り
を測定した。次いで、第１図（ｄ）に示す如く、酸化し
た方のウェハ１１を残り厚さ５０μ尻となるまで研磨し
、再び基板の反りを１ＴＰＪ定した。Next, as shown in FIG. 1(C), both wafers 11°12
The mirror surfaces were pasted together in a clean atmosphere, and 1100
A heat treatment was performed at ℃ for 1 hour, and these were directly bonded. Thereafter, after removing the oxide film 14 on the outside, the warpage of the substrate was measured. Next, as shown in FIG. 1(d), the oxidized wafer 11 was polished until the remaining thickness was approximately 50 μm, and the warpage of the substrate was again determined to be 1 TPJ.
次いで、第１図（ｅ）に示す如く異方性エツチングで素
子分離用の溝１５を形成したのち、同図（ｆ’）に示す
如く溝１５の側面を含む基板表面に素子分離用酸化膜１
６を形成した。その後、第１図（ｇ）に示す如く、基板
表面に多結晶シリコン膜１７を堆積して溝１５を埋込み
、さらに表面を平坦化することにより誘電体分離型半導
体基板を完成した。Next, as shown in FIG. 1(e), grooves 15 for device isolation are formed by anisotropic etching, and then an oxide film for device isolation is formed on the substrate surface including the side surfaces of the grooves 15, as shown in FIG. 1(f'). 1
6 was formed. Thereafter, as shown in FIG. 1(g), a polycrystalline silicon film 17 was deposited on the surface of the substrate to fill the trenches 15, and the surface was further flattened to complete a dielectrically isolated semiconductor substrate.
また、この状態における基板の反りも測定した。Further, the warpage of the substrate in this state was also measured.
一方、比較のために両方のウェハ１１，１２を接着前に
共に酸化した以外は同様にして誘電体分離型半導体基板
を作成し、同様に反りを測定した。On the other hand, for comparison, a dielectric isolation type semiconductor substrate was prepared in the same manner except that both wafers 11 and 12 were oxidized before bonding, and the warpage was measured in the same manner.
その結果、実施例と比較例の各工程における反りは下記
衣の通りであった。なお、この表でウェハ１１側が凸の
場合の反りを正、凹の場合の反りを負で表わし、単位は
μｍとした。As a result, the warpage in each step of the Examples and Comparative Examples was as shown below. In this table, the warpage when the wafer 11 side is convex is expressed as positive, and the warpage when it is concave is expressed as negative, and the unit is μm.
表
かくして本実施例方法によれば、最終的に素子を形成す
る厚さの薄い方のウェハ１１側に熱酸化膜１３を形成す
ることにより、酸化膜位置の非対称性による応力と界面
の違いによる応力とを緩和することができ、基板の反り
を大幅に低減することができる。このため、基板の大口
径化や素子の微細化等が可能となり、その有用性は絶大
である。Thus, according to the method of this embodiment, by forming the thermal oxide film 13 on the side of the thinner wafer 11 on which elements will ultimately be formed, stress due to the asymmetry of the oxide film position and the difference in the interface can be reduced. The stress can be alleviated, and the warpage of the substrate can be significantly reduced. Therefore, it becomes possible to increase the diameter of the substrate, miniaturize the device, etc., and its usefulness is enormous.
第２図は本発明の第２の実施例方法を説明するための工
程断面図である。なお、第１図と同一部分には同一符号
を付して、その詳しい説明は省略する。FIG. 2 is a process sectional view for explaining a second embodiment method of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.
この実施例は先に説明した第１の実施例に加え、素子分
離用溝形成工程の改良をはかったものである。即ち、前
記第１図（ｂ）に示す工程ののち、２枚のウェハ１１，
１２を直接接着するに際し、これらを張合わせたのち水
蒸気雰囲気中ｔｔｏｏ℃で３時間加熱処理した。これに
より、２枚のウエノ１１１．１２は熱酸化膜１３を介し
て接着されると共に、第２図（ａ）に示す如くウェハ１
２の表面（基板裏面）にも酸化膜２１が１．１μｍ形成
された。In addition to the first embodiment described above, this embodiment is an improvement in the step of forming trenches for element isolation. That is, after the step shown in FIG. 1(b), two wafers 11,
When directly adhering No. 12, they were pasted together and then heat-treated at too much° C. for 3 hours in a steam atmosphere. As a result, the two wafers 111 and 12 are bonded together via the thermal oxide film 13, and the wafer 111 and 12 are bonded together as shown in FIG. 2(a).
An oxide film 21 with a thickness of 1.1 μm was also formed on the surface of the substrate 2 (back surface of the substrate).
次いで、第２図（ｂ）に示す如くウェハ１１を研磨した
のち、同図（Ｃ）に示す如くウェハ１１の表面（基板表
面）にマスク酸化膜２２を形成した。Next, after polishing the wafer 11 as shown in FIG. 2(b), a mask oxide film 22 was formed on the surface of the wafer 11 (substrate surface) as shown in FIG. 2(C).
このとき、酸化膜２２の厚みは５０００人とし、特別に
基板裏面の保護は行わなかった。その後、第２図（ｄ）
に示す如く、酸化膜２２上にレジスト２３を塗布し、該
レジストをバターニングして溝エツチング用のマスクを
形成した。At this time, the thickness of the oxide film 22 was set to 5000, and no special protection was applied to the back surface of the substrate. Then, Fig. 2(d)
As shown in FIG. 2, a resist 23 was applied onto the oxide film 22, and the resist was patterned to form a mask for trench etching.
次いで、第１図（ｅ）に示す如く、レジスト２３をマス
クとして酸化膜２２をエツチングし、溝形成用の開口を
形成した。このとき、レジスト２３で覆われていない基
板裏面側の酸化膜２１もエツチングされるが、酸化膜２
１の厚みが酸化膜２２の厚みよりも十分厚いので、酸化
膜２２の開口形成が終了した時点では酸化膜２１は膜厚
が減るのみで基板裏面側に十分残ることになる。Next, as shown in FIG. 1(e), the oxide film 22 was etched using the resist 23 as a mask to form an opening for forming a groove. At this time, the oxide film 21 on the back side of the substrate that is not covered with the resist 23 is also etched, but the oxide film 21
Since the thickness of the oxide film 1 is sufficiently thicker than the thickness of the oxide film 22, when the opening formation in the oxide film 22 is completed, the oxide film 21 only decreases in thickness and remains sufficiently on the back side of the substrate.
次いで、レジスト２３を除去したのち、第２図（ｆ’）
に示す如く、異方性エツチングによりウェハ１１をエツ
チングすることにより素子分離用溝１５を形成した。こ
れ以降は、先の実施例と同様に、酸化膜１６及び多結晶
シリコン膜１７を形成することにより、誘電体分離型半
導体基板が完成することになる。Next, after removing the resist 23, FIG. 2(f')
As shown in FIG. 2, grooves 15 for element isolation were formed by etching the wafer 11 using anisotropic etching. After this, as in the previous embodiment, an oxide film 16 and a polycrystalline silicon film 17 are formed to complete a dielectric isolation type semiconductor substrate.
かくして本実施例方法によれば、溝エツチングの際には
、基板裏面側に酸化膜２１が残存しているので、ウェハ
１２がエツチングされることはない。そしてこの場合、
基板裏面側にワックスで板を張付ける等の面倒な工程も
不要であり、ウエハ１１．１２の接着を酸化性雰囲気で
行うことにより、裏面保護を容易に実現することができ
る。また、最終的に得られる基板の反りも、先の実施例
と同様に極めて小さくすることができる。According to the method of this embodiment, the oxide film 21 remains on the back side of the substrate during groove etching, so that the wafer 12 is not etched. And in this case,
There is no need for a troublesome process such as attaching a plate with wax to the back side of the substrate, and by bonding the wafers 11 and 12 in an oxidizing atmosphere, protection of the back surface can be easily achieved. Further, the warpage of the finally obtained substrate can be made extremely small as in the previous embodiment.
なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記２枚のシリコンウェハを接着する際
の熱処理温度は、接着前に第１のウェハ表面に形成した
熱酸化膜が柔らかくなる温度であればよく、通常は９５
０℃以上であればよい。Note that the present invention is not limited to each of the embodiments described above. For example, the heat treatment temperature when bonding the two silicon wafers may be any temperature that softens the thermal oxide film formed on the surface of the first wafer before bonding, and is usually 95°C.
It is sufficient if the temperature is 0°C or higher.
さらに、第１のウェハを研磨して薄くする工程は、ウェ
ハ接着後に限るものではなく、接着後であってもよい。Furthermore, the step of polishing the first wafer to make it thinner is not limited to after bonding the wafers, but may be performed after bonding.
また、マスク酸化膜の厚みはウェハ接着時に形成された
基板裏面側の酸化膜の厚みよりも薄いものであればよい
が、裏面保護を確実にするためには、裏面側の酸化膜の
厚みの１／２以下にすればよい。その他、本発明の要旨
を逸脱しない範囲で、種々変形して実施することができ
る。In addition, the thickness of the mask oxide film should be thinner than the oxide film on the back side of the substrate formed during wafer bonding, but in order to ensure protection of the back side, the thickness of the oxide film on the back side must be thinner. It may be reduced to 1/2 or less. In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果コ
以上詳述したように本発明によれば、直接接着による基
板の反りを低減することができ、基板の大口径化及び素
子の微細化等に有効である。また、基板裏面にワックス
で板を張付ける等の特別な工程を要することなく裏面保
護を行うことができ、製造工程の簡略化をはかり得る等
の効果がある。[Effects of the Invention] As detailed above, according to the present invention, it is possible to reduce the warping of a substrate due to direct bonding, and it is effective for increasing the diameter of the substrate and miniaturizing the elements. Further, the back surface can be protected without requiring a special process such as pasting a plate with wax on the back surface of the substrate, and the manufacturing process can be simplified.
第１図は本発明の第１の実施例方法に係わる誘電体分離
型半導体基板の製造工程を示す断面図、第２図は本発明
の第２の実施例方法を説明するための工程断面図、第３
図は本発明の詳細な説明するための断面図、第４図乃至
第６図はそれぞれ従来の問題点を説明するための断面図
である。
１１・・・第１のシリコンウェハ、１２・・・第２のシ
リコンウェハ、１３．１４・・・熱酸化膜、１５・・・
素子分離用溝、１６・・・素子分離用酸化膜、１７・・
・多結晶シリコン膜、２１・・・保護用酸化膜、２２・
・・マスク酸化膜、２３・・・レジスト。
出願人代理人 弁理士 鈴江武彦
第１
第２
第３図
第６図FIG. 1 is a cross-sectional view showing the manufacturing process of a dielectrically isolated semiconductor substrate according to the method of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the process for explaining the method of the second embodiment of the present invention. , 3rd
The figure is a cross-sectional view for explaining the present invention in detail, and FIGS. 4 to 6 are cross-sectional views for explaining the problems of the conventional art. 11... First silicon wafer, 12... Second silicon wafer, 13.14... Thermal oxide film, 15...
Element isolation groove, 16... Element isolation oxide film, 17...
・Polycrystalline silicon film, 21... Protective oxide film, 22.
...Mask oxide film, 23...Resist. Applicant's agent Patent attorney Takehiko Suzue No. 1 No. 2 Fig. 3 Fig. 6
Claims (4)
ウェハに接着すべき第２のシリコンウェハとを酸化膜を
介して一体化し、第１のシリコンウェハの素子分離領域
に絶縁体を形成して素子分離を行う誘電体分離型半導体
基板の製造方法において第１のシリコンウェハの表面に
熱酸化膜を形成したのち、この熱酸化膜を介して第１及
び第２のシリコンウェハを接触させ、該熱酸化膜が柔ら
かくなる温度以上で第１及び第２のシリコンウェハを接
着することを特徴とする誘電体分離型半導体基板の製造
方法。(1) A first silicon wafer to be used for device formation and a second silicon wafer to be bonded to this wafer are integrated via an oxide film, and an insulator is formed in the device isolation region of the first silicon wafer. In a method for manufacturing a dielectrically isolated semiconductor substrate that performs element isolation, a thermal oxide film is formed on the surface of a first silicon wafer, and then the first and second silicon wafers are brought into contact with each other through the thermal oxide film. . A method for manufacturing a dielectrically isolated semiconductor substrate, characterized in that first and second silicon wafers are bonded at a temperature above which the thermal oxide film becomes soft.
ンウェハに接着する前又は後に、該第２のシリコンウェ
ハよりも薄く形成されることを特徴とする特許請求の範
囲第１項記載の誘電体分離型半導体基板の製造方法。(2) The first silicon wafer is formed thinner than the second silicon wafer before or after bonding to the second silicon wafer. A method for manufacturing a dielectrically isolated semiconductor substrate.
ウェハよりも厚さの厚い第２のシリコンウェハとを酸化
膜を介して一体化し、第１のシリコンウェハの素子分離
領域に絶縁体を形成して素子分離を行う誘電体分離型半
導体基板の製造方法において、第１のシリコンウェハの
表面に熱酸化膜を形成する工程と、該熱酸化膜が形成さ
れた第１のシリコンウェハに第２のシリコンウェハを接
触させ、熱処理して第１及び第２のシリコンウェハを接
着すると共に、この熱処理を酸化性雰囲気中で行い第２
のシリコンウェハの表面に保護用酸化膜を形成する工程
と、前記第１のシリコンウェハを第２のシリコンウェハ
接着面と反対側からエッチングしてウェハ厚みを薄くす
る工程と、前記第１のシリコンウェハの薄くした表面に
前記保護用酸化膜よりも薄いマスク用酸化膜を形成する
工程とを含むことを特徴とする誘電体分離型半導体基板
の製造方法。(3) A first silicon wafer used for device formation and a second silicon wafer, which is thicker than this wafer, are integrated via an oxide film, and an insulator is placed in the device isolation region of the first silicon wafer. A method for manufacturing a dielectrically isolated semiconductor substrate in which element isolation is performed by forming a semiconductor substrate includes the steps of: forming a thermal oxide film on the surface of a first silicon wafer; A second silicon wafer is brought into contact and heat treated to bond the first and second silicon wafers, and this heat treatment is performed in an oxidizing atmosphere to bond the second silicon wafer.
forming a protective oxide film on the surface of the silicon wafer; etching the first silicon wafer from the side opposite to the bonding surface of the second silicon wafer to reduce the wafer thickness; A method for manufacturing a dielectrically isolated semiconductor substrate, comprising the step of forming a mask oxide film thinner than the protective oxide film on the thinned surface of the wafer.
以下の膜厚であることを特徴とする特許請求の範囲第３
項記載の誘電体分離型半導体基板の製造方法。(4) Claim 3, wherein the masking oxide film has a thickness less than half that of the protective oxide film.
A method for manufacturing a dielectrically isolated semiconductor substrate as described in 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63002103A JP3016512B2 (en) | 1988-01-08 | 1988-01-08 | Method for manufacturing dielectric-separated semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63002103A JP3016512B2 (en) | 1988-01-08 | 1988-01-08 | Method for manufacturing dielectric-separated semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01181438A true JPH01181438A (en) | 1989-07-19 |
| JP3016512B2 JP3016512B2 (en) | 2000-03-06 |
Family
ID=11520008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63002103A Expired - Lifetime JP3016512B2 (en) | 1988-01-08 | 1988-01-08 | Method for manufacturing dielectric-separated semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3016512B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599722A (en) * | 1993-11-26 | 1997-02-04 | Nippondenso Co., Ltd. | SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226640A (en) * | 1986-03-28 | 1987-10-05 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62229855A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-01-08 JP JP63002103A patent/JP3016512B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226640A (en) * | 1986-03-28 | 1987-10-05 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62229855A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599722A (en) * | 1993-11-26 | 1997-02-04 | Nippondenso Co., Ltd. | SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3016512B2 (en) | 2000-03-06 |
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