JPS62229855A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62229855A JPS62229855A JP7078386A JP7078386A JPS62229855A JP S62229855 A JPS62229855 A JP S62229855A JP 7078386 A JP7078386 A JP 7078386A JP 7078386 A JP7078386 A JP 7078386A JP S62229855 A JPS62229855 A JP S62229855A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- groove
- semiconductor single
- crystal
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000013078 crystal Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 14
- 238000000926 separation method Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係り、特に誘電体を
用いた素子分離法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an element isolation method using a dielectric.
従来ＩＣやＬＳＩなどで各素子間の分離を絶縁体で行な
ういわゆる誘電体分離法は、ｐｎ接合分離に比べて、■
もれ電流を極めて小さくすることができる。■耐圧を大
きくすることができる。The so-called dielectric isolation method, which uses an insulator to isolate each element in conventional ICs and LSIs, has a
Leakage current can be made extremely small. ■The withstand voltage can be increased.
Ｇ５電圧印加の方向に気を配る必要がない、透孔の利点
を有する。G5 has the advantage of a through hole, which eliminates the need to pay attention to the direction of voltage application.
理想的な誘電体分離は、各素子を電極接続部を除いて絶
縁体で完全に包み込むことで達成される。Ideal dielectric isolation is achieved by completely encasing each element with an insulator except for electrode connections.
このような素子は例えば、サファイア上にシリコンをエ
ピタキシャル成長させたＳＯ８基板を用いて形成するこ
とができる。しかしながら、サファイアは高価であり、
またシリコンとの結晶整合性も完全ではなく良質の単結
晶膜が得られない、膜厚を充分厚くすることができない
、などの理由で、作製できる素子の種類に制限がある。Such an element can be formed using, for example, an SO8 substrate in which silicon is epitaxially grown on sapphire. However, sapphire is expensive and
Furthermore, the crystal consistency with silicon is not perfect, making it impossible to obtain a high-quality single crystal film or making the film thick enough, which limits the types of devices that can be produced.
サファイアのような絶縁体Ｊ＆板を用いない誘電体分離
法も、これまで数多く提案されている。その−例を第３
図（ａ）〜（ｄ）で説明する。Many dielectric isolation methods that do not use insulator J& plates such as sapphire have been proposed so far. The third example is
This will be explained with reference to Figures (a) to (d).
まず第３図（ａ）は、シリコン単結晶内３１で通常結晶
方位（１００）面を主面として結晶面方位によってエツ
チング速度の差を有するアルカリ系のエツチング液によ
る異方性エツチング技術により複数の分離ｖ字溝３２を
形成し第３図（ｂ）に示すように全面をＳｉＯ□膜等の
絶縁膜３３で覆う。この後第３図（ｃ）に示すように絶
縁膜上に多結晶シリコン支持体層３４を堆積する。First, FIG. 3(a) shows a silicon single crystal 31 in which multiple etches are etched using an anisotropic etching technique using an alkaline etching solution with the (100) plane as the principal plane and the etching rate differing depending on the crystal plane orientation. A separation V-shaped groove 32 is formed and the entire surface is covered with an insulating film 33 such as a SiO□ film as shown in FIG. 3(b). Thereafter, as shown in FIG. 3(c), a polycrystalline silicon support layer 34 is deposited on the insulating film.
次に裏表を逆にしてシリコン基板３１を研磨エツチング
等により各単結晶が完全に分離されるまで削り落とす。Next, the silicon substrate 31 is turned upside down and polished off by etching or the like until each single crystal is completely separated.
そして第３図（ｄ）に示すようにこの分離された単結晶
内３１（ａ）、（ｂ）に半導体層３５ （ａ） 。As shown in FIG. 3(d), a semiconductor layer 35(a) is formed within the separated single crystal 31(a) and (b).
（ｂ）を形成して誘電体分離された素子を得る。(b) to obtain a dielectrically isolated element.
この様な従来の方法での最大の問題は、支持体層の形成
が必須である点にある。支持体層の堆積や異常堆積物（
突起物）の除去等の余分な工程が必要だけでなく、例え
ば良く使われる多結晶シリコンの場合でも、堆積速度が
遅いために、研磨等の工程に耐え得る充分な厚さを得る
ために非常に長い時間を要する。さらにこの多結晶シリ
コンと単結晶シリコンの熱膨張係数の違いから生ずる反
りが発生し、場合によっては数百ミクロンの反りによる
変形が発生し支持体層成形のＰＥＰ工程が困難で製品の
歩留りが非常に悪い欠点があった。The biggest problem with such conventional methods is that it is essential to form a support layer. Support layer deposition and abnormal deposits (
Not only do extra steps such as removing protrusions (protrusions) need to be removed, but even the commonly used polycrystalline silicon has a slow deposition rate, making it extremely difficult to obtain a sufficient thickness to withstand polishing and other steps. It takes a long time. Furthermore, warping occurs due to the difference in thermal expansion coefficient between polycrystalline silicon and single crystal silicon, and in some cases, warping of several hundred microns causes deformation, making the PEP process for forming the support layer difficult and reducing the product yield. had some bad flaws.
本発明は上記した点に鑑みなされたもので、簡便な工程
で信頼性の高い誘電体分離を可能とした半導体装置の製
造方法を提供することを目的とする。The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables highly reliable dielectric isolation through simple steps.
本発明は、二枚の半導体単結晶内の表面が充分平滑に鏡
面研磨されている時、その研磨面同士を充分に清浄な雰
囲気下で直接密着させることにより強固な基板接合体が
得られるという知見に基き、この技術を誘電体分離に適
用する０本発明の骨子は、二枚の半導体単結晶内の間に
絶縁膜が介在した接合体を用い、その一方の半導体単結
晶内の結晶面（１００） を主面としてアルカリ性エツ
チング液による異方性エツチング技術によって分離用の
７字溝を設け、複数の分離された単結晶の島を形成した
ものにおいて１分離用の７字溝の幅Ｗと単結晶の島の厚
さしを
Ｗ Ｗ
Ｔ ” ｔａｎ ｏ ＞ ｔ≧Ｔ＠ｔａｎθ（１−ａ）
（ここで０は（１００）面で＜１１０＞方向に走る溝に
対して５４．７°）
なる関係に形成し、配列した事を特徴とする。According to the present invention, when the surfaces of two semiconductor single crystals are sufficiently smooth and mirror-polished, a strong substrate assembly can be obtained by directly bringing the polished surfaces into close contact with each other in a sufficiently clean atmosphere. Based on this knowledge, this technology is applied to dielectric separation.The gist of the present invention is to use a bonded body in which an insulating film is interposed between two semiconductor single crystals, and to separate the crystal planes in one of the semiconductor single crystals. (100) The width W of the seven-shaped groove for one separation is formed by forming a plurality of isolated single crystal islands by forming seven-shaped grooves for separation using an anisotropic etching technique using an alkaline etching solution on the main surface. and the thickness of the single crystal island W W T ” tan o > t≧T@tanθ (1-a)
(Here, 0 is 54.7° with respect to the groove running in the <110> direction on the (100) plane).
本発明によれば、絶縁膜を介して直接接着した単結晶の
強固な基板接合体を用いる為、基板の反りを無視する事
ができ、かつ基板接合体形成後の高温熱処理工程や研磨
工程の影響をなんら受けることがない、又島状単結晶間
の幅（分離用の７字溝の幅）Ｗと、厚みｔを規定する事
により、集積度が高く、かつ信頼性の高い誘電体分離構
造が可能となる。さらに基板表面が平坦化しているので
、電極の配線が容易で歩留りが高く、安価な半導体装置
を提供することができる。According to the present invention, since a strong single-crystal substrate assembly is used which is directly bonded through an insulating film, warping of the substrate can be ignored, and the high-temperature heat treatment process and polishing process after forming the substrate assembly can be ignored. By specifying the width W between the island-shaped single crystals (width of the 7-shaped groove for separation) and the thickness t, it is possible to achieve high integration and reliable dielectric separation without being affected by any effects. structure becomes possible. Furthermore, since the substrate surface is flattened, electrode wiring is easy, and a high yield and inexpensive semiconductor device can be provided.
以下本発明の実施例を図を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は分離用の７字溝を形成する場合の一実施例を示
した図で、（８）図は斜視図、（ｂ）図は（ａ）図のＡ
−Ａ’間の断面を示したものである。結晶面（１００）
を主面とする単結晶シリコン基板１ｏにアルカリ系水溶
液を用いたエツチングを行なうと、第１図（ａ）に示す
ように結晶面（１００）はエツチング速度が早く結晶面
（１１１）に対してはエツチング速度が非常に遅いため
、結晶面によるエツチング速度の差を利用した異方性エ
ツチングを行なう事ができる。この異方性エツチングを
例えば酸化膜（ｓｉｏ、）をマスク材１３として用いて
行なうと、結晶面（１００）と（１１１）で決まる角度
θをもった７字溝が形成される６第１図（ｂ）に示した
二枚の半導体単結晶内１０及び１２の間に絶縁膜１１が
介在した基板接合体の場合、分離用のＶ字溝１４によっ
て単結晶の島を形成するには１分離用の７字溝幅Ｗと島
の厚さｔの関係は、丁’ｔａｎθ）ｔを満足させる必要
が有り、厚さｔが左辺より大きい条件では分離用の７字
溝が絶縁膜まで達せず、電気的分離が不可能となる。一
方この様な基板接合体上に半導体集積回路を構築する場
合には、ベレット寸法を最小化する必要がある。ペレッ
トの寸法を最小化するには、半導体集積回路の各構成素
子が電気的特性上から必要となる最小限の大きさと、厚
みを持った絶縁分離された単結晶の島を高密度に形成す
る必要がある。従って上記開運点を解決するには。Figure 1 is a diagram showing an example of forming a 7-shaped groove for separation, where Figure (8) is a perspective view and Figure (b) is A of Figure (a)
-A' shows a cross section. Crystal plane (100)
When etching is performed using an alkaline aqueous solution on a single-crystal silicon substrate 1o having a main surface of Since the etching rate is very slow, anisotropic etching can be performed using the difference in etching rate depending on the crystal plane. When this anisotropic etching is performed using, for example, an oxide film (SIO) as the mask material 13, a 7-shaped groove with an angle θ determined by the crystal planes (100) and (111) is formed.6Fig. In the case of the substrate assembly in which the insulating film 11 is interposed between the two semiconductor single crystals 10 and 12 shown in FIG. The relationship between the width W of the figure 7 groove for isolation and the thickness t of the island must satisfy d'tanθ)t, and if the thickness t is larger than the left side, the figure 7 groove for isolation will not reach the insulating film. , electrical isolation becomes impossible. On the other hand, when constructing a semiconductor integrated circuit on such a substrate assembly, it is necessary to minimize the pellet size. In order to minimize the size of the pellet, each component of a semiconductor integrated circuit must have the minimum size and thickness necessary for its electrical characteristics, and form isolated single crystal islands at high density. There is a need. Therefore, to solve the above-mentioned good luck points.
分離用の７字溝幅Ｗと島の厚さｔの関係をＷ
Ｗ
Ｔ−ｔａｎθ＞ ｔ ＞（Ｗ／２）（１−ａ ） ・ｔ
ａｎθθ： ５４．７°（角度）
ａ：０．２ （定数）
になる様に規定した。The relationship between the separation groove width W and the island thickness t is W
W T-tanθ> t > (W/2) (1-a) ・t
Anθθ: 54.7° (angle) a: 0.2 (constant).
第２図（ａ）〜（ｈ）は、本発明を用いたフォトダイオ
ードアレイを製造する場合の一実施例を示す図である。FIGS. 2(a) to 2(h) are diagrams showing an example of manufacturing a photodiode array using the present invention.
第２図（ａ）は、面相数（１００）、抵抗率１０〜２０
Ω・口のＮ型シリコン単結晶内１０に熱酸化膜１１を１
〜１．５癖形成したものを用意する０次に上記基板１０
ともう一方の単結晶内１２との相対向する面の鏡面研磨
側どうしを向けて第２図（ｂ）に示すように密着させ、
２００℃異常の温度で熱処理して接合させる。このよ
うに形成された基板接合体の一方の基板１０を６０±５
−の厚さになるまで研磨、エツチング等により削り、マ
スク材として熱酸化［１３を５０００人形成し第２図（
ｃ）に示す構造を得る。Figure 2 (a) shows the number of planes (100) and the resistivity of 10 to 20.
A thermal oxide film 11 is placed on the inside of the N-type silicon single crystal 10 at Ω.
~1.5 Next, prepare the substrate 10 with 1.5 textures formed.
and the other single crystal inner 12, with their mirror polished sides facing each other and brought into close contact as shown in FIG. 2(b).
They are bonded by heat treatment at an abnormal temperature of 200°C. One substrate 10 of the substrate assembly thus formed is 60±5
The mask material was then thermally oxidized [13] by 5,000 people, as shown in Figure 2 (
Obtain the structure shown in c).
次に配列されたフォトダイオードの間隔が１００ｔｎａ
に設計されたガラスマスクを使って一般に知られている
ＰＥＰ工程により酸化膜１３の一部に幅１００−の格子
状の開口部を設け、この酸化膜をマスクとして例えばＫ
ＯＨを主成分とするアルカリ性エツチング液を用い約８
０℃の温度中にて異方性エツチングを行い、第２図（ｄ
）に示すように分離用のＶ字溝１４（ａ）及び１４（ｂ
）によって単結晶の島１０（ａ）〜（ｃ）を形成する。Next, the spacing between the arrayed photodiodes is 100tna.
A lattice-shaped opening with a width of 100 mm is formed in a part of the oxide film 13 by a generally known PEP process using a glass mask designed in 1995. Using this oxide film as a mask, for example, K.
Using an alkaline etching solution containing OH as the main component, approximately 8
Anisotropic etching was carried out at a temperature of 0°C, as shown in Figure 2 (d).
), the V-shaped grooves 14(a) and 14(b) for separation are
) to form single crystal islands 10(a) to (c).
この各島状に分離された単結晶の表面を第２図（ｅ）に
示すように熱酸化膜１５を１〜１．！ＪＩＩ＠形成しこ
の上に第２図（ｆ）に示すように多結晶ポリシリコン１
６を約６０ｕＭ堆積させる１次に多結晶ポリシリコン側
より研磨を行ない単結晶の島の厚みを５０．になるまで
研磨、エツチング等により削り第２図（ｇ）に示す誘電
体分離基板を完成させる。この後、誘電体分離された単
結晶の島１０（ｂ）の内部にＰ型の不純物であるたとえ
ばボロンとＮ型の不純物であるたとえばリンをそれぞ九
導入しＰ型層１７とＮ型層１８を形成し、第２図（ｈ）
に示したフォトダイオードを作製する。この様に構成さ
れたフォトダイオードを配線電極によって複数個直列接
続する事によりフォトダイオードアレイが完成する。As shown in FIG. 2(e), the surface of each single crystal separated into island shapes is coated with a thermal oxide film 15 of 1 to 1. ! JII@ is formed and polycrystalline silicon 1 is formed on this as shown in FIG. 2(f).
After about 60 μM of polycrystalline silicon is deposited, polishing is performed from the polycrystalline side to a thickness of 50 μM. The dielectric isolation substrate shown in FIG. 2(g) is completed by polishing, etching, etc. until the dielectric isolation substrate is polished. Thereafter, a P-type impurity such as boron and an N-type impurity such as phosphorus are introduced into the dielectrically isolated single crystal island 10(b) to form a P-type layer 17 and an N-type layer. Figure 2 (h)
Fabricate the photodiode shown in . A photodiode array is completed by connecting a plurality of photodiodes configured in this manner in series using wiring electrodes.
以上のようにして本発明実施例によれば、信頼性の高い
誘電体分離構造の半導体装置を簡単に作ることができる
。本発明の最大の特徴は二枚の半導体単結晶内のｌ１ｆ
Ｉに絶縁膜が介在した接合体を用い一方の半導体単結晶
内が結晶面（１００）を主面とした場合、分離用の７字
溝が形成する最大溝幅Ｗと単結晶の島の厚みｔを規定す
ることにより集積度が高く、かつ歩留りが高い誘電体分
離されたフォトダイオードアレイを製造することができ
る。As described above, according to the embodiment of the present invention, a highly reliable semiconductor device having a dielectric isolation structure can be easily manufactured. The biggest feature of the present invention is that l1f in two semiconductor single crystals
When a bonded body with an insulating film interposed in I is used, and one semiconductor single crystal has the crystal plane (100) as the main surface, the maximum groove width W formed by the figure 7 groove for isolation and the thickness of the single crystal island By defining t, it is possible to manufacture a dielectrically isolated photodiode array with a high degree of integration and a high yield.
上記実施例では基板接合体を形成する前に一方の半導体
単結晶内に絶縁膜を形成したが両方の基板に絶縁膜を形
成した後に基板接合体を形成したものにおいても本発明
を適用することができる。In the above embodiment, an insulating film was formed within one semiconductor single crystal before forming a substrate assembly, but the present invention can also be applied to an arrangement in which an insulating film is formed on both substrates and then a substrate assembly is formed. I can do it.
又、−上記実施例ではフォトダイオードアレイについて
説明したがトランジスタやサイリスタ、ＭＯＳＦＥＴ等
も形成する事ができる。Further, in the above embodiments, a photodiode array has been described, but transistors, thyristors, MOSFETs, etc. can also be formed.
第１図は本発明実施例による分離用の７字溝を形成する
場合の条件を説明した図、第２図は本発明による一実施
例の素子製造工程を示す図、第３図は従来のＭ電体分離
法による素子製造］：程を示す図である。
ＩＯ・・・結晶面（１００）を主面とする半導体単結晶
内１１・・・絶縁膜
１２・・・半導体単結晶内
１３・・・マスク材（熱酸化膜）
１４・・・分離用の７字溝
１５・・・絶ｌｐｋ膜
１６・・・多結晶シリコン層
１７・・・Ｐ型層
１８・・・Ｎ型層
代理人 弁理士 則 近 憲 佑
同 竹花喜久男
第 １ 図
第 ２ 図
第 ２ 図FIG. 1 is a diagram explaining the conditions for forming a 7-shaped groove for isolation according to an embodiment of the present invention, FIG. 2 is a diagram showing the device manufacturing process of an embodiment of the present invention, and FIG. Element manufacturing by M electric separation method]: It is a figure showing the process. IO...Inside a semiconductor single crystal whose main surface is the crystal plane (100) 11...Insulating film 12...Inside a semiconductor single crystal 13...Mask material (thermal oxide film) 14...For isolation Figure 7 groove 15... Absolute lpk film 16... Polycrystalline silicon layer 17... P type layer 18... N type layer Agent Patent attorney Noriyuki Chika Yudo Kikuo Takehana Figure 1 Figure 2 Figure 2 2 figure
Claims (2)
われ、結合すべき第１及び第２の半導体単結晶基板を清
浄な雰囲気下で密着させ、２００℃以上の温度で熱処理
して接合する工程と、接合された第１の半導体単結晶基
板の表面から所定の厚みに研磨して除去する工程と、研
磨された第１の半導体単結晶表面からアルカリ性エッチ
ング液を用いて絶縁膜に達する溝を設け、第１の半導体
単結晶の島を形成する工程と、第１の半導体単結晶の島
の表面を再度絶縁膜で覆う工程と、前記溝部分に多結晶
シリコンを埋込む工程と、さらに半導体単結晶の島の表
面が露出するまで平坦に研磨を行ない、この絶縁分離さ
れた半導体単結晶内に少なくとも１つ以上のＰ−Ｎ接合
を形成して成る半導体装置において、上記第１の半導体
単結晶の厚みをと島の間隔Ｗが Ｗ／２・ｔａｎθ＞ｔ≧（Ｗ／２）（１−ａ）・ｔａｎ
θ（ここでθは（１００）面で＜１１０＞方向に走る溝
に耐熱して５４．７°） なる関係に形成した事を特徴とする半導体装置の製造方
法。(1) At least the first semiconductor single crystal substrate is covered with an insulating film, and the first and second semiconductor single crystal substrates to be bonded are closely attached in a clean atmosphere and bonded by heat treatment at a temperature of 200°C or higher. a step of polishing and removing the surface of the bonded first semiconductor single crystal substrate to a predetermined thickness; and a step of using an alkaline etching solution to reach the insulating film from the polished first semiconductor single crystal surface. a step of providing a groove to form a first semiconductor single crystal island; a step of covering the surface of the first semiconductor single crystal island with an insulating film again; and a step of filling the groove portion with polycrystalline silicon; Further, in the semiconductor device, the semiconductor single crystal is polished flat until the surface of the island is exposed, and at least one or more P-N junction is formed in the isolated semiconductor single crystal. The thickness of the semiconductor single crystal and the distance W between the islands are W/2・tanθ>t≧(W/2)(1-a)・tan
A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed in the following relationship: θ (where θ is 54.7°, the heat resistance of a groove running in the <110> direction on the (100) plane).
特許請求の範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the value of the constant a is set to 0.2 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61070783A JPH0754826B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61070783A JPH0754826B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62229855A true JPS62229855A (en) | 1987-10-08 |
| JPH0754826B2 JPH0754826B2 (en) | 1995-06-07 |
Family
ID=13441465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61070783A Expired - Fee Related JPH0754826B2 (en) | 1986-03-31 | 1986-03-31 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0754826B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01181438A (en) * | 1988-01-08 | 1989-07-19 | Toshiba Corp | Manufacture of dielectric-isolation semiconductor substrate |
| JPH02260442A (en) * | 1989-03-30 | 1990-10-23 | Toshiba Corp | Dielectric isolation type semiconductor substrate |
| JPH03250615A (en) * | 1990-02-28 | 1991-11-08 | Shin Etsu Handotai Co Ltd | Manufacture of bonded wafer |
| US5405454A (en) * | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
| JP2010171085A (en) * | 2009-01-20 | 2010-08-05 | Panasonic Electric Works Co Ltd | Semiconductor device and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-03-31 JP JP61070783A patent/JPH0754826B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01181438A (en) * | 1988-01-08 | 1989-07-19 | Toshiba Corp | Manufacture of dielectric-isolation semiconductor substrate |
| JPH02260442A (en) * | 1989-03-30 | 1990-10-23 | Toshiba Corp | Dielectric isolation type semiconductor substrate |
| JPH03250615A (en) * | 1990-02-28 | 1991-11-08 | Shin Etsu Handotai Co Ltd | Manufacture of bonded wafer |
| JPH0680624B2 (en) * | 1990-02-28 | 1994-10-12 | 信越半導体株式会社 | Method for manufacturing bonded wafer |
| US5405454A (en) * | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
| US5543351A (en) * | 1992-03-19 | 1996-08-06 | Matsushita Electric Industrial Co., Ltd. | Method of producing electrically insulated silicon structure |
| JP2010171085A (en) * | 2009-01-20 | 2010-08-05 | Panasonic Electric Works Co Ltd | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0754826B2 (en) | 1995-06-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |