JPH01147912A - Analog voltage generating circuit - Google Patents
Analog voltage generating circuitInfo
- Publication number
- JPH01147912A JPH01147912A JP30717087A JP30717087A JPH01147912A JP H01147912 A JPH01147912 A JP H01147912A JP 30717087 A JP30717087 A JP 30717087A JP 30717087 A JP30717087 A JP 30717087A JP H01147912 A JPH01147912 A JP H01147912A
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- JP
- Japan
- Prior art keywords
- circuit
- switch
- voltage
- voltages
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000470 constituent Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
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- Analogue/Digital Conversion (AREA)
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアナログ電圧生成回路に関し、特に抵抗の分圧
によってアナログ電圧を得るアナログ電圧生成回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog voltage generation circuit, and more particularly to an analog voltage generation circuit that obtains an analog voltage by voltage division of resistors.
従来のアナログ電圧生成回路について図面を参照して説
明する。A conventional analog voltage generation circuit will be explained with reference to the drawings.
第４因は従来のアナログ電圧生成回路の一例を示す回路
図である。The fourth factor is a circuit diagram showing an example of a conventional analog voltage generation circuit.
まず、構成要素について説明する。First, the constituent elements will be explained.
抵抗ラダー回路ＩＤは、電源電圧ＶＤＤ端φ接地電位端
間に直列接続された抵抗値ｒ、の抵抗Ｒ３１２本を備え
、電源電圧ＶＤＤを分圧した複数の電圧をタップＴ Ｏ
” Ｔ １１から出力する。The resistor ladder circuit ID includes 312 resistors R with a resistance value r connected in series between the power supply voltage VDD terminal φ and the ground potential terminal, and taps a plurality of voltages obtained by dividing the power supply voltage VDD.
” Output from T11.
タップＴｌｌ ”電圧ハ（１１／１２ ） Ｖｏｎ テ
ｔｂ ’）、以下タップＴ１゜〜Ｔ１の電圧はそれぞれ
順次（１／１２ ） ＶＤＤづつ低下し、タックＴ０で
接地電位、Ｏｖとなる。The voltage of the tap Tll'' is (11/12) Von ttb'), and the voltages of the taps T1° to T1 sequentially decrease by (1/12) VDD, respectively, and reach the ground potential, Ov, at the tap T0.
スイッチ回路２Ｄは選択信号Ｓ３に基づき、抵抗ラダー
回路ＩＤからの１２個の電圧のうちの１つを選択してア
ナログ電圧ｖ０を出力する。The switch circuit 2D selects one of the 12 voltages from the resistance ladder circuit ID based on the selection signal S3 and outputs the analog voltage v0.
選択論理回路３人は、１２個の電圧の１つを選説明する
。Three selection logic circuits select one of the twelve voltages.
このアナログ電圧生成回路は、選択論理回路３人よ多出
力される選択信号Ｓｇに従って、スイッチ回路２Ｄで抵
抗ラダー回路ＩＤからの１２個の出力電圧のうちから該
当する１つを選択し電圧出力端子ＴＯＵ’ｒよりＯＶ〜
（１１／１２ ） ＶＤｎの範囲のいずれかのアナログ
電圧を出力する構成となっている。This analog voltage generation circuit selects one of the 12 output voltages from the resistance ladder circuit ID using the switch circuit 2D in accordance with the selection signal Sg outputted by the three selection logic circuits, and selects the corresponding one from among the 12 output voltages from the resistance ladder circuit ID. OV from TOU'r~
(11/12) It is configured to output any analog voltage in the range of VDn.
従って、出力する電圧の数と同数の抵抗及びスイッチ素
子を接続しなければならず、ディジタル値のビット数を
ｎとすると ２ｎ個の抵抗及びスイッチ素子と２ｎ本の
接続線を必要とすることになる。Therefore, it is necessary to connect the same number of resistors and switch elements as the number of output voltages, and if the number of bits of the digital value is n, then 2n resistors and switch elements and 2n connection lines are required. Become.
上述した従来のアナログ電圧生成回路は、出力電圧の数
の分だけ抵抗とスイッチ素子及びこれらの接続線を必要
とする構成となっているので、出力電圧の数が多ければ
多いほど、抵抗とスイッチ素子及びこれらの接続線が多
くなり、ＬＳＩ化する場合、チップ面積が大きくなりコ
スト高になるという欠点がある。The conventional analog voltage generation circuit described above is configured to require as many resistors, switch elements, and connection lines for these as there are output voltages, so the larger the number of output voltages, the more resistors and switches The number of elements and their connection lines increases, and when integrated into an LSI, the chip area becomes large and the cost increases.
本発明の目的は、抵抗、スイッチ素子及び接続線の数を
低減することができ、ＬＳＩ化の際、チップ面積を小さ
くすることができ、従ってコストダウンすることができ
るアナログ電圧成生回路を提供することにある。An object of the present invention is to provide an analog voltage generation circuit that can reduce the number of resistors, switch elements, and connection lines, and can reduce the chip area when integrated into an LSI, thereby reducing costs. It's about doing.
本発明のアナログ電圧生成回路は、電源電圧端・接地電
位端間に接続された複数の抵抗をそれぞれ備え電源電圧
を分圧した複数の電圧をそれぞれ出力する第１及び第２
の抵抗ラダー回路ヒ、対応するこれら第１及び第２の抵
抗ラダー回路の複数の出力電圧のうちの１つを選択し互
いに異なる電圧を出力する第１及び第２のスイッチ回路
と、これら第１及び第２のスイッチ回路の出力端間に接
続された複数の抵抗を備えこれら第１及び第２のスイッ
チ回路の出力端間の電圧を分圧した複数の電圧を出力す
る第３の抵抗ラダー回路と、この第３の抵抗ラダー回路
の複数の出力電圧のうちの１つを選択して出力する第３
のスイッチ回路とを有している。The analog voltage generation circuit of the present invention includes first and second resistors each having a plurality of resistors connected between a power supply voltage terminal and a ground potential terminal, and outputting a plurality of voltages obtained by dividing the power supply voltage.
a resistor ladder circuit H, first and second switch circuits that select one of the plurality of output voltages of the corresponding first and second resistor ladder circuits and output mutually different voltages; and a third resistance ladder circuit that includes a plurality of resistors connected between the output terminals of the second switch circuit and outputs a plurality of voltages obtained by dividing the voltage between the output terminals of the first and second switch circuits. and a third resistor ladder circuit that selects and outputs one of the plurality of output voltages of the third resistor ladder circuit.
It has a switch circuit.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
まず、構成要素について説明する。First, the constituent elements will be explained.
第１の抵抗ラダー回路１人は、電源電圧ＶＤＤ端・接地
電位端間に３本の抵抗Ｒ１を備え、電源電圧ＶＤＤを分
圧しり’ｌｌ圧（１／３）ＶＤＤ、 （２／３）ＶＤＤ
。One first resistor ladder circuit includes three resistors R1 between the power supply voltage VDD terminal and the ground potential terminal, and divides the power supply voltage VDD into voltages (1/3) VDD, (2/3) VDD
.
ＶＤＤをタップＴ、１．Ｔ□ＩＴＳ！からそれぞれ出力
する。Tap VDD, 1. T□ITS! Output each from.
第２の抵抗ラダー回路ＩＢは、電源電圧ＶＤＤ端・接地
電位端間に直列接続された３本の抵抗Ｒ１を備え、電源
電圧ＶＤＤを分圧した電圧ＯＶ 、 （１／３ ）ＶＤ
Ｄ＃ （２／３）ＶＤＤヲタｙプＴｏｏ ｐ ＴＨａ
’ｒｕ カらそれぞれ出力する。The second resistance ladder circuit IB includes three resistors R1 connected in series between the power supply voltage VDD terminal and the ground potential terminal, and divides the power supply voltage VDD into voltages OV, (1/3) VD.
D# (2/3) VDD wota Too p THa
'ru Output each file.
第１及び第２のスイッチ回路２人ｅ２Ｂは、それぞれ、
選択信号Ｓ、により対応する第１及び第２抵抗ラダー回
路ＩＡ＊ＩＢの複数の出力電圧のうちの、１つを選択し
、互いに異なる電圧を出力する。The first and second switch circuits e2B are each
One of the plurality of output voltages of the corresponding first and second resistance ladder circuits IA*IB is selected by the selection signal S, and different voltages are output.
第３の抵抗ラダー回路ｌｃは、第１及び第２のスイッチ
回路２ム、２Ｂの出力端間に直列接続された４本の抵抗
Ｒ３を備え、これら第１及び第２のスイッチ回路２人、
２Ｂの出力端間の電圧を分圧した４つの電圧をタップＴ
□〜Ｔａ４から出力する。The third resistance ladder circuit lc includes four resistors R3 connected in series between the output terminals of the first and second switch circuits 2M and 2B.
Tap T to four voltages obtained by dividing the voltage between the output terminals of 2B.
Output from □ to Ta4.
第３のスイッチ回路２ｃは、選択信号Ｓ！により、第３
の抵抗ラダー回路１ｃからの４つの出力電圧のうちの１
つを選択してアナログ電圧Ｖｏを出力する。The third switch circuit 2c receives a selection signal S! According to the third
One of the four output voltages from the resistor ladder circuit 1c of
One is selected and the analog voltage Vo is output.
選択論理回路３は、選択信号Ｓ１． Ｓ、を出力する。The selection logic circuit 3 receives the selection signal S1. Outputs S.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
第１及び第２のスイッチ回路２人、２Ｂは、選択信号Ｓ
、により連動するように女っている。すなわちスイッチ
回路２人で任意の電圧を選択すると、スイッチ回路２Ｂ
においては、スイッチ回路２人で選択した電圧の１段下
、つま’） （１／３ ） ＶＤＤだけ低い電圧が選択
される。Two first and second switch circuits, 2B, have a selection signal S
, I'm a woman who is more interested in you. In other words, when two switch circuits select an arbitrary voltage, switch circuit 2B
In this case, a voltage is selected that is one step lower than the voltage selected by the two switch circuits, and is lower by (1/3) VDD.
そして、抵抗ラダー回路１ｃの両端に印加された電圧は
４等分され、スイッチ回路２゜のによってその１つが選
択される。すなわち（１／１２）Ｖ、Ｄ刻みで出力電圧
を設定することができる。The voltage applied to both ends of the resistance ladder circuit 1c is divided into four equal parts, and one of them is selected by the switch circuit 2. That is, the output voltage can be set in (1/12)V, D increments.
スイッチ回路２人〜２ｃによる抵抗ラダー回路１ム〜１
ｃの電圧（タップ）の選択と出力電圧Ｖｏとの関係を第
１表及び第２図に示す。Resistance ladder circuit 1m-1 with switch circuit 2-2c
Table 1 and FIG. 2 show the relationship between the selection of the voltage (tap) of c and the output voltage Vo.
この実施例において、抵抗ラダー回路１ｃに流れる電流
によって抵抗ラダー回路１人、ＩＢのタップ間の電圧が
変化するのを小さくするために、抵抗Ｒ３の値は抵抗Ｒ
ｔ 、 Ｒｔよシ十分大きな値に設定しておくとよい。In this embodiment, in order to reduce the change in the voltage between the taps of the resistor ladder circuit 1 and IB due to the current flowing through the resistor ladder circuit 1c, the value of the resistor R3 is determined by the resistor R3.
It is preferable to set it to a value that is sufficiently larger than t and Rt.
このように、本実施例においては、合計１０個の抵抗と
１０個のスイッチ素子とによって１２種の電圧を得るこ
とができる。従来の方式で１２種の電圧を得ようとする
と１２個の抵抗と１２個のスイッチ素子が必要であった
のに対し部品数が約１７％も減少している。In this way, in this embodiment, 12 types of voltages can be obtained using a total of 10 resistors and 10 switch elements. When trying to obtain 12 different voltages using the conventional method, 12 resistors and 12 switch elements were required, but the number of components has been reduced by about 17%.
一般に抵抗ラダー回路１人ＩＢをそれぞれｎ個の抵抗で
構成し抵抗ラダー回路１ｃをｍ個の抵抗で構成すると、
出力電圧はｍＸｎ通り得ることができる。その時必要と
なる抵抗数及びスイッチ素子数はそれぞれ（２ｎ＋ｍ）
個となる。In general, if each resistor ladder circuit IB is composed of n resistors and the resistor ladder circuit 1c is composed of m resistors, then
The output voltage can be obtained in mXn ways. The number of resistors and switch elements required at that time are each (2n+m)
Become an individual.
たとえば、２５６種の電圧を得たい時、従来２５６個も
の抵抗とスイッチ素子が必要であるのに対して、本実施
例においては１６Ｘ２＋１６＝４８個で済む。For example, when it is desired to obtain 256 types of voltages, conventionally 256 resistors and switch elements are required, but in this embodiment, only 16×2+16=48 are required.
部品数低減の効果は、ｍ 、 ｎが大きい程顕著である
から、一般に多用される８ビット以上のＤ−Ａ変換器等
に本発明を適用すれば著しい部品数低減効果が得られる
。The effect of reducing the number of parts is more significant as m and n are larger. Therefore, if the present invention is applied to commonly used 8-bit or more D-A converters, a significant effect of reducing the number of parts can be obtained.
第３図は本発明の第２の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
この第２の実施例は第１及び第２の抵抗ラダー回路を１
つの抵抗ラダー回路１に統合し、第１及び第２のスイッ
チ回路２人、２Ｂに対し、第１の実施例と同一の電圧を
供給するようにしたものである。This second embodiment combines the first and second resistor ladder circuits into one
The resistor ladder circuit 1 is integrated into two resistor ladder circuits 1, and the same voltage as in the first embodiment is supplied to the two first and second switch circuits 2B.
この様に、第２の実施例においては、合計７本の抵抗と
１０個のスイッチ素子及びこれらの接続１ｆｓｌＣよっ
て１２種の電圧を得ることができる。これを従来例と比
較するとスイッチ素子数が１７％、抵抗数が４２％も低
減している。In this way, in the second embodiment, 12 types of voltages can be obtained by a total of 7 resistors, 10 switch elements, and their connection 1fslC. Comparing this with the conventional example, the number of switch elements is reduced by 17% and the number of resistors is reduced by 42%.
一般的に第２の実施例の方式においては、抵抗ラダー回
路１をｎ個、抵抗ラダー回路１ｃをｍ個の抵抗で構成す
ると、出力電圧はｍ Ｘ ｎ通り得ることができる。ま
た抵抗数はｎ十ｍ個、スイッチ素子及びその接続線の数
は（２ｎ＋ｍ）個で、第１の実施例の方式と比較して抵
抗数がｎ個低減できるという利点がある。Generally, in the method of the second embodiment, if the resistance ladder circuit 1 is formed of n resistors and the resistance ladder circuit 1c is formed of m resistors, output voltages can be obtained in m x n ways. Further, the number of resistors is n0m, and the number of switch elements and their connection lines is (2n+m), which has the advantage that the number of resistors can be reduced by n compared to the method of the first embodiment.
以上説明したように本発明は、複数の電圧を出力する１
つまたは２つの抵抗ラダー回路と、これら抵抗ラダー回
路の複数の出力電圧のうちの互いに異なる１つをそれぞ
れ選択して出力する２つのスイッチ回路と、これらスイ
ッチ回路の出力端間の電圧を分圧し出力する抵抗ラダー
回路及びこの出力電圧を選択し出力するスイッチ回路と
を設ける構成とすることによシ、抵抗、スイッチ素子及
びこれらの接続線の数を大幅に低減することができ、従
ってＬＳＩ等のチップ面積を小さくすることができ、か
つコストダウンすることができる効果がある。As explained above, the present invention provides a single unit that outputs a plurality of voltages.
one or two resistor ladder circuits, two switch circuits that each select and output one different output voltage from a plurality of output voltages of these resistor ladder circuits, and voltage division between the output terminals of these switch circuits. By providing a configuration including a resistor ladder circuit that outputs and a switch circuit that selects and outputs this output voltage, the number of resistors, switch elements, and their connection lines can be significantly reduced, and therefore LSI etc. This has the effect of reducing the chip area and reducing costs.
第１図は本発明の第１の実施例を示す回路図、第２図は
第１図に示された実施例のスイッチ回路による抵抗ラダ
ー回路の電圧（タップ）選択と出力電圧との関係を示す
特性図、第３図は本発明の第２の実施例を示す回路図、
第４図は従来のアナログ電圧生成回路の一例を示す回路
図である。
１．１人〜ＩＤ・・・・・・抵抗ラダー回路、２ＡＡ／
２Ｄ・・・・・・スイッチ回路、３，３人・・・・・・
選択論理回路、Ｒ１−Ｒ４・・・・・・抵抗。
代理人 弁理士 内 原 晋
粥、ｆ５図FIG. 1 is a circuit diagram showing the first embodiment of the present invention, and FIG. 2 shows the relationship between voltage (tap) selection and output voltage of the resistance ladder circuit by the switch circuit of the embodiment shown in FIG. FIG. 3 is a circuit diagram showing a second embodiment of the present invention,
FIG. 4 is a circuit diagram showing an example of a conventional analog voltage generation circuit. 1.1 person ~ ID...Resistance ladder circuit, 2AA/
2D...Switch circuit, 3, 3 people...
Selection logic circuit, R1-R4...Resistance. Agent: Patent attorney Shinga Uchihara, f5 diagram
Claims (2)
抗をそれぞれ備え電源電圧を分圧した複数の電圧をそれ
ぞれ出力する第１及び第２の抵抗ラダー回路と、対応す
るこれら第１及び第２の抵抗ラダー回路の複数の出力電
圧のうちの１つを選択し互いに異なる電圧を出力する第
１及び第２のスイッチ回路と、これら第１及び第２のス
イッチ回路の出力端間に接続された複数の抵抗を備えこ
れら第１及び第２のスイッチ回路の出力端間の電圧を分
圧した複数の電圧を出力する第３の抵抗ラダー回路と、
この第３の抵抗ラダー回路の複数の出力電圧のうちの１
つを選択して出力する第３のスイッチ回路とを有するこ
とを特徴とするアナログ電圧成生回路。(1) First and second resistor ladder circuits each including a plurality of resistors connected between a power supply voltage terminal and a ground potential terminal and outputting a plurality of voltages obtained by dividing the power supply voltage, and the corresponding first resistor ladder circuits. and first and second switch circuits that select one of the plurality of output voltages of the second resistance ladder circuit and output mutually different voltages, and between the output terminals of these first and second switch circuits. a third resistance ladder circuit that includes a plurality of connected resistors and outputs a plurality of voltages obtained by dividing the voltage between the output terminals of the first and second switch circuits;
One of the plurality of output voltages of this third resistance ladder circuit
and a third switch circuit that selects and outputs one voltage.
ー回路で構成した特許請求の範囲第１項記載のアナログ
電圧生成回路。(2) The analog voltage generation circuit according to claim 1, wherein the first and second resistance ladder circuits are constituted by one resistance ladder circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30717087A JPH01147912A (en) | 1987-12-03 | 1987-12-03 | Analog voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30717087A JPH01147912A (en) | 1987-12-03 | 1987-12-03 | Analog voltage generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01147912A true JPH01147912A (en) | 1989-06-09 |
Family
ID=17965877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30717087A Pending JPH01147912A (en) | 1987-12-03 | 1987-12-03 | Analog voltage generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01147912A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132828A (en) * | 1992-10-14 | 1994-05-13 | Mitsubishi Electric Corp | D/a converter |
| KR100579537B1 (en) * | 1997-06-02 | 2006-09-22 | 세이코 엡슨 가부시키가이샤 | Digital-to-analog converters, circuit boards, electronics and liquid crystal displays |
| JP2007195018A (en) * | 2006-01-20 | 2007-08-02 | Oki Electric Ind Co Ltd | Digital/analog converter |
| JP2009005051A (en) * | 2007-06-21 | 2009-01-08 | Sanyo Electric Co Ltd | Da conversion circuit |
| US7919931B2 (en) | 2005-04-26 | 2011-04-05 | Epson Imaging Devices Corporation | LED driving circuit, illuminating device, and electro-optical device |
| JP2016096497A (en) * | 2014-11-17 | 2016-05-26 | ラピスセミコンダクタ株式会社 | Equalizer circuit and semiconductor integrated device |
-
1987
- 1987-12-03 JP JP30717087A patent/JPH01147912A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132828A (en) * | 1992-10-14 | 1994-05-13 | Mitsubishi Electric Corp | D/a converter |
| KR100579537B1 (en) * | 1997-06-02 | 2006-09-22 | 세이코 엡슨 가부시키가이샤 | Digital-to-analog converters, circuit boards, electronics and liquid crystal displays |
| US7919931B2 (en) | 2005-04-26 | 2011-04-05 | Epson Imaging Devices Corporation | LED driving circuit, illuminating device, and electro-optical device |
| JP2007195018A (en) * | 2006-01-20 | 2007-08-02 | Oki Electric Ind Co Ltd | Digital/analog converter |
| KR101243169B1 (en) * | 2006-01-20 | 2013-03-13 | 오끼 덴끼 고오교 가부시끼가이샤 | Digital-analog converter |
| JP2009005051A (en) * | 2007-06-21 | 2009-01-08 | Sanyo Electric Co Ltd | Da conversion circuit |
| JP2016096497A (en) * | 2014-11-17 | 2016-05-26 | ラピスセミコンダクタ株式会社 | Equalizer circuit and semiconductor integrated device |
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