JPH01138718A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01138718A JPH01138718A JP29726287A JP29726287A JPH01138718A JP H01138718 A JPH01138718 A JP H01138718A JP 29726287 A JP29726287 A JP 29726287A JP 29726287 A JP29726287 A JP 29726287A JP H01138718 A JPH01138718 A JP H01138718A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- substrate
- plating
- type
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000007747 plating Methods 0.000 claims abstract description 53
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 abstract description 4
- 239000003792 electrolyte Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 8
- 238000007738 vacuum evaporation Methods 0.000 description 7
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体基板上の電極取り出し部の形成方法に関電極取り
出し部のステンプカバレージを良好にすると共に電極取
り出し部の埋め込み金属と半４体基板との密着性および
バリヤー性を向上させることを目的とし。[Detailed Description of the Invention] [Summary] A method for forming an electrode lead-out portion on a semiconductor substrate involves improving the stamp coverage of the electrode lead-out portion and improving the adhesion between the embedded metal of the electrode lead-out portion and the semi-quadrite substrate. The purpose is to improve barrier properties.
半導体基板の上に形成された絶縁膜に設けられた開孔部
中に、電極取り出し用の金属をメッキにより析出させる
半導体装置の製造方法において。In a method of manufacturing a semiconductor device, a metal for taking out an electrode is deposited by plating into an opening provided in an insulating film formed on a semiconductor substrate.
開孔部に、半導体とメッキ金属の双方に相性が良くかつ
メッキ金属が半導体基板に拡散するのを防ぐ能力を有す
るバリヤ−メタルを付着させ、その上に電極取り出し用
の金属をメッキにより析出させてメッキ膜を形成するよ
うに構成する。A barrier metal that is compatible with both the semiconductor and the plating metal and has the ability to prevent the plating metal from diffusing into the semiconductor substrate is attached to the opening, and a metal for taking out the electrode is deposited on it by plating. to form a plating film.
本発明は、半導体装置の製造方法、特に半導体基板上の
電極取り出し部の形成方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an electrode lead-out portion on a semiconductor substrate.
現在、ｌ４Ｓｌ配線材料として、ΔｌまたはＡ１合金が
用いられ、その３膜形成方法として真空蒸着やスパッタ
リングが用いられている。Currently, Δl or A1 alloy is used as the l4Sl wiring material, and vacuum evaporation and sputtering are used as methods for forming the three films.
素子の高集積度化、高密度化が進むにつれて。As devices become more highly integrated and densely packed.
ＡＩ配線を行うべき下地の段差形状が厳しくなってきて
いる。すなわち、アスペクト比（段差の高さと開花部の
大きさとの比）が大きくなってきている。このため、良
好なステップカバレージを持ったＡＩ膜を形成すること
が困難になってきている。The shape of the step on the base for AI wiring is becoming stricter. In other words, the aspect ratio (the ratio between the height of the step and the size of the flowering part) is increasing. For this reason, it has become difficult to form an AI film with good step coverage.
この傾向は、多層配線構造を持つ素子ではより深刻であ
る。This tendency is more serious in devices having a multilayer wiring structure.
第５図は、従来例を示す図である。 FIG. 5 is a diagram showing a conventional example.
第５図において、６１はＰ型Ｓｉ基板、６２はＰ型Ｓｉ
基板６１の表面に形成されたＮ゛型領領域６３はＰ型Ｓ
ｉ基板６１とＮ°型領領域６２で形成されたＰＮ接合、
６４はＰ型Ｓｉ基板６１上に形成され、 ＳｉＯ２，Ｐ
ＳＧ等からなる絶縁膜、６５は絶縁膜６４中に形成され
た電極取り出し用の開孔部。In FIG. 5, 61 is a P-type Si substrate, 62 is a P-type Si substrate, and 62 is a P-type Si substrate.
The N-type region 63 formed on the surface of the substrate 61 is a P-type S
A PN junction formed by the i-substrate 61 and the N° type region 62,
64 is formed on the P-type Si substrate 61, SiO2, P
An insulating film made of SG or the like, 65 is an opening formed in the insulating film 64 for taking out an electrode.
６６はＡＩ＆！線である。66 is AI&! It is a line.
従来、＾ｌ配線６６は、真空蒸着やスパッタリングによ
りＡＩを半導体基板の上面から堆積した後。Conventionally, the wiring 66 is formed after AI is deposited from the top surface of the semiconductor substrate by vacuum evaporation or sputtering.
バクーニングして形成していた。It was formed by bakuning.
従来の方法では、第５図に示したように、開花部６５の
アスペクト比が大きい場合、 ＡＩ配線６６に断線、陥
没、盛り上がり等が生じてステップカバレージが良くな
いという問題が生じていた。In the conventional method, as shown in FIG. 5, when the aspect ratio of the flowering part 65 is large, the AI wiring 66 is broken, depressed, bulged, etc., resulting in poor step coverage.
本発明は、ステップカバレージが良好な電極取り出し部
を形成することができるようにすると共に電極取り出し
部の埋め込み金属と半導体基板との密着性およびバリヤ
ー性を向上させた半導体装置の製造方法を提供すること
を目的とする。The present invention provides a method for manufacturing a semiconductor device that enables the formation of an electrode lead-out part with good step coverage and improves the adhesion and barrier properties between the embedded metal of the electrode lead-out part and a semiconductor substrate. The purpose is to
本発明は、電極取り出し用の開孔部の底面の半導体基板
の上から、電解メッキにより、半導体および配線用の金
属の双方になじみ易い金属を析出させて開孔部を充填し
た後１表面に配線用の金属を堆積させれば、開花部のス
テップカバレージが良好になるという知見に基づいてな
されたものである。In the present invention, a metal that is compatible with both the semiconductor and wiring metal is deposited from the top of the semiconductor substrate at the bottom of the hole for taking out the electrode by electrolytic plating, and the hole is filled with a metal that is easily compatible with both the semiconductor and the metal for wiring. This was done based on the knowledge that step coverage in the flowering area would be improved if metal for wiring was deposited.
しかしながら、半導体基板に直接メッキ膜を形成すると
、密着性が悪＜、！１．ｌ＋かれてしまうという問題が
ある。However, when a plating film is formed directly on a semiconductor substrate, the adhesion is poor! 1. There is a problem that l+ is lost.
そこで１本発明では、予め、電極取り出し用の開花部に
、半導体とメッキ金属の双方に相性が良いと共にメッキ
金属が半導体基板に拡散するのを防ぐ能力を有するバリ
ヤ−メタルを付着させた後にメッキを行うことにより、
上記の問題を解決した。Therefore, in the present invention, a barrier metal that is compatible with both the semiconductor and the plating metal and has the ability to prevent the plating metal from diffusing into the semiconductor substrate is attached to the flowering part for taking out the electrode in advance, and then the plating is performed. By doing
Solved the above problem.
第１図（ａ）および（ｂ）は１本発明の原理説明図であ
る。FIGS. 1(a) and 1(b) are diagrams explaining the principle of the present invention.
第１図（ａ）および（ｂ）において、１はＰ型半導体基
板、２はＰ型半専体基Ｆｉ１の表面に形成されたＮ゛型
領領域３はＰ型半導体基板１およびＮ゛型領領域２で形
成されたＰＮ接合、４は絶縁膜、５は絶縁膜４中に設け
られた電極取り出し用の開孔部、６は開孔部５の内面に
形成された。半導体とメッキ金属の双方に相性が良いと
共にメッキ金属が半導体基板に拡散するのを防ぐ能力を
有するバリヤ−メタル５７は開孔部５に析出されたメッ
キ膜である。In FIGS. 1(a) and (b), 1 is a P-type semiconductor substrate, 2 is an N-type region 3 formed on the surface of a P-type semi-dedicated group Fi1, and 2 is a P-type semiconductor substrate 1 and an N-type region 3 formed on the surface of a P-type semi-dedicated group Fi1. A PN junction was formed in the region 2, 4 was an insulating film, 5 was an opening provided in the insulating film 4 for taking out an electrode, and 6 was formed on the inner surface of the opening 5. The barrier metal 57 is a plating film deposited in the opening 5, which is compatible with both the semiconductor and the plating metal and has the ability to prevent the plating metal from diffusing into the semiconductor substrate.
まず、第１図（ａ）に示すように、絶縁膜４中に形成さ
れた電極取り出し用の開孔部５に半導体とメッキ金属の
双方に相性が良くかつメッキ金属が半導体基板に拡散す
るのを防ぐ能力を有するバリヤ−メタル６を付着させた
後、Ｐ型半導体基板１を負電位にして９メッキ金属の電
解液中に浸して電解メッキを行う。First, as shown in FIG. 1(a), the opening 5 for taking out the electrode formed in the insulating film 4 has good compatibility with both the semiconductor and the plating metal, and the plating metal can diffuse into the semiconductor substrate. After depositing a barrier metal 6 having the ability to prevent this, the P-type semiconductor substrate 1 is brought to a negative potential and immersed in an electrolytic solution for plating metal to perform electrolytic plating.
この際、電極取り出し用の開花部５の下に、第１図に示
すように、Ｎ゛型領領域２設けられている場合に問題が
生じる。すなわち、電解メッキの際に、Ｐ型半導体基板
１は常に負の電位にされるので、Ｐ型半導体基板１とＮ
゛型領領域２で形成されるＰＮ接合３は逆バイアスされ
、電流がほとんど流れず、したがって、メッキ金属はほ
とんど析出されない。At this time, a problem arises when an N-shaped area 2 is provided below the flowering part 5 for taking out the electrode, as shown in FIG. That is, during electrolytic plating, since the P-type semiconductor substrate 1 is always brought to a negative potential, the P-type semiconductor substrate 1 and the N
The PN junction 3 formed in the ゛-type region 2 is reverse biased so that little current flows, and therefore little plating metal is deposited.
この問題は、Ｐ型半導体基板１に光を照射することによ
り、ＰＮ接合３の逆方向電流を増加させてメッキ生長を
生じさせることにより解決することができる。This problem can be solved by irradiating the P-type semiconductor substrate 1 with light to increase the reverse current in the PN junction 3 and cause plating growth.
Ｐ型半導体基板１に光を照射する場合、Ｐ型半導体基Ｆ
ｉ、１の表面には鞄緑膜４や析出金属等があるので、光
の照射は、Ｐ型半導体基板１の背面から行う。When irradiating light onto the P-type semiconductor substrate 1, the P-type semiconductor substrate F
Since there is a bag green film 4, precipitated metal, etc. on the surface of i, 1, the light irradiation is performed from the back side of the P-type semiconductor substrate 1.
Ｐ型半導体基板Ｉの背面から照射された光は。The light irradiated from the back side of the P-type semiconductor substrate I is.
Ｐ型半導体基板１に吸収され、ＰＮ接合３に到達し、Ｐ
Ｎ接合３の逆方向電流を増加させる。これにより、電極
取り出し用の開孔部５の底面からメッキが生長し、第１
図（ｂ）に示すようにメッキ膜７が形成される。It is absorbed into the P-type semiconductor substrate 1, reaches the PN junction 3, and P
The reverse current of N junction 3 is increased. As a result, the plating grows from the bottom of the opening 5 for taking out the electrode, and the first
A plating film 7 is formed as shown in Figure (b).
この後、メッキ膜７の表面に、メッキ金属および配線金
属の双方に相性の良い金属を付着させ。Thereafter, a metal compatible with both the plating metal and the wiring metal is attached to the surface of the plating film 7.
その上に配線金属を堆積させた後、バターニングを行っ
て金属配線を形成する。After depositing wiring metal thereon, patterning is performed to form metal wiring.
（実施例１） 第２図は、実施例１を示す図である。 (Example 1) FIG. 2 is a diagram showing the first embodiment.
本実施例は、半導体基板表面の全面に付着させたバリヤ
−メタルのうち開孔部以外の部分を、開孔部に設けたレ
ジストをマスクにしてエツチングにより除去した後、レ
ジストを除去し、バリヤ−メタルの上にメッキを行うも
のである。In this example, the portions of the barrier metal adhered to the entire surface of the semiconductor substrate other than the openings are removed by etching using the resist provided in the openings as a mask, and then the resist is removed and the barrier metal is removed. - Plating is performed on metal.
第２図において、２１はＰ型Ｓｉ基板、２２はＰ型Ｓｉ
基板２１の表面に設けられたＮ゛型領領域２３はＰ型Ｓ
ｉ基板２１およびＮ゛型領領域２２で形成されるＰＮ接
合、２４はＰＳＧ膜、２５はバリヤ−メタルとしてのＴ
ｉＷ、２６はレジスｌ−，２７はＡｕメッキ膜、２８は
メッキ金属および配線金属の双方と相性の良い金属とし
てのＴｉＷ、２９はＡＩ配線である。In FIG. 2, 21 is a P-type Si substrate, 22 is a P-type Si substrate, and 22 is a P-type Si substrate.
The N-type region 23 provided on the surface of the substrate 21 is a P-type S
A PN junction formed by an i-substrate 21 and an N-type region 22, 24 a PSG film, and 25 a T film as a barrier metal.
iW, 26 is a resist l-, 27 is an Au plating film, 28 is TiW as a metal that is compatible with both the plating metal and the wiring metal, and 29 is an AI wiring.
以下、第２図に基づいて２本実施例を詳細に説明する。Hereinafter, two embodiments will be described in detail based on FIG.
■ 表面が電極取り出し用の開孔部を有する厚さ１μｍ
のＰＳＧ膜２４で覆われ、Ｎ′領域２２が設けられたＰ
型Ｓｉ基板２１の表面全体に真空蒸着やスパッタリング
によりＴｉＷ２５を２０００大の厚さに堆積させる。■ 1 μm thick surface with openings for electrode extraction
P is covered with a PSG film 24 and provided with an N' region 22.
TiW 25 is deposited to a thickness of 2000 mm over the entire surface of the type Si substrate 21 by vacuum evaporation or sputtering.
■ 電極取り出し用の開孔部およびその周囲をレジスト
２６で覆う。(2) Cover the opening for taking out the electrode and its surroundings with a resist 26;
■ レジスト２６をマスクとして５電極取り出し部およ
びその周囲を残してＴｉＷ２５をエツチングにより除去
する。(2) Using the resist 26 as a mask, the TiW 25 is removed by etching, leaving the 5-electrode extraction portion and its surroundings.
■ レジスト２６をｆｆ１ｌＸ’ｌｆする。■ Perform ff1lX'lf on the resist 26.
■ Ｐ型Ｓｉ基板２１を、基板側を負電位にしてＡｕの
電解液中に浸してＴｉＷ２５の上にＡｕをメッキ生長さ
せてＡｕメッキ膜２７を形成する。(2) A P-type Si substrate 21 is immersed in an Au electrolyte with the substrate side set to a negative potential, and Au is plated and grown on the TiW 25 to form an Au plating film 27.
この時、Ｐ型Ｓｉ基板２１は負電位であるから。At this time, the P-type Si substrate 21 is at a negative potential.
Ｐ型Ｓｉ基板２１とＮ″領域２２とで形成されるＰＮ接
合２３は逆バイアスとなり、電流がほとんど流れない。The PN junction 23 formed by the P-type Si substrate 21 and the N'' region 22 is reverse biased, and almost no current flows.
そこで、Ｐ型Ｓｔ基板２１の背面から光を照射してＰＮ
接合２３の逆方向電流を増大させてＡｕのメッキ生長を
行う。Therefore, light is irradiated from the back side of the P-type St substrate 21 to form a PN
The reverse current in the junction 23 is increased to cause Au plating to grow.
１例として、電流密度２ ｍ Ａ ／ ｃｄで１０分間
メッキ生長を行った場合、 Ａｕメッキ膜２７は０．５
μｍの厚さに形成された。As an example, when plating is grown for 10 minutes at a current density of 2 mA/cd, the Au plating film 27 is 0.5 mA/cd.
It was formed to a thickness of μm.
■ Ａｕメッキ膜２７が形成されたＰ型Ｓｉ基板２１の
表面全体にＡｕおよび配線金属である八１の双方に相性
の良い金属としてＴｉＷ２８を真空蒸着やスパッタリン
グにより、２．０００人の１１さにｔｌ積させた後、バ
ターニングを行う。■ On the entire surface of the P-type Si substrate 21 on which the Au plating film 27 has been formed, TiW 28, which is a metal that is compatible with both Au and the wiring metal 81, is deposited on 2,000 11 layers by vacuum evaporation or sputtering. After tl stacking, buttering is performed.
■ 基板表面全体に配線金属であるＡＩを真空蒸着やス
パッタリングにより、１μｍの厚さに堆積させた後、バ
ターニングを行ってＡＩ配線２９を形成する。(2) AI, which is a wiring metal, is deposited on the entire surface of the substrate to a thickness of 1 μm by vacuum evaporation or sputtering, and then patterning is performed to form an AI wiring 29.
以上の説明ではバリヤ−メタルとしてＴｉＷを用いた場
合を示したが、バリヤ−メタルとしては。In the above explanation, the case where TiW was used as the barrier metal was shown, but as the barrier metal.
ＴｉＷの他に、 Ｔｉ、Ｎｉ、ＴｉＮ、Ｃｒ＋Ｐｄ、Ｃ
ｕ、Ｐｔ等が用いられる。Besides TiW, Ti, Ni, TiN, Cr+Pd, C
U, Pt, etc. are used.
（実施例２） 第３図は、実施例２を示す図である。(Example 2) FIG. 3 is a diagram showing the second embodiment.
本実施例は、半導体基板表面の全面にバリヤ−メタルを
付着させ、開孔部以外の部分にレジストを設け、この状
態で開孔部にメッキを行い、その後、レジストを剥離し
、形成されたメッキ膜をマスクとして余分のバリヤ−メ
タルをエツチングにより除去するものである。In this example, a barrier metal is attached to the entire surface of the semiconductor substrate, a resist is provided on the part other than the opening, plating is performed on the opening in this state, and then the resist is peeled off. Excess barrier metal is removed by etching using the plating film as a mask.
第３図において、３１はＰ型Ｓｉ基板、３２はＰ型Ｓｉ
基板３１の表面に設けられたＮ°型領領域３３はＰ型Ｓ
ｉ基板３１およびＮ゛型領領域３２で形成されるＰＮ接
合、３４はＰＳＧ膜、３５はバリヤ−メタルとしてのＴ
ｉＷ、３６はレジスト、３７はＡｕメッキ膜、３８はメ
ッキ金属および配線金属の双方と相性の良い金属として
のＴｉＷ、３９はＡｔ配線である。In FIG. 3, 31 is a P-type Si substrate, 32 is a P-type Si substrate, and 32 is a P-type Si substrate.
The N° type region 33 provided on the surface of the substrate 31 is a P type S
A PN junction formed by an i-substrate 31 and an N-type region 32, 34 a PSG film, and 35 a T film as a barrier metal.
iW, 36 is a resist, 37 is an Au plating film, 38 is TiW as a metal that is compatible with both the plating metal and the wiring metal, and 39 is an At wiring.
以下、第３図に基づいて９本実施例を詳細に説明する。Hereinafter, nine embodiments will be described in detail based on FIG.
■ 表面が電極取り出し用の開花部を存する。厚さ１μ
ｍのＰＳＧ膜３４で覆われ、Ｎ″領域３２が設けられた
Ｐ型Ｓ１基板３１の表面全体に真空７着やスパッタリン
グによりＴｉＷ３５を２０００人の厚さに堆積させる。■ The surface has a flowering part for taking out the electrode. Thickness 1μ
TiW 35 is deposited to a thickness of 2,000 nm over the entire surface of the P-type S1 substrate 31 covered with a PSG film 34 of 2,000 nm and provided with an N'' region 32 by vacuum deposition or sputtering.
■ 電極取り出し用の開花部およびその周囲を残してレ
ジスト３６を塗布する。■ Apply resist 36, leaving the flowering part and its surroundings for electrode extraction.
■ Ｐ型Ｓｉ基板３１を、基板側を負電位にしてＡｕの
電解液中に浸してＴｉＷ３５の上にＡｕをメッキ生長さ
せてＡｕメッキ膜３７を形成する。(2) A P-type Si substrate 31 is immersed in an Au electrolyte with the substrate side set to a negative potential, and Au is plated and grown on the TiW 35 to form an Au plating film 37.
この時、Ｐ型Ｓｉ基板３１が負電位であるから。At this time, the P-type Si substrate 31 is at a negative potential.
Ｐ型Ｓｉｉ板３１とＮ Ｉ ｈｐ域３２とで形成される
ＰＮ接合３３は逆バイアスとなり、電流がほとんど流れ
ない。そこで、Ｐ型Ｓｉ％仮３１の背面から光を照射し
てＰＮ接合３３の逆方向電流を増大させてＡｕのメッキ
生長を行う。The PN junction 33 formed by the P-type Sii plate 31 and the N I hp region 32 is reverse biased, and almost no current flows. Therefore, light is irradiated from the back side of the P-type Si% temporary 31 to increase the reverse current in the PN junction 33 to grow Au plating.
１例として５電流密度２ ｍ Ａ ／ ｃｆｆｌで１０
分間メッキ生長を行った場合、０．５μｍの厚さのＡｕ
メッキ膜３７が形成できた。10 at a current density of 2 mA/cffl as an example
When plating growth is performed for minutes, Au with a thickness of 0.5 μm
A plating film 37 was formed.
■ レジスト３６を剥離する。■ Peel off the resist 36.
■ Ａｕメッキ膜３７をマスクとして余分のＴｉＷ３５
をエツチングにより除去する。■ Using the Au plating film 37 as a mask, remove extra TiW 35
is removed by etching.
■ Ａｕメッキ膜３７が形成されたＰ型Ｓｉ基板３Ｉの
表面全体にＡｕおよび配線金属であるＡＩの双方に相性
の良い金属としてＴｉＷ３８を真空蒸着やスパッタリン
グにより、２０００人の厚さに堆積させた後、バターニ
ングを行う。■ On the entire surface of the P-type Si substrate 3I on which the Au plating film 37 was formed, TiW 38, a metal that is compatible with both Au and the wiring metal AI, was deposited to a thickness of 2000 nm by vacuum evaporation or sputtering. Afterwards, perform buttering.
■ 基板表面全体に配線金属であるＡＩを真空蒸着やス
パッタリングにより、１μｍの厚さに堆積させた後、パ
ターニングを行ってＡｔ配線３９を形成する。(2) After depositing AI, which is a wiring metal, on the entire surface of the substrate to a thickness of 1 μm by vacuum evaporation or sputtering, patterning is performed to form an At wiring 39.
以上の説明ではバリヤ−メタルとしてＴｉＷを用いた場
合を示したが、バリヤ−メタルとしては。In the above explanation, the case where TiW was used as the barrier metal was shown, but as the barrier metal.
ＴＮＲ／の他に、Ｔｉ、Ｎ＋＋Ｔ＋）１．Ｃｒ、Ｐｄ、
Ｃｕ、Ｐｔ等が用いられる。In addition to TNR/, Ti, N++T+)1. Cr, Pd,
Cu, Pt, etc. are used.
（実施例３） 第４図は、実施例３を示す図である。(Example 3) FIG. 4 is a diagram showing the third embodiment.
本実施例は４本発明を、電極取り出し部の下池が半導体
基板ばかりでなく、配線金属の場合にも適用したもので
ある。In this embodiment, the present invention is applied not only to a semiconductor substrate but also to a case where the lower layer of the electrode lead-out portion is a metal wiring.
第４図において、４１はＰ型Ｓｉ基板、４２はＰ型Ｓｉ
基板４１の表面に設けられたＮ゛型領領域４３はＰ型Ｓ
ｉ基板４１およびＮ°型領領域４２より形成されるＰＮ
接合、４４はＰＳＧ膜、４５はバリヤ−メタルとしての
ＴｉＷ、４６はＡｕメッキ膜。In FIG. 4, 41 is a P-type Si substrate, 42 is a P-type Si substrate, and 42 is a P-type Si substrate.
The N-type region 43 provided on the surface of the substrate 41 is a P-type S
PN formed by the i-substrate 41 and the N° type region 42
44 is a PSG film, 45 is TiW as a barrier metal, and 46 is an Au plating film.
４７は篩メッキ４６および配線金属の双方と相性の良い
金属としてのＴｉＷ、４８はＡｔ配線、４９はＰ型Ｓｉ
基板に直接設けられたＡＩ！ｉ！線、５０はｐｓＧ膜、
５１はＡｔ配線４９上に被着されたバリヤ−メタルとし
てのＴｉＷ、５２はＡｕメッキ膜、５３はメッキ金属お
よび配線金属の双方と相性の良い金属としてのＴｉＷ、
５４はＡｔ配線である。47 is TiW as a metal that is compatible with both the sieve plating 46 and the wiring metal, 48 is At wiring, and 49 is P-type Si.
AI installed directly on the board! i! line, 50 is psG film,
51 is TiW as a barrier metal deposited on the At wiring 49; 52 is an Au plating film; 53 is TiW as a metal compatible with both the plating metal and the wiring metal;
54 is an At wiring.
本実施例では、第４図の左側に示した電極取り出し部は
、実施例１および実施例２と同様に半導体基板の上から
形成されているが、右側に示した電極取り出し部は、
Ａｔ配線の上から形成されている。In this example, the electrode lead-out portion shown on the left side of FIG. 4 is formed from above the semiconductor substrate as in Examples 1 and 2, but the electrode lead-out portion shown on the right side
It is formed from above the At wiring.
このように１本発明は、メッキ金属が析出する下地が半
導体基板でなく、配線金属であっても適用することがで
きる。As described above, the present invention can be applied even if the base on which the plating metal is deposited is not a semiconductor substrate but a wiring metal.
したがって、多層配線の形成に有用である。Therefore, it is useful for forming multilayer wiring.
以上の説明ではバリヤ−メタルとしてＴｉＷを用いた場
合を示したが、バリヤ−メタルとしては。In the above explanation, the case where TiW was used as the barrier metal was shown, but as the barrier metal.
ＴｔＷの他に、 Ｔｉ、Ｎｉ＋ＴｉＮ＋Ｃｒ、Ｐｄ、Ｃ
ｕ、Ｐｔ等が用いられる。In addition to TtW, Ti, Ni+TiN+Cr, Pd, C
U, Pt, etc. are used.
本発明によれば、ステンプカバレージが良好な電極取り
出し部を形成することができると共に電極取り出し部の
埋め込み金属と半導体基板との密着性およびバリヤー性
を向上させることができる。According to the present invention, it is possible to form an electrode lead-out portion with good stamp coverage, and it is also possible to improve the adhesion and barrier properties between the embedded metal of the electrode lead-out portion and the semiconductor substrate.
第１図は本発明の原理説明図、第２図は実施例１を示す
回、第３図は実施例２を示す図、第４図は実施例３を示
す図、第５図は従来例を示す図である。
第１図において
ｌａｐ型半導体基板
２：Ｎ゛型領領
域：ＰＮ接合
４：絶縁膜
５：開孔部
６：バリヤ−メタル
７；メッキ膜Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing the first embodiment, Fig. 3 is a diagram showing the second embodiment, Fig. 4 is a diagram showing the third embodiment, and Fig. 5 is a conventional example. FIG. In FIG. 1, a lap type semiconductor substrate 2: an N-type region: a PN junction 4: an insulating film 5: an opening 6: a barrier metal 7; a plating film
Claims (1)
けられた開孔部（５）中に、電極取り出し用の金属をメ
ッキにより析出させる半導体装置の製造方法において、 開孔部（５）に、半導体とメッキ金属の双方に相性が良
くかつメッキ金属が半導体基板（１）に拡散するのを防
ぐ能力を有するバリヤ−メタル（６）を付着させ、その
上に電極取り出し用の金属をメッキにより析出させてメ
ッキ膜（７）を形成することを特徴とする半導体装置の
製造方法。[Claims] A method for manufacturing a semiconductor device, in which a metal for taking out an electrode is deposited by plating into an opening (5) provided in an insulating film (4) formed on a semiconductor substrate (1). A barrier metal (6) that is compatible with both the semiconductor and the plating metal and has the ability to prevent the plating metal from diffusing into the semiconductor substrate (1) is attached to the opening (5), and then A method for manufacturing a semiconductor device, comprising depositing a metal for taking out an electrode by plating to form a plating film (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29726287A JPH01138718A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29726287A JPH01138718A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01138718A true JPH01138718A (en) | 1989-05-31 |
Family
ID=17844246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29726287A Pending JPH01138718A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01138718A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006523025A (en) * | 2003-04-10 | 2006-10-05 | サンパワー コーポレイション | Metal contact structure for solar cell and manufacturing method |
-
1987
- 1987-11-25 JP JP29726287A patent/JPH01138718A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006523025A (en) * | 2003-04-10 | 2006-10-05 | サンパワー コーポレイション | Metal contact structure for solar cell and manufacturing method |
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