JPS58134428A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58134428A JPS58134428A JP57018504A JP1850482A JPS58134428A JP S58134428 A JPS58134428 A JP S58134428A JP 57018504 A JP57018504 A JP 57018504A JP 1850482 A JP1850482 A JP 1850482A JP S58134428 A JPS58134428 A JP S58134428A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- electrolytic plating
- electrode
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、％に半導体装
置の多層厚メツキ電極の形成方法の改良に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in a method for forming a multi-layer thick plating electrode for a semiconductor device.
以下、半導体基板として砒化ガリウム（ＧａＡｅ）を用
いたショットキバリアゲート構造ＧａＡａ電界効果トラ
ンジスタ（ＧａＡｓ ＭＢ２７ＥＴ） において、特に
７リツプチツプ構造を例にとって説明を行う。In the following, a Schottky barrier gate structure GaAa field effect transistor (GaAs MB27ET) using gallium arsenide (GaAe) as a semiconductor substrate will be explained, particularly taking a 7-lip chip structure as an example.
フリップチップ構造ＧａＡ・ＭＢ２１ＦＥＴはＸ帯以上
の高周波帯において高利得をもたせるのに有効で、しか
も量産性に優れる等の多くの利点を有している事は周知
である。特に前者はボンディングワイヤを介さずＦＩＴ
チップが、ＩＩ′ｌｌ１Ｔパッケージに倒置形で直接熱
圧着またはハンダ材を介しての溶接により接着されるこ
とによる寄生インダクタンス及び熱抵抗の低減効果に依
り、後者祉ボンディング作業性の向上等の利点に依る所
が大である。It is well known that the flip-chip structure GaA/MB21FET is effective in providing high gain in high frequency bands above the X band, and has many advantages such as being excellent in mass production. In particular, the former is FIT without using bonding wires.
Due to the effect of reducing parasitic inductance and thermal resistance due to the fact that the chip is bonded to the II'll1T package upside down by direct thermocompression bonding or welding via solder material, the latter has advantages such as improved bonding workability. A lot depends on it.
ところで、この種のＦＩＣ？構造では、ＦＩＴチップ上
のソース、ゲートおよびドレインの条電極の所望の部分
ＫＳＩＦＩＣ？パッケージとの熱圧着またはハンダ材に
よる溶接のための中間接着導体として、多層厚メツキ電
極層を選択的に形成することが不可欠となる。By the way, this kind of FIC? In the structure, the desired portions of the source, gate and drain strip electrodes on the FIT chip KSIFIC? It is essential to selectively form a multi-thick plating electrode layer as an intermediate adhesive conductor for thermocompression bonding or welding with a solder material to the package.
従来、この種の多層厚メツキ電極形成法の一例として第
１図（ａ）〜（ｊ）の主要工程における断面図に示すよ
うな方法があった。Conventionally, there has been a method as shown in cross-sectional views of main steps in FIGS. 1(a) to 1(j) as an example of this type of method for forming a multi-layer thick plating electrode.
尚、以下に述べる方法は、ソース電極上のみに厚メツキ
電極を形成する場合についてであり、ゲートおよびドレ
イン電極上については同様であるため省略する。Note that the method described below is for forming a thick plating electrode only on the source electrode, and the method for forming the thick plating electrode on the gate and drain electrodes is omitted because it is the same.
この方法では、先ず第１図（ａ）に示すように半艶□。In this method, first, as shown in FIG. 1(a), a semi-gloss square is formed.
１．８□（１１，、、、ヮうゎえ屓・ｌ’Ｗ ｆｉ 。1.8□(11,...
１．６や、ヶ。1.6 or so.
（２）の表面に、ソース電極（３）、ゲート電極（図示
省略）、およびドレイン電極（図示省略）を所定の間隔
で設け、第１図（（９）に示すように、ソース電極（８
）の一部を残し他をレジスト層（４）で被覆する０その
後、第１図（０）に示すように、周知の蒸着法によりバ
リアメタル金属層（６）管形成し、続いてリフトオフエ
Ｓを経て第１図（〜に示すような構造を得る０バリアメ
タル金属層（５）は、主に動作時における素子の温度上
昇または環境温度の上昇に起因する電極構成材料間の熱
的反応を抑制し、素子の高信頼度化を達成するために形
成するものである。バリアメタル金属層（６）形成後、
第１図（、）に示すように１バリアメタル金属層（６）
の一部を露出させ他を下敷レジスト層（６）で被覆する
。その後、第１図（ｆ）に示すように、蒸着法により電
解メッキ用下地金属層（７）を形成し、続いて、第１図
（−に示すように、バリアメタル金属層［１１上の下敷
レジスト層（６）の開孔部に対応する箇所を残し他を表
面レジスト層（８）で被覆する。しかる１後、第１図（
ｈ）に示すように、電解メッキ用下地金：菖層（ｙｌを
電極として表面レジスト層（３）の開孔部に電解メッキ
法により厚メッキ層（９）を形成する。その後、表面レ
ジスト層（８）を除去しく第１図（ｉ） ） 、電解メ
ッキ用下地金属層（７）および下敷レジスト層（６）の
除去を順次行い、ｊＲ１図（、＋）Ｋ示すような構造を
得ていた〇
しかしながら、この様な従来法では、ソース電極（３）
と厚メッキ層（９）との間に、バリアメタル金属層（６
）と電解メッキ用下地金属層（７）の２つの層を独立し
た工程で形成せねばならず、それに伴ない製造工程が複
雑化するという問題があった。また、この事が作業能率
低下の要因となっていた。A source electrode (3), a gate electrode (not shown), and a drain electrode (not shown) are provided at predetermined intervals on the surface of the source electrode (2), as shown in FIG. 1 ((9)).
), leaving a part and covering the rest with a resist layer (4). Then, as shown in FIG. The barrier metal layer (5), which obtains the structure shown in Figure 1 (~) through the process, prevents the thermal reaction between the electrode constituent materials mainly caused by the rise in temperature of the element or the rise in environmental temperature during operation. Barrier metal layer (6) is formed to achieve high reliability of the device.After forming the barrier metal layer (6),
1 barrier metal layer (6) as shown in Figure 1(,)
A part of the resist layer is exposed and the other part is covered with an underlying resist layer (6). Thereafter, as shown in FIG. 1(f), a base metal layer (7) for electrolytic plating is formed by vapor deposition, followed by a barrier metal layer [11] as shown in FIG. Leaving only the portions of the underlying resist layer (6) that correspond to the openings, cover the rest with the surface resist layer (8).After that, as shown in FIG.
As shown in h), a thick plating layer (9) is formed by electrolytic plating in the openings of the surface resist layer (3) using the base gold for electrolytic plating: iris layer (yl) as an electrode. (8) (Figure 1(i))), the base metal layer for electrolytic plating (7) and the underlying resist layer (6) were sequentially removed to obtain the structure shown in Figure jR1(,+)K. 〇However, in this conventional method, the source electrode (3)
A barrier metal layer (6) is provided between the thick plating layer (9) and the thick plating layer (9).
) and the base metal layer for electrolytic plating (7) must be formed in separate processes, which has caused a problem in that the manufacturing process becomes complicated. This also caused a decrease in work efficiency.
本発明は、このような従来の欠点ｉｒｃ対処してなされ
たもので、バリアメタル金属層と電解メッキ用下地金属
層の両者の効果を併せ持つ金属層を利用する事により、
製造工程の簡略化が図れ作業能率の改善がで色る半導体
装置の製造方法を提供することを目的としている。The present invention has been made to address such drawbacks of the conventional IRC, and by using a metal layer that has both the effects of a barrier metal metal layer and a base metal layer for electrolytic plating,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that simplifies the manufacturing process and improves work efficiency.
このような目的を達成するため、本発明はバリア効果を
有する金属材料で構成される金属層を電解メッキ用下地
金属層として用いる事を％徴とするもので、以下に実施
例を用い詳細に説明する。In order to achieve such an object, the present invention features the use of a metal layer made of a metal material having a barrier effect as a base metal layer for electrolytic plating, and will be described in detail using examples below. explain.
第２図（ａ） 〜（ｆ）はＧａＡｓ Ｍ２Ｓ ＦＥＴの
本発明による製造方法の一実施例の主要工程を示す断面
図である。尚、この実施例は、ソース電極上のみに厚メ
ツキ電極を形成する場合に限定した説明であり、ゲート
およびドレイン電極は省略している。FIGS. 2(a) to 2(f) are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a GaAs M2S FET according to the present invention. Note that this embodiment is an explanation limited to the case where a thick plating electrode is formed only on the source electrode, and the gate and drain electrodes are omitted.
先ず、第２図（ａ） Ｋ示すように、半絶縁性ＧａＡ−
基板伸）上に周知の気相エピタキシャル成長法等により
生成されたｎＷｊｌの牛導体層＋１２１の表面に、例え
ば、金−ゲルマニウム（合金層）、ニッケルおよび金の
３層からなるソース電＆（１：ｌｌおよびドレイン電極
（図示省略）、また、アルミニウム等によるゲート電極
（図示省略）が選択的に形成されている試料を用意する
。仁の後、亀２図（ｂ）に示すように、ソース電極Ｏ騰
の所望の部分を露出させ、他を被覆する下敷レジスト層
Ｉを形成する。下敷レジスト層（１４の開孔部パターン
形状は従来構造との比較のため、その寸法、形状は第１
図の従来法で示したバリアメタル金属層（５）と同一で
あるとする。このよう表面レジスト層Ｉの形成後、比２
図（ｃ） Ｋ示すように、周知の蒸着法により電解メッ
キ用下地金属層１１を形成する。この電解メッキ用下地
金属層−は本発明の目的音達成するための主要な構成要
素で、前述したようにバリア効果を有する金属材料を、
含む構造となる０尚、この場合に金属層−は単一金属層
でなくてもよく、轟然の事ながら連続蒸着法で形成され
る多層構造の金属層（例えばＴｉ−Ｍｏ−ムｕ 、 Ｔ
ｉ−Ｗ−ムｕ ｔ ７’Ｃｔｉ Ｔｉ−Ｐｔ−ムＵ等）
であってもよい。First, as shown in Fig. 2(a) K, semi-insulating GaA-
For example, a source electrode consisting of three layers of gold-germanium (alloy layer), nickel, and gold is deposited on the surface of an nWjl conductor layer +121 produced by a well-known vapor phase epitaxial growth method on a substrate (alloy layer). A sample is prepared in which a drain electrode (not shown) and a gate electrode (not shown) made of aluminum or the like are selectively formed. A desired portion of the opening is exposed and an underlay resist layer I is formed to cover the other parts.The underlay resist layer (the opening pattern shape of 14 is for comparison with the conventional structure, its dimensions and shape are the same as those of the first resist layer).
It is assumed that this layer is the same as the barrier metal layer (5) shown in the conventional method shown in the figure. After forming the surface resist layer I in this way, the ratio 2
As shown in Figure (c) K, a base metal layer 11 for electrolytic plating is formed by a well-known vapor deposition method. This base metal layer for electrolytic plating is a main component for achieving the objective of the present invention, and as mentioned above, it is a metal material with a barrier effect.
Incidentally, in this case, the metal layer does not have to be a single metal layer, but may be a metal layer with a multilayer structure formed by a continuous vapor deposition method (for example, Ti-Mo-mu, T
i-W-mu t 7'Cti Ti-Pt-mu U, etc.)
It may be.
また、その膜厚は、バリアメタル金属層及び電解メッキ
用下地金属層の両効果を同時に満足するような膜厚で且
つ、後述するリフトオフ工程に支障を与えないような膜
厚である事が必要で、これ社下敷レジスト層ｒＪ４の膜
厚を考慮して決定される。In addition, the film thickness must be such that it simultaneously satisfies the effects of both the barrier metal layer and the base metal layer for electrolytic plating, and the film thickness must be such that it does not interfere with the lift-off process described below. It is determined in consideration of the film thickness of the underlying resist layer rJ4.
この後、ｊｌＥ ”図（（Ｌ）に示すように下敷レジス
ト層（１４）の開孔部と同じ形状の開孔部を有する表面
レジスト層（Ｉ尋を形成する０絖いて、゛第２図（・）
に示すように１表面レジスト層輪會マ不りとして電解メ
ッキ法によシ選択的に厚メッキ層（ｌηを形成する０し
かる後、リフトオフ法によ、、、（Ｌ′下敷レジスト層
０４゜電解メッキ用下地金属層（１）の周縁部および表
面レジスト層端を同時に除去し、第２図（ｆ）に示すよ
うな構造を得る０
このように、上記実施例ではＩＰＥＴの厚メツキ電極層
を電解メッキ法で形成するに当って、電解メッキ用下地
金属層をバリアメタル金属層としての効果（バリア効果
）を伴せもつ導電材料で構成し、この厚メッキ層を形成
後、残存する不用な表面レジスト層、電解メッキ用下地
金属層の周縁部及び下敷レジスト層をリフトオフ法で除
去するようにしたので、従来方法よりも工程数が減少し
、作業能率が向上する。しかも、下敷レジスト層の開孔
部の大きさを従来の方法における大きさよりも大きくで
き、更に表面レジスト層の開孔部の大きさも上記下敷レ
ジスト層の開孔部の大きさと等しくしたので、厚メッキ
層のソース電極への付着面積を大急くできる。従って、
素子パッケージへの中間接着導体として用いたときに熱
伝導性が向上し、□
素子の熱抵抗の改、善に寄与する。After this, as shown in Figure (L), the surface resist layer (14) having openings having the same shape as the openings in the underlying resist layer (14) is formed. （・）
As shown in Figure 1, a thick plating layer (lη) is selectively formed by electrolytic plating without any contact with the surface resist layer. The peripheral edge of the base metal layer for electrolytic plating (1) and the edge of the surface resist layer are simultaneously removed to obtain a structure as shown in FIG. When forming by electrolytic plating, the base metal layer for electrolytic plating is made of a conductive material that also has an effect as a barrier metal layer (barrier effect), and after forming this thick plating layer, the remaining unnecessary metal layer is Since the surface resist layer, the peripheral edge of the base metal layer for electrolytic plating, and the underlying resist layer are removed by the lift-off method, the number of steps is reduced and work efficiency is improved compared to the conventional method. The size of the opening in the surface resist layer can be made larger than that in the conventional method, and the size of the opening in the surface resist layer is also made equal to the size of the opening in the underlying resist layer. The adhesion area can be greatly increased.Therefore,
When used as an intermediate adhesive conductor to an element package, it improves thermal conductivity and contributes to improving the thermal resistance of the element.
、□、。,□,.
以上、実施例で暖ＧａＡｓ ＭＢ２ ＦＩＴのソース電
極上に厚メッキＭを形成する場合について述べたが、こ
の発明は勿論ゲートおよびドレイン電極に対しても適用
できるものである。ｏ Ｉ Ｋ ＳＧ＆Ａ８ ＭＪ８８
７ＩＴＫ限らずトランジスタ、ダイオードなど一般の半
導体装置についても半導体基体上の所望の電極に対して
厚メッキ層を形成する場合にこの発明は広く適用できる
。In the above embodiments, the case where thick plating M is formed on the source electrode of a warm GaAs MB2 FIT has been described, but the present invention can of course be applied to gate and drain electrodes. o I K SG&A8 MJ88
The present invention is widely applicable not only to 7ITK but also to general semiconductor devices such as transistors and diodes when forming a thick plating layer on a desired electrode on a semiconductor substrate.
以上詳述したように、この発明では半導体基体の表面に
形成された電極上に厚メッキ層を形成するに当って、バ
リア金属としての機能を有する金属からなる電解メッキ
用下地金属層を用い、厚メツキ層形成後の不用な電解メ
ッキ用下地金属層の部分の除去にり７トオフ法を適用す
るようＫし九ので、従来方法に比して工程数が減少し、
作業能率が向上する。また、この発明では従来方法の場
合に比して、厚メッキ層の電極への付着面積の電極面積
に対する割合を大きくすることができ、従って熱伝導性
の向上による素子熱抵抗の低減が可能である。As detailed above, in the present invention, when forming a thick plating layer on an electrode formed on the surface of a semiconductor substrate, a base metal layer for electrolytic plating made of a metal having a function as a barrier metal is used, Since the 7-off method is applied to remove unnecessary portions of the base metal layer for electrolytic plating after the thick plating layer is formed, the number of steps is reduced compared to the conventional method.
Work efficiency improves. Furthermore, in this invention, compared to the conventional method, it is possible to increase the ratio of the area of the thick plating layer to the electrode to the electrode area, and therefore it is possible to reduce the element thermal resistance by improving thermal conductivity. be.
絡１図（ａ）〜（ｊ）は厚メツキ電極を有するＧａム−
Ｍ１１ｔ８ＦＩＣＴの従来の製造方法を説明するための
その主要工程段階における状態を示す断面図、第２図（
ａ）〜＜１＞はこの発明の一実施例を説−するためのそ
の主要工程段階における状態を示す断面図である０図に
おいて、（１１）は中絶縁性ＧａＡｓ基板、（ｌ！１は
ｎ形Ｇａｐｓ亭導体層、〔（■）と（Ｉ！１とが半導体
基体を構成する。）、６１社ソース電極、■は下敷レジ
スト層（第１のマスク層）、Ｈは電解メッキ用下地金属
層（第１の金属層）、鵠は表面レジスト層（第２のマス
ク層）、ｒＪηは厚メッキ層である０なお、図中同一符
号は同一または相ｉｓ分を示す０
代理人 、葛 野 信 −（外１名）
第１図
、′？
第１図
第２図
第２図Figure 1 (a) to (j) shows a Ga film with thick plated electrodes.
FIG. 2 is a cross-sectional view showing the state of the main process steps to explain the conventional manufacturing method of M11t8FICT.
a) to <1> are cross-sectional views showing the state at the main process steps for explaining one embodiment of the present invention. In Figure 0, (11) is a medium insulating GaAs substrate, (l!1 is n-type gap conductor layer, [(■) and (I!1 constitute the semiconductor substrate), 61 source electrode, ■ is the underlying resist layer (first mask layer), H is the base for electrolytic plating The metal layer (first metal layer), the mouse is the surface resist layer (second mask layer), and rJη is the thick plating layer. Nobuo Nobu - (1 other person) Figure 1, '? Figure 1 Figure 2 Figure 2
Claims (2)
の上面の少なくとも一部を露出させる第１の開孔部を有
する第１のマスク層を形成する工程、上記第１のマスク
層の上および上記第１の開孔部に露出した上記電極の上
面にわたってバリア金属としての機能をも有する第１の
金属“・層を形成する工程、上記第１の金属層の上にお
いて、上記第１のマスク層の上記第１の開孔部に対応す
る位置に、これと同形状、同面積の第２の開孔部を有す
る第２のマスク層を形成する工程、上記第２のマスク層
をマスクとして上記第２の開孔部に露出する上記第１の
金属層の無比部に選択的に電解メッキを厚く施して第２
の金属からなる厚メッキ層を形成する工程、及び上記第
１のマスク層と上記第１のマスク層の上の上記第１の金
属層の部分とを上記第２のマスク層とともにリフトオフ
技術によって除去する工程を備えたこと１−特徴とする
半導体装置の製造方法。(1) A step of forming a first mask layer having a first opening that exposes at least a part of the upper surface of the electrode on a semiconductor substrate having an electrode formed on the surface; forming a first metal layer that also functions as a barrier metal over the upper surface of the electrode exposed in the first opening; forming a second mask layer having a second opening having the same shape and the same area at a position corresponding to the first opening of the mask layer; As a mask, electrolytic plating is selectively applied thickly to the unmatched portion of the first metal layer exposed in the second opening.
forming a thick plating layer made of a metal; and removing the first mask layer and a portion of the first metal layer above the first mask layer together with the second mask layer by a lift-off technique. 1 - A method for manufacturing a semiconductor device characterized by the step of:
いることを特徴とする特許請求の範囲第１項記載の半導
体装置の製造方法。(2) A method of manufacturing a semiconductor device according to claim 1, characterized in that a photoresist material is used for the first and second mask layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57018504A JPS58134428A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57018504A JPS58134428A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58134428A true JPS58134428A (en) | 1983-08-10 |
Family
ID=11973447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57018504A Pending JPS58134428A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58134428A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61141155A (en) * | 1984-12-14 | 1986-06-28 | Hitachi Ltd | Solder-base electrode |
| DE19640242C2 (en) * | 1996-09-30 | 2002-01-10 | Infineon Technologies Ag | Cathode arrangement for GTO thyristor |
-
1982
- 1982-02-05 JP JP57018504A patent/JPS58134428A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61141155A (en) * | 1984-12-14 | 1986-06-28 | Hitachi Ltd | Solder-base electrode |
| DE19640242C2 (en) * | 1996-09-30 | 2002-01-10 | Infineon Technologies Ag | Cathode arrangement for GTO thyristor |
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