JPS6059742B2 - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JPS6059742B2 JPS6059742B2 JP52137055A JP13705577A JPS6059742B2 JP S6059742 B2 JPS6059742 B2 JP S6059742B2 JP 52137055 A JP52137055 A JP 52137055A JP 13705577 A JP13705577 A JP 13705577A JP S6059742 B2 JPS6059742 B2 JP S6059742B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- insulating film
- electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Weting (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置およびその製造方法に関する。[Detailed description of the invention] The present invention relates to a semiconductor device and a method for manufacturing the same.
半導体装置のパッケージングとして実装密度が、高いこ
と、及びボンディング以降の製造工程を自動化できると
いう利点からフィルムキャリア方式が開発されてきた。The film carrier method has been developed as a packaging method for semiconductor devices because of its high packaging density and the ability to automate the manufacturing process after bonding.
フィルムキャリア方式を採用するためにはペレット内の
外部引出し電極にＡｕなどの突起電極（バンプ）を形成
しなければならない。第１図は従来のペレット内にバン
プを形成する工程における断面図である。In order to employ the film carrier method, protruding electrodes (bumps) made of Au or the like must be formed on external lead electrodes within the pellet. FIG. 1 is a cross-sectional view of a conventional step of forming bumps in a pellet.
第１図ａに示すように、半導体基板上に形成されたフィ
ールド酸化膜１の上にバンプを形成すべき箇所にＮ電極
２を形成し、さらにＣＶＤ（Ｃｈｅ−ＭｊｃｅｌＶａｐ
ＯｒＤｅｐＯｓｉｔｉＯｎ）法によりＳｉＯ２膜３を成
長させた後、Ｎ電極２上にスルーホールを開孔する。As shown in FIG. 1a, an N electrode 2 is formed on a field oxide film 1 formed on a semiconductor substrate at a location where a bump is to be formed, and further CVD (Che-MjcelVap) is formed on a field oxide film 1 formed on a semiconductor substrate.
After growing the SiO2 film 3 by the OrDepOsitiOn method, a through hole is formed on the N electrode 2.
次に、第１図ｂに示すように、フォトレジスト膜４を形
成する。Next, as shown in FIG. 1b, a photoresist film 4 is formed.
次に、第１図ｃに示すように、Ｔｉ膜５とＰｔ膜６をス
パッタ法により形成した後、リフトオフ法によりバンプ
形成箇所以外のＴｉ膜５及びＰｔ膜６を除去する。Next, as shown in FIG. 1c, a Ti film 5 and a Pt film 6 are formed by sputtering, and then the Ti film 5 and Pt film 6 are removed from areas other than the bump formation locations by a lift-off method.
次に、第１図ｄに示すように、メッキ電極用Ｎ蒸着膜７
を全面に形成した後、バンプ形成箇所以外をフォトレジ
スト膜８で覆う。Next, as shown in FIG. 1d, the N vapor deposition film 7 for the plating electrode is
After forming on the entire surface, areas other than the bump formation areas are covered with a photoresist film 8.
次に、第１図ｅに示すように、フォトレジスト膜８をマ
スクにしてＰｔ膜６上のＮをエッチングした後、Ａｕメ
ッキによりＡｕバンプ９を形成する。Next, as shown in FIG. 1e, after etching N on the Pt film 6 using the photoresist film 8 as a mask, Au bumps 9 are formed by Au plating.
次に、第１図ｆに示すように、フォトレジスト膜８を除
去し、メッキ電極用Ａ１蒸着膜７をエッチングすること
によりバンプ９が得られる。Next, as shown in FIG. 1f, the bumps 9 are obtained by removing the photoresist film 8 and etching the A1 vapor deposited film 7 for the plating electrode.
上記従来の製造方法には次のような問題点がある。（１
）ＣＶＤ酸化膜は熱酸化膜に比べてピンホールが多いの
で、メッキ電極用Ａｌ７をエッチングするときにＳｌＯ
２膜３の下にある配線Ａｌを完全に保護するためにはＳ
ｌＯ２膜３を厚くする必要がある。The conventional manufacturing method described above has the following problems. (1
) CVD oxide film has more pinholes than thermal oxide film, so when etching Al7 for plating electrode,
2 In order to completely protect the wiring Al under the film 3, S
It is necessary to make the lO2 film 3 thicker.
その場合にＡｌ電極２とＳｌＯ２膜３の段差が大きくな
り、第１図ｆ（７）Ａ部におけるチタン膜５、白金膜６
の被覆が悪くなつてしまい、ＡｕとＡ１とが反応してパ
ーブル・ブレーグを発生−し、バンプの引張り強度が弱
くなる。（２）Ｔｉ及びＰｔスパッタ膜形成後はＴｉが
活性なため、高温で熱処理（約４００℃以上）を行うと
Ａｌ及びＰｔと反応してしまい密着性がわるくなり、ボ
ンディングした場合に引張り強度が弱くな，る。In that case, the difference in level between the Al electrode 2 and the SlO2 film 3 becomes large, and the titanium film 5 and the platinum film 6 in part A of FIG.
The coating becomes poor, Au and A1 react to generate purplish brags, and the tensile strength of the bump becomes weak. (2) Ti is active after Ti and Pt sputtering films are formed, so if heat treatment is performed at high temperatures (approximately 400°C or higher), it will react with Al and Pt, resulting in poor adhesion and lower tensile strength when bonded. become weak.
そのためＴｉ及びＰｔスパッタ膜形成後の熱処理は極力
低温かつ短時間にする必要がある。しかし、メッキ電極
用Ａｌ蒸着の除に蒸着法によつては半導体基板と絶縁膜
の界面に損傷を生じ、トランジスタの基本特性に影響を
及ぼす。最も量産性にすぐれた電子ビーム蒸着法による
損傷を回復させるためには４５０℃程度の熱処理を必要
とする。したがつて、従来法によれば前述の如く４００
℃以上の熱処理ができないため電子ビーム蒸着法は用い
ることはできず、他の損傷のない蒸着法（例えば、抵抗
加熱蒸着法）を用いなければならず、量産性の低下を余
儀なくされる欠点がある。本発明は上記欠点を除去し、
酸化膜の段部におけるチタン及び白金膜被覆を改良し、
また、アルミニウム蒸着時に生ずる半導体基板と絶縁膜
との界面の損傷を回復することのできる半導体装置の製
造方法を堤供するものてある。Therefore, the heat treatment after forming the Ti and Pt sputtered films needs to be performed at a low temperature and for a short time as much as possible. However, some vapor deposition methods other than Al vapor deposition for plating electrodes cause damage to the interface between the semiconductor substrate and the insulating film, which affects the basic characteristics of the transistor. Heat treatment at about 450° C. is required to recover from damage caused by electron beam evaporation, which is the most efficient method for mass production. Therefore, according to the conventional method, 400
Electron beam evaporation cannot be used because heat treatment above ℃ is not possible, and other non-damaging evaporation methods (for example, resistance heating evaporation) must be used, which has the disadvantage of reducing mass productivity. be. The present invention eliminates the above drawbacks and
Improved titanium and platinum film coating on the step part of the oxide film,
The present invention also provides a method for manufacturing a semiconductor device that can recover damage to the interface between a semiconductor substrate and an insulating film that occurs during aluminum evaporation.
本発明の特徴は、半導体基板の一主面に設けられた第１
の絶縁膜と、該第１の絶縁膜上に設けられたアルミニウ
ム電極と、該第１の絶縁膜上より該アルミニウム電極の
上面の周辺部上に存在して設けられた第２の絶縁膜と、
該アルミニウム電極ｌの上面の中央部に被着して、かつ
該第２の絶縁膜上に存在して設けられたアルミニウム膜
と、該アルミニウム膜上のチタニウム膜と、該チタニウ
ム膜上の白金膜と該白金膜上の金バンプ層とを有する半
導体装置にある。The feature of the present invention is that the first
an insulating film, an aluminum electrode provided on the first insulating film, and a second insulating film provided above the first insulating film and above the peripheral portion of the upper surface of the aluminum electrode. ,
an aluminum film deposited on the center of the upper surface of the aluminum electrode l and existing on the second insulating film; a titanium film on the aluminum film; and a platinum film on the titanium film. and a gold bump layer on the platinum film.
本発明の他の特徴は、半導体基板の一主面に設けられた
第１の絶縁膜上に電極部を設ける工程と、該第１の絶縁
膜の表面上より該電極部の周辺部上にかけて第２の絶縁
膜を設ける工程と、該第２の絶縁膜が上に設けられてい
ない該電極部の中央部上から該第２の絶縁膜の表面上に
かけて、該電極部と同一材質の金属膜を形成する工程と
、前記電極部の中央部よりも広い面積であり、かつ該中
央部を包含することき第１の開孔を有する第１のフォト
レジスト層を該金属膜上に形成する工程と、該第１の開
孔内にバリア金属膜を選択的に形成する工程と、該第１
のフォトレジスト層を除去した後、該バリア金属膜の周
辺部を除く中央部を露出させる第２の開孔を有する第２
のフォトレジスト層を該バリア金属膜の該周辺部上から
該金属膜上にかけて設ける工程と、該金属膜メッキの電
流路として、該第２の開孔内の該バリア金属膜上に突起
電極をメッキにより形成する工程と、該第２のフォトレ
ジスト層を除去した後、前記バリア金属膜下の前記金属
膜の部分を残余せしめ、残りの金属膜の部分をエッチン
グ除去する半導体装置の製造方法にある。Other features of the present invention include the step of providing an electrode portion on a first insulating film provided on one main surface of a semiconductor substrate, and extending from the surface of the first insulating film to the peripheral portion of the electrode portion. a step of providing a second insulating film, and a metal made of the same material as the electrode part from above the center part of the electrode part on which the second insulating film is not provided to the surface of the second insulating film; forming a film, and forming a first photoresist layer on the metal film, the first photoresist layer having a larger area than the central part of the electrode part and having a first opening that covers the central part. a step of selectively forming a barrier metal film within the first opening;
After removing the photoresist layer, a second opening having a second opening exposing the central portion of the barrier metal film excluding the peripheral portion is removed.
a step of providing a photoresist layer from above the peripheral portion of the barrier metal film onto the metal film; and providing a protruding electrode on the barrier metal film in the second opening as a current path for plating the metal film. A method for manufacturing a semiconductor device including a step of forming by plating, and after removing the second photoresist layer, leaving a portion of the metal film under the barrier metal film and removing the remaining metal film by etching. be.
本発明の別の特徴は、半導体基板の一主面に設けられた
第１の絶縁膜上に電極部を設ける工程と、該第１の絶縁
膜の表面上より該電極部の周辺一部上にかけて第２の絶
縁膜を設ける工程と、該第２の絶縁膜がその上に設けら
れていない該電極部の中央部上から第２の絶縁膜の表面
上にかけて、該電極部と同一材質の金属膜を形成する工
程と、前記電極部の中央部よりも広い面積であり、かつ
該中央部を包含することき開孔を有するマスク層を該金
属膜上に形成する工程と、該開孔内にバリア層を選択的
に形成する工程と、該バリア層上に、前記金属膜をメッ
キの電流路として、メッキにより突起電極を形成する工
程と、該バリア層下の該金属膜の部分を残余せしめ、他
の金属膜の部分をエッチング除去する工程を有する半導
体装置の製造方法にある。Another feature of the present invention is the step of providing an electrode portion on a first insulating film provided on one main surface of a semiconductor substrate, and the step of providing an electrode portion on a part of the periphery of the electrode portion from above the surface of the first insulating film. a step of providing a second insulating film over the area, and a step of forming a second insulating film made of the same material as the electrode part from above the center part of the electrode part on which the second insulating film is not provided to the surface of the second insulating film. a step of forming a metal film; a step of forming a mask layer on the metal film having an aperture having an area larger than the central portion of the electrode portion and encompassing the central portion; and the aperture. a step of selectively forming a barrier layer within the barrier layer; a step of forming a protruding electrode by plating on the barrier layer using the metal film as a current path for plating; The method of manufacturing a semiconductor device includes a step of removing remaining metal film portions by etching away other metal film portions.
本発明によればメッキ電極用Ａ１蒸着をＴｉ及びＰｔ膜
形成の前に行うのでＴｉ及びＰｔ膜の段部被覆を改良し
、また４００℃以上て熱処理できることから損傷を与え
る蒸着法も使用できるという利点を有する。According to the present invention, the A1 vapor deposition for the plating electrode is performed before the formation of the Ti and Pt films, which improves the step coverage of the Ti and Pt films, and also allows the use of damaging vapor deposition methods since heat treatment can be performed at temperatures above 400°C. has advantages.
さらに、従来法ではスルホール開孔後、写真蝕刻工程を
２回必要としたが、本発明によればそれを１回にするこ
とも可能である。また、メッキ電極用Ａ１蒸着をスルー
ホール開孔直後に行うことからそれ以後の工程のイオン
性の汚染を防ぎ安定した特性の半導体装置を得ることが
できる。又、バリア膜下に金属膜を設けたことにより、
上記欠点が除去でき、第２の絶縁膜を厚くしてもバリア
膜は段切れ等の懸念はなくなる。さらに、バリア金属膜
として白金膜をチタニウム膜とともに用いると、突起電
極（バンプ）との接着性、電気導電率がよくなる。すな
わち、チタニウムは活性化が大であるから、容易にその
上にバンプ形成前に、うすい酸化膜が生成される。これ
を抑制するには白金膜が一番好ましい。本発明を実施例
により説明する。Further, in the conventional method, two photo-etching steps were required after opening the through-holes, but according to the present invention, it is possible to perform the photo-etching process only once. Furthermore, since the A1 vapor deposition for the plating electrode is performed immediately after opening the through hole, ionic contamination in subsequent steps can be prevented and a semiconductor device with stable characteristics can be obtained. In addition, by providing a metal film under the barrier film,
The above drawbacks can be eliminated, and even if the second insulating film is made thicker, there is no fear that the barrier film will break. Furthermore, when a platinum film is used together with a titanium film as a barrier metal film, adhesion to protruding electrodes (bumps) and electrical conductivity are improved. That is, since titanium is highly activated, a thin oxide film is easily formed thereon before bump formation. To suppress this, a platinum film is most preferable. The present invention will be explained by examples.
第２図は本発明の１実施例の半導体装置のバンプの製造
工程における断面図である。FIG. 2 is a cross-sectional view of a bump manufacturing process of a semiconductor device according to an embodiment of the present invention.
まず、第２図ａのように、従来法と同様にして、フィー
ルド酸化膜１１の上にＡｌ電極１２とＣＶＤ法によるＳ
ｉＯ２膜１３を成長してスルホールを開孔する。First, as shown in FIG.
The iO2 film 13 is grown and through holes are opened.
次に、第２図ｂのように、メッキ電極用として全面にＮ
蒸着膜１７を形成する。Next, as shown in Figure 2b, the entire surface is covered with N for the plating electrode.
A vapor deposited film 17 is formed.
この時点でアルミ蒸着によるダメージを回復させるため
の熱処理を行う場合はＴｉ及びＰｔスパッタ膜がないた
め、損傷回復に要する充分な温度（４５０℃程度）で熱
処理できる。次に、第２図ｃのように、フォトレジスト
膜１４を形成した後、Ｔｉ＜５Ｐｔを連続スパッタして
Ｔｉ膜１５、Ｐｔ膜１６を形成する。If heat treatment is performed to recover damage caused by aluminum vapor deposition at this point, since there is no Ti and Pt sputtered film, heat treatment can be performed at a sufficient temperature (approximately 450° C.) required for damage recovery. Next, as shown in FIG. 2c, after forming a photoresist film 14, Ti<5Pt is continuously sputtered to form a Ti film 15 and a Pt film 16.
次に、第２図ｄのように、リフトオフ法によりバンプ形
成箇所以外のＴｉ膜１５、Ｐｔ膜１６を除去し、バンプ
形成箇所以外をフォトレジスト膜１８で覆う。Next, as shown in FIG. 2d, the Ti film 15 and Pt film 16 other than the bump formation area are removed by a lift-off method, and the area other than the bump formation area is covered with a photoresist film 18.
次に、第２図ｅのように、フォトレジスト膜１１をマス
クにＡｕメッキを行い、Ａｕバンプ１９を形成する。Next, as shown in FIG. 2e, Au plating is performed using the photoresist film 11 as a mask to form Au bumps 19.
次に、第２図ｆのように、フォトレジスト膜１８を除去
し、に蒸着膜１７をエッチングして、本発明による半導
体装置のバンプが得られる。上記実施例に示したように
、ＴｉとＰｔのスパッタ蒸着工程で、メッキ電極用Ａｌ
蒸着を全面に行うことによりＮ電極１２とＳｉＯ２膜１
３の段差が小さくなり、Ｔｉ及びＰｔスパッタ膜の段部
被覆が良くなる。Next, as shown in FIG. 2f, the photoresist film 18 is removed and the deposited film 17 is etched to obtain bumps of the semiconductor device according to the present invention. As shown in the above example, in the sputter deposition process of Ti and Pt, Al
By performing vapor deposition on the entire surface, the N electrode 12 and the SiO2 film 1 are formed.
3 becomes smaller, and the Ti and Pt sputtered films cover the step better.
また、Ａ１蒸着による損傷を４００゜Ｃ以上の熱処理に
より回復させることが可能なもので電子ビーム蒸着法等
の損傷が発生する蒸着法も使用可能になる。さらにＡＩ
蒸着膜１７をバンプの製造工程の最初に行うため、それ
以後の工程のイオン性汚染を防ぐことができる。ノ 第
３図は本発明の他の実施例の半導体装置のバンプの製造
工程における断面図てある。In addition, damage caused by A1 deposition can be recovered by heat treatment at 400° C. or higher, making it possible to use deposition methods that cause damage, such as electron beam deposition. Furthermore, AI
Since the vapor deposition film 17 is formed at the beginning of the bump manufacturing process, ionic contamination in subsequent steps can be prevented. FIG. 3 is a cross-sectional view of a bump manufacturing process of a semiconductor device according to another embodiment of the present invention.
第３図ａのように、フィールド酸化膜２１の上にＡ１電
極２２及びＣＶＤ法による酸化膜２３を設け、ズルーホ
ーノｚを開孔する。次に、第３図ｂのように、メッキ電
極用のＡｌ蒸着膜２７を形成した後、ＣＶＤ法によりＳ
ｌＯ２膜２３″を成長させ、バンプ形成箇所以外をフォ
トレジスト膜２４で覆う。次に、第３図ｃのように、Ｓ
ｉＯ２膜２３″をエツチングする。As shown in FIG. 3A, an A1 electrode 22 and an oxide film 23 formed by the CVD method are provided on the field oxide film 21, and a hole Z is formed therein. Next, as shown in FIG. 3b, after forming an Al vapor deposition film 27 for the plating electrode, S
A lO2 film 23'' is grown, and areas other than bump formation areas are covered with a photoresist film 24. Next, as shown in FIG.
The iO2 film 23'' is etched.
フォトレジスト膜２４を残したまま、１５０℃程度の温
度で処理をし、Ｔｉ．ｌ５Ｐｔを連続スパッタして、Ｔ
ｉ膜２５、Ｐｔ膜２６を形成する。次に、第３図ｄのよ
うに、リストオフ法によりバンプ形成箇所以外のＴｉ膜
２５及びＰｔ膜２６を除去する。While leaving the photoresist film 24, it is processed at a temperature of about 150°C, and the Ti. Continuous sputtering of l5Pt
An i film 25 and a Pt film 26 are formed. Next, as shown in FIG. 3d, the Ti film 25 and the Pt film 26 are removed from areas other than the bump formation areas using the list-off method.
次に、第３図ｅのようにＳｉα膜２３″をマスクとして
Ａｕメッキを行い、バンプ２９を形成する。Next, as shown in FIG. 3e, Au plating is performed using the Siα film 23'' as a mask to form bumps 29.
最後に、第３図ｆのようにＳｉＯ２膜２３″及びメッキ
電極用アルミ蒸着膜２７をエッチングして、本発明の半
導体装置のバンプが得られる。この第２の実施例に示し
た方法に従うと前記実施例の利点に加えて、さらにスル
ーホール開孔以後、写真蝕刻工程が１回ですみ、従来法
に比ベ工数を削減でき、原価低減をもたらすことができ
る。また、上記実施例ではＮ−Ｔｉ−Ｒ−Ａｕ系につい
て説明したが他の金属についても応用できる事は明らか
である。Finally, as shown in FIG. 3f, the SiO2 film 23'' and the aluminum vapor deposited film 27 for plating electrodes are etched to obtain the bumps of the semiconductor device of the present invention.If the method shown in this second embodiment is followed, In addition to the advantages of the above-mentioned embodiment, the photo-etching step is only required once after the through-hole is formed, which reduces the number of man-hours compared to the conventional method, resulting in a reduction in cost. Although the -Ti-R-Au system has been described, it is clear that the invention can also be applied to other metals.
以上説明したように、本発明によればバンプ形成製造工
程においてメッキ電極用に蒸着をＴｉ及びＰｔスパッタ
蒸着工程の前工程で行うことにより、Ｔｉ及びＰｔスパ
ッタ膜の段部被覆の改良、製造工程中のイオン性汚染の
防止、さらにＡｌ蒸着法を任意に選択できる。As explained above, according to the present invention, by performing vapor deposition for plating electrodes in the bump formation manufacturing process in the pre-process of the Ti and Pt sputtering vapor deposition process, it is possible to improve the step coverage of the Ti and Pt sputtered films and improve the manufacturing process. In addition to preventing ionic contamination inside the structure, the Al vapor deposition method can be selected arbitrarily.
第１図は従来のペレット内にバンプを形成する工程にお
ける断面図、第２図は、本発明の１実施例の半導体装置
のバンプの製造工程における断面図、第３図は本発明の
他の実施例の半導体装置のバンプの製造工程における断
面図である。
１，１１，２１・ ・・フィールド酸化膜、２，１２，
２２・・・・・・に電極、３，１３，２３，２３５・・
・ＣＶＤ法によるＳｌＯ２膜、４，１４，２４・・・・
・・フォトレジスト膜、５，１５，２５・・・・・Ｔｉ
膜、６，１６，２６・・・・・Ｐｔ膜、７，１７，２７
・ナ・・・・メッキ電極用Ａｌ蒸着膜、８，１８・・・
・・フォトレジスト膜、９，１９，２９・・・・・・Ａ
ｕバンプ。FIG. 1 is a cross-sectional view of a conventional step of forming bumps in a pellet, FIG. 2 is a cross-sectional view of a bump manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of another embodiment of the present invention. FIG. 3 is a cross-sectional view of the bump manufacturing process of the semiconductor device according to the example. 1, 11, 21...field oxide film, 2, 12,
22... electrodes, 3, 13, 23, 235...
・SlO2 film by CVD method, 4, 14, 24...
...Photoresist film, 5, 15, 25...Ti
Membrane, 6, 16, 26...Pt membrane, 7, 17, 27
・Na... Al vapor deposited film for plating electrode, 8, 18...
...Photoresist film, 9, 19, 29...A
u bump.
Claims (1)
該第１の絶縁膜上に設けられたアルミニウム電極と、該
第１の絶縁膜上より該アルミニウム電極の上面周辺部上
に延在して設けられた第２の絶縁膜と、該アルミニウム
電極の上面の中央部に被着してかつ該第２の絶縁膜上に
延在して設けられたアルミニウム膜と、該アルミニウム
膜上のチタニウム膜と、該チタニウム膜上の白金膜と、
該白金膜上の金バンプ層とを有することを特徴とする半
導体装置。 ２ 半導体基板の一主面に設けられた第１の絶縁膜上に
電極部を設ける工程と、該第１の絶縁膜の表面上より該
電極部の周辺部上にかけて第２の絶縁膜を設ける工程と
、該第２の絶縁膜が上に設けられていない該電極部の中
央部上から該第２の絶縁膜の表面上にかけて該電極部と
同一材質の金属膜を形成する工程と、前記電極部の中央
部よりも広い面積でありかつ該中央部を包含することき
第１の開孔を有する第１のフォトレジスト層を該金属膜
上に形成する工程と、該第１の開孔内にバリア金属膜を
選択的に形成する工程と、該第１のフォトレジスト層を
除去した後該バリア金属膜の周辺部を除く中央部を露出
させる第２の開孔を有する第２のフォトレジスト層を該
バリア金属膜の該周辺部上から該金属膜上にかけて設け
る工程と、該金属膜をメッキの電流路として該第２の開
孔内の該バリア金属膜上に突起電極をメッキにより形成
する工程と、該第２のフォトレジスト層を除去した後、
前記バリア金属膜下の前記金属膜の部分を残余せしめ残
りの金属膜の部分をエッチング除去する工程とを有する
ことを特徴とする半導体装置の製造方法。 ３ 半導体基板の一主面に設けられた第１の絶縁膜上に
電極部を設ける工程と、該第１の絶縁膜の表面上より該
電極部の周辺部上にかけて第２の絶縁膜を設ける工程と
、該第２の絶縁膜がその上に設けられていない該電極部
の中央部上から該第２の絶縁膜の表面上にかけて該電極
部と同一材質の金属膜を形成する工程と、前記電極部の
中央部よりも広い面積でありかつ該中央部を包含するこ
とき開孔を有するマスク層を該金属膜上に形成する工程
と、該開孔内にバリア層を選択的に形成する工程と、該
バリア層上に、前記金属膜をメッキの電流路として、メ
ッキにより突起電極を形成する工程と、該バリア層下の
該金属膜の部分を残余せしめ、他の金属膜の部分をエッ
チング除去する工程とを有することを特徴とする半導体
装置の製造方法。[Claims] 1. A first insulating film provided on one main surface of a semiconductor substrate;
an aluminum electrode provided on the first insulating film; a second insulating film provided extending from above the first insulating film onto a peripheral portion of the upper surface of the aluminum electrode; an aluminum film deposited on the center of the upper surface and extending over the second insulating film; a titanium film on the aluminum film; and a platinum film on the titanium film;
A semiconductor device comprising a gold bump layer on the platinum film. 2. Providing an electrode portion on a first insulating film provided on one main surface of the semiconductor substrate, and providing a second insulating film from the surface of the first insulating film to the peripheral portion of the electrode portion. a step of forming a metal film made of the same material as the electrode portion from above the center portion of the electrode portion on which the second insulating film is not provided to the surface of the second insulating film; forming on the metal film a first photoresist layer having a first opening having an area larger than the central part of the electrode part and encompassing the central part; selectively forming a barrier metal film within the barrier metal film; and after removing the first photoresist layer, a second photoresist layer having a second opening that exposes the central portion of the barrier metal film excluding the peripheral portion; a step of providing a resist layer from above the periphery of the barrier metal film to above the metal film; and a step of plating a protruding electrode on the barrier metal film in the second opening using the metal film as a current path for plating. After forming and removing the second photoresist layer,
A method for manufacturing a semiconductor device, comprising the steps of leaving a portion of the metal film under the barrier metal film and removing the remaining metal film portion by etching. 3. Providing an electrode portion on a first insulating film provided on one principal surface of the semiconductor substrate, and providing a second insulating film from the surface of the first insulating film to the peripheral portion of the electrode portion. a step of forming a metal film made of the same material as the electrode portion from above the center portion of the electrode portion on which the second insulating film is not provided to the surface of the second insulating film; Forming on the metal film a mask layer having an opening having an area larger than the central part of the electrode part and encompassing the central part, and selectively forming a barrier layer within the opening. a step of forming a protruding electrode on the barrier layer by plating, using the metal film as a current path for plating, and leaving a portion of the metal film under the barrier layer and forming a portion of another metal film. A method for manufacturing a semiconductor device, comprising the step of etching away.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52137055A JPS6059742B2 (en) | 1977-11-14 | 1977-11-14 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52137055A JPS6059742B2 (en) | 1977-11-14 | 1977-11-14 | Semiconductor device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5469382A JPS5469382A (en) | 1979-06-04 |
| JPS6059742B2 true JPS6059742B2 (en) | 1985-12-26 |
Family
ID=15189818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52137055A Expired JPS6059742B2 (en) | 1977-11-14 | 1977-11-14 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059742B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5932154A (en) * | 1982-08-18 | 1984-02-21 | Seiko Instr & Electronics Ltd | Forming method for solder bump |
| JPS6396943A (en) * | 1986-10-13 | 1988-04-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH0290622A (en) * | 1988-09-28 | 1990-03-30 | Seiko Instr Inc | Gold bump forming method |
-
1977
- 1977-11-14 JP JP52137055A patent/JPS6059742B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5469382A (en) | 1979-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6149819B2 (en) | ||
| JP2785338B2 (en) | Method for manufacturing semiconductor device | |
| JPS6059742B2 (en) | Semiconductor device and its manufacturing method | |
| JPH02253628A (en) | Manufacture of semiconductor device | |
| JPH0697663B2 (en) | Method for manufacturing semiconductor device | |
| JPH02224336A (en) | Manufacture of semiconductor device | |
| JPH03198342A (en) | Manufacture of semiconductor device | |
| JPS63122248A (en) | Manufacture of semiconductor device | |
| JPS6336548A (en) | Semiconductor device and manufacture thereof | |
| JPS60176231A (en) | Electrode forming process of compound semiconductor element | |
| JPS628943B2 (en) | ||
| JPS62281356A (en) | Manufacture of semiconductor device | |
| JPH01238044A (en) | Semiconductor device | |
| JPH02277242A (en) | Manufacture of semiconductor device | |
| JPS6240770A (en) | Manufacture of semiconductor device | |
| JPS6362104B2 (en) | ||
| JPH0334675B2 (en) | ||
| JPH04278543A (en) | Semiconductor device and manufacture thereof | |
| JPS61141157A (en) | Manufacture of semiconductor element | |
| JPS5950221B2 (en) | Manufacturing method of semiconductor device | |
| JPH0237724A (en) | Formation of bump type electrode of semiconductor device | |
| JPH04144228A (en) | Manufacture of semiconductor device | |
| JPH0287526A (en) | Manufacture of semiconductor device | |
| JPS6130418B2 (en) | ||
| JPH04264733A (en) | Formation of bump base film for integrated circuit device |