JPH01117066A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPH01117066A JPH01117066A JP27478087A JP27478087A JPH01117066A JP H01117066 A JPH01117066 A JP H01117066A JP 27478087 A JP27478087 A JP 27478087A JP 27478087 A JP27478087 A JP 27478087A JP H01117066 A JPH01117066 A JP H01117066A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate electrode
- ions
- ion implantation
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 206010067482 No adverse event Diseases 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ＭＯＳ型半導体装置の製造方法に関し、ゲート電極の闇
値電圧のシフトのないＭＯＳ型半導体装置の製造方法の
提供を目的とし、ゲート電極形成後に、シリコン基板と
前記ゲート電極の側面とのなす角度の中の斜め方向から
イオンの注入を行い、前記ゲート電極の周辺部の下部の
前記シリコン基板（１）に低濃度のイオン注入層を形成
する工程を含むよう構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a MOS type semiconductor device, the purpose is to provide a method for manufacturing a MOS type semiconductor device in which the dark voltage of the gate electrode does not shift. and forming a low concentration ion implantation layer in the silicon substrate (1) below the peripheral part of the gate electrode by implanting ions from an oblique direction within the angle formed by the gate electrode and the side surface of the gate electrode. Configure it like this.
本発明は、半導体装置の製造方法に係り、特にＭＯＳ型
半導体装置の製造方法に関するものである。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a MOS type semiconductor device.
ＭＯＳ型半導体装置の高集積化に伴う微細化に伴い、ゲ
ート電極部で制御するチャネル長が１μｍ以下の微細構
造の場合には、ソース、ドレイン間の電圧によるブレイ
クダウンを防ぐために、ドレインの近傍に低濃度の拡散
層を形成し、ソース。With the miniaturization of MOS semiconductor devices due to higher integration, in the case of a fine structure with a channel length controlled by the gate electrode of 1 μm or less, it is necessary to Form a low concentration diffusion layer on the source.
ドレイン耐圧の向上を図るライトリ−・ドープド・ドレ
イン構造（Ｌ、Ｄ、Ｄ、構造）が用いられている。A lightly doped drain structure (L, D, D structure) is used to improve drain breakdown voltage.
しかしながら、従来のプロセスではゲート電極の側壁に
ヘパシリコン酸化膜を残す構造が採用されているが、こ
の構造では低濃度拡散層の直上にはゲート電極が存在し
ないうえ、ソース近傍にも低濃度拡散層が形成されるた
め、低濃度拡散層が抵抗層として働き、トランジスタの
０Ｎｊｌ抗の増加や電界集中によって発生したホットエ
レクトロンはゲート電極で制御できず、シリコン基板と
ゲート酸化膜界面にトラップされるために起きる闇値電
圧の低い方へのシフト等の悪影響が生じている。However, in the conventional process, a structure is adopted in which a hepasilicon oxide film is left on the sidewalls of the gate electrode, but in this structure, there is no gate electrode directly above the low concentration diffusion layer, and there is also a low concentration diffusion layer near the source. is formed, the low-concentration diffusion layer acts as a resistance layer, and hot electrons generated due to an increase in the transistor's 0Njl resistance and electric field concentration cannot be controlled by the gate electrode and are trapped at the interface between the silicon substrate and the gate oxide film. Negative effects such as a shift to lower dark value voltages are occurring.
以上のような状況からゲート電極の闇値電圧が低い方ヘ
シフトするのを防止することが可能なＭＯ８型半導体装
置の製造方法が要望されている。Under the above circumstances, there is a need for a method of manufacturing an MO8 type semiconductor device that can prevent the dark voltage of the gate electrode from shifting to a lower value.
従来のＭＯＳ型半導体装置の製造方法を工程順に第３図
により説明する。A conventional method for manufacturing a MOS type semiconductor device will be explained step by step with reference to FIG.
先ず第３図（ａｌに示すように、シリコン基板２１の表
面に周知の選択酸化法により表面保護及び素子分離層と
してのフィールド酸化膜２４を形成し、このフィールド
酸化膜２４により素子形成領域を画定する。First, as shown in FIG. 3 (al), a field oxide film 24 is formed as a surface protection and element isolation layer on the surface of a silicon substrate 21 by a well-known selective oxidation method, and an element formation region is defined by this field oxide film 24. do.
次にフィールド酸化膜２４により画定した素子形成領域
のシリコン基板２１の表面に熱酸化膜よりなるゲート酸
化膜２５を形成し、その表面にＣＶＤ法によりポリシリ
コン膜を形成し、周知のリソグラフィー技術によりポリ
シリコン膜をエツチングしてゲート電極２６を形成する
。Next, a gate oxide film 25 made of a thermal oxide film is formed on the surface of the silicon substrate 21 in the element formation region defined by the field oxide film 24, a polysilicon film is formed on the surface by the CVD method, and a well-known lithography technique is used to form the gate oxide film 25, which is a thermal oxide film. A gate electrode 26 is formed by etching the polysilicon film.
次いで第３図（ｂｌに示すように、ゲート電極２６をマ
スクとしてゲート酸化膜２５を通して低濃度の不純物イ
オンを注入して低濃度のソース２７ａ及びドレイン２８
ａを形成する。Next, as shown in FIG. 3 (bl), low concentration impurity ions are implanted through the gate oxide film 25 using the gate electrode 26 as a mask to form a low concentration source 27a and drain 28.
form a.
次いで第３図（Ｃ）に示すように、ゲート電極２６゜ソ
ース２７ａ及びドレイン２８ａの表面にＣＶＤ法により
シリコン酸化膜よりなるカバー絶縁膜２９ａを形成する
。Next, as shown in FIG. 3C, a cover insulating film 29a made of a silicon oxide film is formed on the surfaces of the gate electrode 26, the source 27a, and the drain 28a by CVD.
最後に第３図＋ｄ）に示すように、カバー絶縁膜２９ａ
を異方性の全面エツチングすることにより、カバー絶縁
膜２９ａのゲート電極２６の側壁部についている部分を
残存させてゲート電極２６の周囲にヘパシリコン酸化膜
２９を形成し、高濃度のイオンの注入を行ってソース２
７及びドレイン２８の拡散領域を形成する。Finally, as shown in FIG. 3+d), cover insulating film 29a
By etching the entire surface anisotropically, a hepasilicon oxide film 29 is formed around the gate electrode 26 by leaving a portion of the cover insulating film 29a attached to the side wall of the gate electrode 26, and high-concentration ions are implanted. go source 2
7 and the drain 28 are formed.
このようにして素子形成領域に素子を形成した＝３−
後、ＣＶＤ法により全面にＰＳＧ膜３０を形成し、リソ
グラフィー技術によりソース電極３１及びドレイン電極
３２用のコンタクトホールを形成し、アルミニウムより
なるソース電極３１及びドレイン電極３２を形成してＭ
ＯＳ型半導体装置を製造する。After forming an element in the element formation region in this way = 3-, a PSG film 30 is formed on the entire surface by CVD method, contact holes for source electrode 31 and drain electrode 32 are formed by lithography technology, and then a PSG film 30 made of aluminum is formed. Forming a source electrode 31 and a drain electrode 32
Manufacture an OS type semiconductor device.
以上説明の従来のＭＯＳ型半導体装置で問題となるのは
、従来のプロセスによるゲート電極の側壁にヘパシリコ
ン酸化膜を残す構造では低濃度拡散層の直上にはゲート
電極が存在しないため、低濃度拡散層が抵抗層となり、
トランジスタのＯＮ抵抗の増加や電界集中によって発生
したホットエレクトロンはゲート電極で制御できず、シ
リコン基板とゲート酸化膜界面にトラップされるために
起きる闇値電圧の低い方へのシフト等の悪影響が生じて
いることである。The problem with the conventional MOS type semiconductor device described above is that in the structure in which a hepasilicon oxide film is left on the sidewalls of the gate electrode by the conventional process, the gate electrode does not exist directly above the low concentration diffusion layer. layer becomes a resistance layer,
Hot electrons generated due to an increase in transistor ON resistance and electric field concentration cannot be controlled by the gate electrode, and are trapped at the interface between the silicon substrate and the gate oxide film, causing negative effects such as a shift of the dark value voltage to a lower side. This is what is happening.
本発明は以上のような状況から、容易に実施し得る工程
により、ゲート電極の闇値電圧のシフトのないＭＯＳ型
半導体装置の製造方法の提供を目、づ−
的としたものである。In view of the above-mentioned circumstances, the present invention aims to provide a method of manufacturing a MOS type semiconductor device without shifting the dark voltage of the gate electrode by a process that can be easily implemented.
上記問題点は、ＭＯＳ型半導体装置において、ゲート電
極形成後に、シリコン基板と前記ゲート電極の側面との
なす角度の中の斜め方向からイオンの注入を行い、前記
ゲート電極の周辺部の下部のシリコン基板に低濃度のイ
オン注入層を形成するＭＯＳ型半導体装置の製造方法に
よって解決される。The problem described above is that in a MOS semiconductor device, after the gate electrode is formed, ions are implanted from an oblique direction within the angle between the silicon substrate and the side surface of the gate electrode. The problem is solved by a method of manufacturing a MOS type semiconductor device in which a low concentration ion implantation layer is formed in a substrate.
即ち、本発明においては、ゲート電極形成後にシリコン
基板とゲート電極の側面とのなす角度の中の斜め方向か
らイオンの注入を行い、ゲート電極の周辺部の下部のシ
リコン基板に低濃度のイオン注入層を形成するので、電
界集中により発生したホットエレクトロンは、ゲート電
極で制御できるため、ゲート酸化膜界面にトラップされ
なくなり、閾値電圧の低い方へのシフト等の悪影響が生
じなくなる。That is, in the present invention, after the gate electrode is formed, ions are implanted from an oblique direction within the angle between the silicon substrate and the side surface of the gate electrode, and ions are implanted at a low concentration into the silicon substrate below the periphery of the gate electrode. Since a layer is formed, hot electrons generated by electric field concentration can be controlled by the gate electrode, so they are no longer trapped at the gate oxide film interface, and no adverse effects such as a shift of the threshold voltage to a lower side occur.
以下第１図について本発明の一実施例、第２図について
他の実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1, and another embodiment with reference to FIG. 2.
第１図の実施例は、ドレイン側にのみ低濃度のイオン注
入層を形成する例であり、第２図の実施例は、ソース側
とドレイン側の両方に低濃度のイオン注入層を形成する
例である。The embodiment shown in Fig. 1 is an example in which a low concentration ion implantation layer is formed only on the drain side, and the embodiment shown in Fig. 2 is an example in which a low concentration ion implantation layer is formed on both the source side and the drain side. This is an example.
先ず第１図（ａｌに示すように、Ｐ型のシリコン基板１
の表面に厚さ５００人のシリコン酸化膜２を形成し、更
にその上に厚さ１ 、０００人のシリコン窒化膜３を形
成する。First, as shown in FIG. 1 (al), a P-type silicon substrate 1 is
A silicon oxide film 2 with a thickness of 500 wafers is formed on the surface, and a silicon nitride film 3 with a thickness of 1,000 wafers is further formed thereon.
次に第１図（ｂｌに示すように、シリコン基板１の素子
形成領域以外のシリコン窒化膜３を除去し、チャネルカ
ット用のイオン注入を下記条件にて行う。Next, as shown in FIG. 1 (bl), the silicon nitride film 3 of the silicon substrate 1 other than the element formation region is removed, and ion implantation for channel cut is performed under the following conditions.
イオン種−−−−−−−−−一−−−−−−−−−−−
−−−−−−−−一・−一一−−−−−・−硼素（Ｂ）
イオン注入の加速電圧−−−−−−−−−−−−−−−
−−−−−−３０Ｋ ｅ Ｖドーズ量−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−一一一
一−Ｉ Ｘ １０ ” ｃｆｆＩ−”次いで第１図（Ｃ
）に示すように、ウェット酸素中で９５０℃に加熱し、
厚さ６．０００人のフィールド酸化膜４を形成する。Ion species-------------
−−−−−−−−1・−11−−−−−・−Boron (B)
Accelerating voltage for ion implantation
-------30K e V dose------
−−−−−−−−−−−−−−−−−−−−1111−I
), heated to 950 °C in wet oxygen,
A field oxide film 4 having a thickness of 6,000 wafers is formed.
次にシリコン窒化膜３を除去した後、弗酸系エツチング
液により厚さ５００人のシリコン酸化膜２をエツチング
して除去する。Next, after removing the silicon nitride film 3, the silicon oxide film 2 having a thickness of 500 mm is etched using a hydrofluoric acid etching solution.
その後第１図＋ｄ）に示すように、フィールド酸化膜４
により画定した素子形成領域のシリコン基板１０表面に
厚さ２００人の熱酸化膜よりなるゲート酸化膜５を形成
し、その表面にＣＶＤ法により厚さ４．０００人のポリ
シリコン膜を堆積し、リソグラフィー技術によるパター
ニング法により反応ガスとしてＣαｚＦ’ｔを用いるポ
リシリコン膜の異方性エツチングでゲート電極６を形成
する。After that, as shown in FIG. 1+d), the field oxide film 4 is
A gate oxide film 5 made of a thermal oxide film with a thickness of 200 μm is formed on the surface of the silicon substrate 10 in the element formation region defined by , and a polysilicon film with a thickness of 4,000 μm is deposited on the surface by the CVD method. Gate electrode 6 is formed by anisotropic etching of a polysilicon film using CαzF't as a reactive gas using a patterning method using lithography technology.
更に第１図（ｅ）に示すように、ゲート電極６をマスク
としてゲート酸化膜５を通してシリコン基板１の表面に
下記の条件にてイオンの注入を行い、ソース７及びドレ
イン８を形成する。Further, as shown in FIG. 1(e), using the gate electrode 6 as a mask, ions are implanted into the surface of the silicon substrate 1 through the gate oxide film 5 under the following conditions to form a source 7 and a drain 8.
イオン種−一−−−−−−−−・・・・・・−・−・−
ｍ−−−−−−−−−−−−−−−−−一砒素（ΔＳ）
イオン注入の加速電圧−・−ｍ−−−−−−・・・・−
・−・・−・−７０ＫｅＶドーズ量−−−−−−−−−
−−−−−−−−−−−−−−−−一−−−−−−−−
−・−４Ｘ１０′５印−２この際ゲート電極６のポリシ
リコン膜にもイオン注入が行われ、ゲート電極６のシー
ト抵抗が低下する。Ion species-1------------------
m------------- Monoarsenic (ΔS)
Accelerating voltage for ion implantation −・−m−−−−−・・・・−
・−・・−・−70KeV dose−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−
-.-4X10'5 Mark -2 At this time, ions are also implanted into the polysilicon film of the gate electrode 6, and the sheet resistance of the gate electrode 6 is reduced.
ここで第１図（ｆｌに示すように、シリコン基板１の表
面に対して４５６の角度の斜めイオン注入をドレイン側
から行い低濃度のイオン注入層９を形成する。Here, as shown in FIG. 1 (fl), oblique ion implantation at an angle of 456 to the surface of the silicon substrate 1 is performed from the drain side to form a low concentration ion implantation layer 9.
このイオン注入の条件は下記の通りである。The conditions for this ion implantation are as follows.
イオン種−一一一一−−−−−−−−−−−−−−−−
−−−−−一一一−−−−−−−−−−−−−−砒素（
Ａｓ）イオン注入の加速電圧−−−−−−−−−−−−
−−−−−−−−−−１５０ＫｅＶドーズ量−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−２Ｘ Ｉ Ｑ ’ ” ｃ＋ｎ −２
この結果第１図ｔｇ＞に示すように、ゲート電極６の周
辺部の下部に低濃度のイオン注入層９を形成することが
できる。Ion species - 1111
−−−−−111−−−−−−−−−−−−−−Arsenic (
As) Ion implantation acceleration voltage----------------------
----------150KeV dose------
−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−2X I Q' ” c+n −2
As a result, as shown in FIG.
この場合のゲート電極６の下部へのイオン注入層９のく
い込み長はゲート酸化膜５の膜厚、イオン注入の加速電
圧、イオン注入角度、ゲート電極側壁の角度等によって
制御可能であり、ゲート酸化膜５の厚さが２００人の本
実施例では、深さ６００人、ゲート電極４側壁より内部
６００人の部分に低濃度イオンのイオン注入層９を形成
することができた。In this case, the penetration length of the ion implantation layer 9 into the lower part of the gate electrode 6 can be controlled by the thickness of the gate oxide film 5, the acceleration voltage of ion implantation, the ion implantation angle, the angle of the side walls of the gate electrode, etc. In this example, the thickness of the film 5 was 200 layers, and the ion implantation layer 9 of low concentration ions could be formed at a depth of 600 layers and in a portion of the 600 layers inside from the side wall of the gate electrode 4.
最後に第１図（ｈｌに示すように厚さ１μｍのＰＳＧ膜
１０を堆積し、窒素ガス中で９００℃のアニールを３０
分間行って不純物の活性化を行い、コンタクトホールを
形成してアルミニウムでソース電極１１及びドレイン電
極１２を形成してＭＯＳ型半導体装置を製造する。Finally, as shown in FIG.
A contact hole is formed and a source electrode 11 and a drain electrode 12 are formed using aluminum to manufacture a MOS type semiconductor device.
第２図に示す本発明の他の実施例においては、第１図（
ａ）から第１図（ａまでの工程を終えた後、シリコン基
板１の表面に対して４５°の角度の斜めイオン注入をソ
ース側から行い、低濃度のイオン注入層９を形成する。In another embodiment of the invention shown in FIG.
After completing the steps from a) to FIG. 1(a), oblique ion implantation at an angle of 45° to the surface of the silicon substrate 1 is performed from the source side to form a low concentration ion implantation layer 9.
このイオン注入条件は下記の通りである。The ion implantation conditions are as follows.
イオン種−−−−−−一−−−−−−−−−・−−−−
−−・・−一−−−−−−−−−−−・−砒素（Ａｓ）
イオン注入の加速電圧・−−−−−−−−−−−−−−
−−−−−−１５０ＫｅＶドーズ量−・−−−−−−−
−−−・−−−−−ｍ−・−・−−−−−−−−−−−
−−Ｌ Ｘ １０’秘「２この結果第２図（ａ）に示す
ように、ゲート電極６の周囲の下部のソース側に低濃度
のイオン注入層９を形成することができる。Ion species-----------
---・・-1---------------Arsenic (As)
Accelerating voltage for ion implantation
-------150KeV dose------
−−−・−−−−−m−・−・−−−−−−−−−−−
--L
本実施例においては、ソース側の低濃度のイオン注入層
のドーズ量（濃度）をドレイン側の低濃度のイオン注入
層のドーズ量（？１度）より低く設定している。In this embodiment, the dose (concentration) of the low concentration ion implantation layer on the source side is set lower than the dose (?1 degree) of the low concentration ion implantation layer on the drain side.
最後に第２図（ｂ）に示すように、厚さ１μｍのＰＳＧ
膜１０を堆積し、窒素ガス中で９００℃のアニールを３
０分間行って不純物の活性化を行い、コンタクトホール
を形成してアルミニウムでソース電極１１及びドレイン
電極１２を形成してＭＯＳ型半導体装置を製造する。Finally, as shown in Figure 2(b), a 1 μm thick PSG
A film 10 is deposited and annealed at 900°C in nitrogen gas for 3
The process is carried out for 0 minutes to activate impurities, form a contact hole, and form a source electrode 11 and a drain electrode 12 of aluminum to manufacture a MOS type semiconductor device.
本実施例では、両側に形成した低濃度のイオン注入層の
濃度をドレイン側とソース側で変えているが、本発明が
この場合に限定されることはない。In this embodiment, the concentration of the low concentration ion implantation layers formed on both sides is different between the drain side and the source side, but the present invention is not limited to this case.
また、低濃度のイオン注入層を形成してからソース、ド
レインの高濃度イオン注入をおこなってもよいことは明
らかである。It is also obvious that high concentration ion implantation for the source and drain may be performed after forming a low concentration ion implantation layer.
以上の説明から明らかなように、本発明によれば容易に
実施し得るイオン注入により、ゲート電極の周辺部の下
部に低濃度イオンのイオン注入層を形成することが可能
となり、この低濃度イオンのイオン注入層の周囲のくう
ぼう層が厚くなり、電界の集中が起こり難くなるので、
ブレイクダウンを防止することが可能で、しかもホット
エレクトロンのトラップによる閾値電圧の変動が発生し
にくい等の利点があり、経済的及び信頼性向上の効果が
期待でき工業的には極めて有用なものである。As is clear from the above description, according to the present invention, it is possible to form an ion implantation layer of low concentration ions in the lower part of the peripheral part of the gate electrode by ion implantation that can be easily carried out. The ion-implanted layer surrounding the ion-implanted layer becomes thicker, making it difficult for electric field concentration to occur.
It has the advantage of being able to prevent breakdown, and is less likely to cause fluctuations in threshold voltage due to hot electron trapping, and is expected to be economically and reliability-improving, making it extremely useful industrially. be.
第１図は本発明による一実施例を工程順に示す側断面図
、
第２図は本発明による他の実施例を工程順に示す側断面
図、
第３図は従来のＭＯＳ型半導体装置の製造方法を工程順
に示す側断面図、
である。
図において、
１はシリコン基板、
２はシリコン酸化膜、
３はシリコン窒化膜、
４はフィールド酸化膜、
５はゲート酸化膜、
６はゲート電極、
７はソース、
８はドレイン、
９は低濃度のイオン注入層、
１０はＰＳＧ膜、
１１はソース電極、
１２はドレイン電極、
ド 跡
−Ｌ−Ｌ−ＳＣ−ｉ
単FIG. 1 is a side cross-sectional view showing an embodiment according to the present invention in the order of steps; FIG. 2 is a side cross-sectional view showing another embodiment according to the present invention in order of steps; FIG. 3 is a conventional method for manufacturing a MOS type semiconductor device. These are side sectional views showing the steps in the order of steps. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is a silicon nitride film, 4 is a field oxide film, 5 is a gate oxide film, 6 is a gate electrode, 7 is a source, 8 is a drain, and 9 is a low concentration film. ion implantation layer; 10 is a PSG film; 11 is a source electrode; 12 is a drain electrode;
Claims (1)
記ゲート電極（６）の側面とのなす角度の中の斜め方向
からイオンの注入を行い、前記ゲート電極（６）の周辺
部の下部の前記シリコン基板（１）に低濃度のイオン注
入層（９）を形成する工程を含むことを特徴とするＭＯ
Ｓ型半導体装置の製造方法。After forming the gate electrode (6), ions are implanted from an oblique direction within the angle formed between the silicon substrate (1) and the side surface of the gate electrode (6), and the lower part of the periphery of the gate electrode (6) is implanted. An MO characterized by comprising a step of forming a low concentration ion implantation layer (9) on the silicon substrate (1).
A method for manufacturing an S-type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27478087A JPH01117066A (en) | 1987-10-29 | 1987-10-29 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27478087A JPH01117066A (en) | 1987-10-29 | 1987-10-29 | Manufacture of mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01117066A true JPH01117066A (en) | 1989-05-09 |
Family
ID=17546459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27478087A Pending JPH01117066A (en) | 1987-10-29 | 1987-10-29 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01117066A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02250331A (en) * | 1989-03-24 | 1990-10-08 | Hitachi Ltd | Semiconductor device and its manufacture |
| US5158903A (en) * | 1989-11-01 | 1992-10-27 | Matsushita Electric Industrial Co., Ltd. | Method for producing a field-effect type semiconductor device |
| JP2006332110A (en) * | 2005-05-23 | 2006-12-07 | Asahi Kasei Microsystems Kk | Semiconductor device and its fabrication process |
-
1987
- 1987-10-29 JP JP27478087A patent/JPH01117066A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02250331A (en) * | 1989-03-24 | 1990-10-08 | Hitachi Ltd | Semiconductor device and its manufacture |
| US5158903A (en) * | 1989-11-01 | 1992-10-27 | Matsushita Electric Industrial Co., Ltd. | Method for producing a field-effect type semiconductor device |
| JP2006332110A (en) * | 2005-05-23 | 2006-12-07 | Asahi Kasei Microsystems Kk | Semiconductor device and its fabrication process |
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