KR0157910B1 - Method of forming mosfet having ldd structure - Google Patents
Method of forming mosfet having ldd structure Download PDFInfo
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- KR0157910B1 KR0157910B1 KR1019950043560A KR19950043560A KR0157910B1 KR 0157910 B1 KR0157910 B1 KR 0157910B1 KR 1019950043560 A KR1019950043560 A KR 1019950043560A KR 19950043560 A KR19950043560 A KR 19950043560A KR 0157910 B1 KR0157910 B1 KR 0157910B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 230000005669 field effect Effects 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 16
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 description 21
- 230000015556 catabolic process Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000007539 photo-oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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Abstract
본 발명은 LDD구조를 갖는 MOS형 전계효과트랜지스터(이하 MOS FET라 한다)의 제조방법에 관한 것으로, 특히 셀프얼라인방식으로 소자영역을 정의하고 측벽 구조와 이온주입 및 열처리공정을 이용하여 LDD구조를 형성하는 MOS FET의 제조방법에 관한 것이다. 이와 같은 본 발명은 먼저 액티브영역에 제1산화막과 질화막층을 적층한 다음에 사진식각공정을 실시하여 게이트영역의 질화막과 산화막을 제거하고, 이어서 제2산화막을 형성하고 다결정실리콘을 적층한 후에 식각하여 게이트도전층을 형성한다. 그리고 상기 게이트도전층의 좌·우측에 있는 질화막층과 제1산화막을 에칭하여 측벽을 형성한 후에 이온을 주입하여 고농도 소오스/드레인 영역을 형성하고 이어서 열확산하여 저농도 소오스/드레인 영역을 형성함으로써 LDD구조를 형성한다. 상기와 같은 제조방법은 공정수를 줄이고 공정제어가 용이한 방법을 제공함과 아울러 고미세패턴의 게이트를 형성할 수 있고, 균일한 소오스/드레인 PN접합을 형성하며, 접합깊이도 얇게 형성할 수 있는 효과가 있다.The present invention relates to a method for manufacturing a MOS field effect transistor (hereinafter referred to as a MOS FET) having an LDD structure. In particular, the device region is defined in a self-aligned manner, and the LDD structure is formed using sidewall structures, ion implantation, and heat treatment processes. The present invention relates to a method of manufacturing a MOS FET. In the present invention, first, the first oxide film and the nitride film layer are laminated in the active region, and then a photolithography process is performed to remove the nitride film and the oxide film in the gate region, followed by forming a second oxide film and laminating polycrystalline silicon. To form a gate conductive layer. The nitride layer on the left and right sides of the gate conductive layer and the first oxide film are etched to form sidewalls, and then ion is implanted to form a high concentration source / drain region, followed by thermal diffusion to form a low concentration source / drain region. To form. The manufacturing method as described above provides a method of reducing the number of processes and easily controlling the process, and can form a gate having a high fine pattern, form a uniform source / drain PN junction, and form a thin junction depth. It works.
Description
제1도의 (a) 내지 (g)는 종래의 엘디디(LDD) 구조를 갖는 모스페트(MOS FET)의 제조방법을 도시한 공정순서단면도.(A)-(g) is a process sequence sectional drawing which shows the manufacturing method of the MOS FET which has the conventional LDD structure.
제2도의 (a) 내지 (g)는 본 발명에 따른 엘디디 구조를 갖는 모스페트(MOS FET)의 제조방법을 도시한 공정순서단면도.(A)-(g) of FIG. 2 is a process sequence sectional drawing which shows the manufacturing method of the MOS FET which has the LED structure which concerns on this invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101 : 실리콘기판 102 : 필트산화막101: silicon substrate 102: filter oxide film
103 : 채널스토퍼영역 104 : 제2산화막103: channel stopper region 104: second oxide film
105 : 다결정실리콘층 105a : 게이트도전층105: polycrystalline silicon layer 105a: gate conductive layer
108 : 포토레지스트 109, 110 : 저농도 불순물층108: photoresist 109, 110: low concentration impurity layer
111 : 질화막 111a : 측벽스페이서111 nitride film 111a sidewall spacer
113, 114 : 고농도불순물층 117 : 제1산화막113, 114: high impurity layer 117: first oxide film
118 : 손실층118: loss layer
본 발명은 엘디디(Lightly Doped Drain; 이하 'LDD'라 한다)구조를 갖는 절연게이트형 전계효과트랜지스터(Metal Oxide Semiconductor-Field Effect Transistor; 이하 'MOS FET'라 한다)의 제조방법에 관한 것으로, 특히 게이트도전층이 실리콘기판 내부까지 형성되어 소오스/드레인 영역과 단차가 생기도록 하고, 측벽 스페이서(Side-Wall Spacer)를 마스크로 하여 이온을 주입한 다음에 이를 확산시켜 소오스/드레인 영역을 형성함으로써, 게이트 및 소오스/드레인 영역이 고미세패턴으로 형성되고, 채널 및 PN접합부의 파괴전압이 저하되는 것을 방지한 LDD구조를 갖는 MOS FET의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing an insulated gate field effect transistor (LDMOS) having a lightly doped drain (LDD) structure. In particular, the gate conductive layer is formed up to the inside of the silicon substrate so as to generate a step with the source / drain region, and ion is implanted using a side-wall spacer as a mask and then diffused to form a source / drain region. The present invention relates to a method for manufacturing a MOS FET having an LDD structure in which gate and source / drain regions are formed in a high fine pattern, and a breakdown voltage of a channel and a PN junction is prevented from decreasing.
일반적으로, 소오스/드레인 영역의 불순물농도가 균일한 고미세화 MOS FET는 게이트 전극측으로부터의 전계에 따라 드레인 표면부에 전계집중이 일어나는데, 이는 표면부에서의 PN 접합간의 공핍층 퍼짐이 억제되기 때문에 결과적으로, 채널 및 PN접합부의 접합내압을 저하시켜 벌크내의 접합내압보다 낮은 전압에서 브레이크 다운이 발생하는 문제점이 있었다.In general, high-density MOS FETs having a uniform impurity concentration in the source / drain regions have electric field concentration at the drain surface part according to an electric field from the gate electrode side, since depletion of the depletion layer between PN junctions at the surface part is suppressed. As a result, there is a problem in that the breakdown voltage of the channel and the PN junction is lowered and breakdown occurs at a voltage lower than the breakdown voltage in the bulk.
상기와 같은 문제점을 해결하기 위하여 일반적으로 통상의 소오스/드레인 영역보다 상대적으로 불순물농도가 낮은 영역(LDD 영역)을 채널영역 쪽으로 배치함으로써 표면부분의 내압저하를 방지하고 있다. 즉, 상기 LDD 영역의 접합내압이 통상의 소오스/드레인부 보다 높게되어 게이트 전계가 이 LDD 영역에 집중됨으로써 고내압 구조를 얻게 되는 것이다.In order to solve the above problems, a pressure drop of the surface portion is prevented by disposing a region having a lower impurity concentration (LDD region) toward a channel region than a general source / drain region. That is, the junction breakdown voltage of the LDD region is higher than that of a normal source / drain portion, and the gate electric field is concentrated in the LDD region, thereby obtaining a high breakdown voltage structure.
상기와 같은 LDD 구조를 갖는 MOS FET에 대한 종래의 제조방법에 대해서 첨부한 도면을 참조하여 설명한다.A conventional manufacturing method for a MOS FET having the above LDD structure will be described with reference to the accompanying drawings.
제1도의 (a) 내지 (g)는 LDD 구조를 갖는 MOS FET에 대한 종래의 제조방법을 공정순서단면도로 도시한 것으로, 이를 참조하여 상세히 설명하면 다음과 같다.(A) to (g) of FIG. 1 illustrate a conventional manufacturing method for a MOS FET having an LDD structure in a process sequence cross-sectional view.
먼저, 제1도의 (a)에 도시된 바와 같이 액티브영역과 필드영역(2)이 정의된 실리콘기판(1) 속에 불순물 이온을 주입하여 채널스토퍼(Channel Stopper)영역(3)을 형성한다. 상기 채널스토퍼 영역(3)은 반도체 소자 사이를 전기적으로 분리하기 위한 불순물층으로, n형 MOS FET는 p형의 채널스토퍼를 p형 MOS FET는 n형의 채널스토퍼를 주입한다.First, as shown in FIG. 1A, impurity ions are implanted into the silicon substrate 1 in which the active region and the field region 2 are defined to form a channel stopper region 3. The channel stopper region 3 is an impurity layer for electrically separating semiconductor devices, and an n-type MOS FET injects a p-type channel stopper and a p-type MOS FET injects an n-type channel stopper.
이후, 제1도의 (b)에 도시된 바와 같이 채널스토퍼 영역(3)이 형성된 실리콘기판(1) 상에 게이트절연용 제1산화막(4) 다결정실리콘층(5), 게이트 상부 절연용 제2산화막(Cap-HLD;6), 반사율저감용막(HSG;7)을 순차적으로 적층한 후, 레지스트 공정을 실시하여 상기 반사율저감용막(7) 상에 레지스패턴(8)을 형성한다.Subsequently, as shown in FIG. 1B, the first oxide film 4 for gate insulation, the polysilicon layer 5, and the second gate upper insulation are formed on the silicon substrate 1 having the channel stopper region 3 formed thereon. An oxide film (Cap-HLD) 6 and a reflectance reduction film (HSG) 7 are sequentially stacked, and then a resist process is performed to form a resist pattern 8 on the reflectance reduction film 7.
상기 레지스패턴(8)은 게이트가 형성될 영역에만 포토레지스트(8)가 남도록 하는 게이트 형성을 위한 패턴이다.The resist pattern 8 is a pattern for forming a gate such that the photoresist 8 remains only in a region where the gate is to be formed.
그리고, 제1도의 (c)에 도시된 바와 같이 상기 포토레지스트(8)를 마스크로 하여 에칭함으로써, 게이트가 형성될 영역을 제외한 부분의 반사율저잠용막(7)과 제2산화막(6)을 제거하고, 이어서 포토레지스트 마스크(8)을 제거한다.As shown in (c) of FIG. 1, the photoresist 8 is etched as a mask, thereby removing the reflectance low barrier film 7 and the second oxide film 6 except for the region where the gate is to be formed. Then, the photoresist mask 8 is removed.
이어서, 제1도의 (d)에 도시된 바와 같이 반사율저감용막(7)을 제거한 후에, 제2산화막(6a)을 마스크로 이용하여 건식에칭을 실시함으로써 다결정실리콘층(5)으로 이루어진 게이트전도층(5a)이 형성됨과 아울러 소오스/드레인 영역위의 제1산화막(4)이 노출된다.Subsequently, after removing the reflectance reduction film 7 as shown in FIG. 1D, the gate conduction layer made of the polycrystalline silicon layer 5 is subjected to dry etching using the second oxide film 6a as a mask. 5a is formed and the first oxide film 4 on the source / drain regions is exposed.
이어서, LDD구조를 만들기 위한 공정을 실행하게 되는데, 제1도의 (d)에 도시된 바와 같이 상기 게이트전도층(5a) 위에 있는 제2산화막(6a)을 마스크로 하여 저농도 불순물 이온을 주입함으로써, 제1산화막(4) 아래의 실리콘기판(1) 내부에 저농도 소오스/드레인영역(9,10)을 형성한다.Subsequently, a process for making an LDD structure is performed. By implanting low concentration impurity ions using a second oxide film 6a on the gate conductive layer 5a as a mask, as shown in FIG. Low concentration source / drain regions 9 and 10 are formed in the silicon substrate 1 under the first oxide film 4.
다음으로, 제1도의 (e)에 도시된 바와 같이 상기 저농도 소오스/드레인 영역이 형성된 소자의 표면 상에 게이트영역(5a,6a)을 중심으로 측벽 스페이서(Side-Wall Spacer) 형성용 제3산화막(11)을 도포한다.Next, as shown in (e) of FIG. 1, a third oxide film for forming sidewall spacers around the gate regions 5a and 6a on the surface of the device on which the low concentration source / drain regions are formed. (11) is applied.
이후, 제1도의 (f)에 도시된 바와 같이 상기 제3산화막(11)에 대해 에치백(Etch-back)을 실시하여 측벽스페이서(11a)을 형성하고, 상기 제2산화막(6a)과 제3산화막(11)으로 이루어진 측벽스페이서(11a)를 마스크로 이용하여 고농도 불순물 이온을 주입함으로써, 고농도 소오스/드레인영역(13,14)을 형성한다.Subsequently, as shown in FIG. 1F, an etch-back is performed on the third oxide film 11 to form sidewall spacers 11a, and the second oxide film 6a and the second oxide film 6a are formed. High concentration source / drain regions 13 and 14 are formed by implanting high concentration impurity ions using the sidewall spacers 11a formed of the trioxide film 11 as a mask.
제1도의 (g)는 상기와 같은 공정을 실시하여 최종적으로 완성된 MOS FET의 단면을 도시한 단면도로서, 이에 도시된 바와 같이 접합내압이 통상의 고농도 소오스/드레인영역(13,14) 보다 높은 LDD 영역(9,10)이 채널영역쪽으로 형성됨으로써, 게이트 전계가 이 LDD 영역(9,10)에 집중되어 채널 및 PN접합부의 접합내압이 형성된 고내압 구조의 MOS FET를 얻게 되는 것이다.FIG. 1 (g) is a cross-sectional view showing a cross section of the MOS FET finally completed by performing the above process, and as shown therein, the junction breakdown voltage is higher than that of the usual high concentration source / drain regions 13 and 14. By forming the LDD regions 9 and 10 toward the channel region, the gate electric field is concentrated in the LDD regions 9 and 10 to obtain a MOS FET having a high breakdown voltage structure in which the junction breakdown voltage of the channel and the PN junction is formed.
그러나, 이와 같은 종래의 제조방법 게이트영역(5a,6a) 형성 및 LDD 구조를 형성하기 위하여 다수의 포토리소그래피공정과 측벽스페이서 형성공정, 에칭공정 등의 복잡하고 번거로운 공정을 여러 번 실시해야 하는 단점과, LDD 구조를 형성하는 공정에 있어서 저농도 불순물 이온을 측벽스페이서(11a)가 없는 상태에서 주입함으로써 저농도영역(9,10)과 게이트영역(5a,6a)의 오버 랩(Over Lap)이 발생하는데, 이 오버 랩이 과도하게 되면 채널길이가 줄게 되고 따라서 쇼트채널효과(Shoer Channal Effect)가 발생하여 반도체 소자의 특성이 열화되는 문제점이 있었다.However, in order to form the gate area 5a and 6a and the LDD structure of the conventional manufacturing method, a number of complicated and cumbersome processes such as photolithography, sidewall spacer forming, and etching are required. In the process of forming the LDD structure, the low concentration impurity ions are implanted in the absence of the sidewall spacers 11a to generate an overlap between the low concentration regions 9 and 10 and the gate regions 5a and 6a. If the overlap is excessive, the channel length is reduced, and thus, a short channel effect occurs, resulting in deterioration of characteristics of the semiconductor device.
그리고, 고농도 이온주입을 측벽스페이서(11a)가 형성된 후에 실시함으로써, 산화막(11)으로 구성된 측벽스페이서(11a)를 통하여 게이트(5a)와 드레인(10) 간에 미세한 누설전류가 흐르는 문제점이 있었다.Further, since high concentration ion implantation is performed after the sidewall spacers 11a are formed, there is a problem that a minute leakage current flows between the gate 5a and the drain 10 through the sidewall spacers 11a formed of the oxide film 11.
또한, 액티브영역의 실리콘기판(1)에 채널스토퍼영역(3)을 형성하는 공정에서 소오스/드레인 영역에 까지 이온을 주입함으로써, 펀치쓰루우(pinch-through) 방지효과에 대한 신뢰성이 저감되고 쇼트채널효과가 발생하는 문제점이 있었다.In addition, by implanting ions into the source / drain regions in the process of forming the channel stopper region 3 in the silicon substrate 1 in the active region, the reliability of the punch-through prevention effect is reduced and the shot is shortened. There was a problem that the channel effect occurs.
이에 본 발명은 상기와 같은 종래의 문제점을 개선하기 위하여 창안한 것으로, 제조공정이 단순하면서도 게이트패턴을 고도로 미세하게 형성할 수 있고 채널(Channel) 및 PN접합부의 파괴전압(Breakdown Voltage)에 대한 소자의 특성을 개선할 수 있는 MOS FET의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention was devised to improve the above-mentioned problems, and the manufacturing process is simple, but the gate pattern can be formed very finely, and the device for the breakdown voltage of the channel and the PN junction part is reduced. It is an object of the present invention to provide a method for manufacturing a MOS FET that can improve the characteristics of the.
상기와 같은 목적을 달성하기 위하여 본 발명에 따른 MOS FET의 제조방법은 액티브영역과 필드영역이 정의되고 제1산화막이 형성된 실리콘기판 상에 질화막(Nitride Film)을 형성한 후, 포토레지스트(Photo Resist)로 게이트패턴을 형성하는 공정과; 상기 게이트패턴을 마스크로 하여 에칭함으로써 게이트가 형성될 영역의 질화막과 제1산화막 및 실리콘기판 표면을 소정의 깊이로 제거한 후, 포토레지스트를 제거하는 공정과; 상기 에칭공정을 통하여 노출된 실리콘기판의 내부에 채널스토퍼영역 형성용 불순물이온을 주입하는 공정과; 상기 이온주입공정에서 발생한 손실층을 제거한 후, 게이트절연용 제2산화막을 형성하고 이어서 게이트도전층 형성용 다결정실리콘을 게이트영역의 개구부를 포함한 소자의 전면에 적층하는 공정과; 상기 다결정실리콘을 식각하여 게이트도전층을 형성하는 공정과; 상기 게이트도전층을 마스크로 하여 에칭함으로써, 게이트도전층의 측면에 질화물과 제1산화물로 이루어진 측벽스페이서를 형성하는 공정과; 상기 다결정실리콘으로 이루어진 게이트도전층과 질화물 및 제1산화물로 이루어진 측벽스페이서를 마스크로 이용하여 실리콘기판에 소정의 깊이로 고농도 불순물 이온을 주입함으로써, 고농도 소오스/드레인 영역을 형성하는 공정과; 상기 고농도 소오스/드레인 영역을 열처리함으로써, 상기 고농도 소오스/드레인 영역의 측면방향에 저농도 소오스/드레인 영역을 형성함과 아울러 소오스/드레인 영역을 활성화 시키는 공정을 포함하여 구성되는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a MOS FET according to the present invention includes forming a nitride film on a silicon substrate on which an active region and a field region are defined and a first oxide film is formed, and then a photoresist. Forming a gate pattern; Removing the photoresist by removing the nitride film, the first oxide film, and the silicon substrate surface of the region where the gate is to be formed by etching the gate pattern as a mask to a predetermined depth; Injecting impurity ions for forming a channel stopper region into the silicon substrate exposed through the etching process; Removing the loss layer generated in the ion implantation process, forming a second oxide film for gate insulation, and then laminating polycrystalline silicon for forming the gate conductive layer on the entire surface of the device including the opening of the gate region; Etching the polysilicon to form a gate conductive layer; Etching the gate conductive layer as a mask to form a sidewall spacer made of nitride and a first oxide on the side surface of the gate conductive layer; Forming a high concentration source / drain region by implanting high concentration impurity ions at a predetermined depth into a silicon substrate using the gate conductive layer made of polysilicon and a sidewall spacer made of nitride and a first oxide as a mask; And heat-treating the high concentration source / drain region, thereby forming a low concentration source / drain region in the lateral direction of the high concentration source / drain region and activating the source / drain region.
이와 같은 공정으로 제조된 MOS FET는 LDD영역이 게이트영역과 과도하게 오버 랩이 되지 않고, 소오스/드레인 영역은 얕은 PN접합이 되며 채널스토퍼 영역이 게이트 영역에만 형성된다.In the MOS FET fabricated by this process, the LDD region is not excessively overlapped with the gate region, the source / drain region is a shallow PN junction, and the channel stopper region is formed only in the gate region.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제2도의 (a) 내지 (g)는 본 발명에 따른 모스페트(MOS FET)의 연속적인 제조공정을 수직단면도로 도시한 공정순서단면도로서, 이를 참조하여 제조공정을 상세히 살펴보면 다음과 같다.(A) to (g) of Figure 2 is a process sequence cross-sectional view showing a continuous manufacturing process of the MOSFET (MOS FET) according to the present invention in a vertical cross-sectional view, referring to this in detail as follows.
먼저, 제2도의 (a)에 도시된 바와 같이 필드산화막(102)을 형성하여 액티브영역과 필드영역이 정의되고 액티브영역 절연용 제1산화막이 형성된 실리콘기판(101) 위에 질화막(Nitride Film;111)을 증착한 후, 포토레지스트(Photo Resist;108)를 이용하여 게이트영역이 노출되는 패턴을 형성한다. 이때, 상기 질화막(111)은 최종적으로 형성되는 게이트도전층(105a)의 두께에 대응하도록 적층한다.First, as shown in FIG. 2A, a field oxide film 102 is formed to define an active region and a field region, and a nitride film 111 is formed on the silicon substrate 101 on which the first oxide film for insulating the active region is formed. ) Is deposited, and then a pattern is formed in which the gate region is exposed using a photoresist 108. In this case, the nitride film 111 is stacked to correspond to the thickness of the gate conductive layer 105a finally formed.
이후, 제2도의 (b)에 도시된 바와 같이 게이트영역이 노출된 상기 포토레지스트(108)을 이용하여 질화막(111)과 제1산화막(117) 및 실리콘기판(101)의 표면부를 소정의 깊이로 제거하는 건식에칭을 실행한 후 레지스트 마스크(108)를 제거한다. 이때, 상기 건식에칭은 패턴의 창으로 부터 수직으로 질화막(118)과 산화막(117), 게이트산화막(117) 및 실리콘기판(101)의 표면이 소정의 두께 만큼 제거되어 소오스/드레인 영역과 단차가 생기도록 에칭한다.Thereafter, as shown in FIG. 2B, the surface portion of the nitride film 111, the first oxide film 117, and the silicon substrate 101 is exposed to a predetermined depth using the photoresist 108 having the gate region exposed. The resist mask 108 is removed after performing dry etching. At this time, the dry etching is performed by removing the surface of the nitride film 118, the oxide film 117, the gate oxide film 117, and the silicon substrate 101 by a predetermined thickness vertically from the window of the pattern so that the source / drain region and the step difference are reduced. Etch to produce.
이어서, 제2도의 (c)에 도시된 바와 같이 상기 에칭공정을 통하여 형성된 질화막(111) 패턴을 이용하여 개구부의 하단부에 노출된 실리콘기판(101)에 채널스토퍼영역(103)을 형성하기 위한 불순물이온을 주입한다. 이때, 상기 이온이 직접 충돌한 실리콘기판(101)의 표면에 손실층(또는 결함층;118)이 발생한다.Subsequently, an impurity for forming the channel stopper region 103 in the silicon substrate 101 exposed at the lower end of the opening using the nitride film 111 pattern formed through the etching process as shown in FIG. Implant ions. At this time, a loss layer (or a defect layer) 118 is generated on the surface of the silicon substrate 101 directly collided with the ions.
그리고, 제2도의 (d)에 도시된 바와 같이 상기 손실층(118)을 습식에칭(Wet Etching) 또는 광산화법으로 제거한 후에, 상기 기판(101)의 식각면 표면에 게이트절연용 제2산화막(104)을 형성하고, 게이트도전층 형성용 다결정실리콘(105)을 개구부를 포함한 액티브영역 전체가 충분히 도포되도록 적층한다. 따라서 상기 제2산화막(104)은 게이트영역의 실리콘기판(101)에 단면이 'ㄷ'자형으로 형성된다.As shown in FIG. 2D, after the loss layer 118 is removed by wet etching or a photooxidation method, a second oxide film for gate insulation is formed on the surface of the etching surface of the substrate 101. 104 is formed, and the polysilicon 105 for forming the gate conductive layer is laminated so that the entire active region including the openings is sufficiently coated. Accordingly, the second oxide film 104 is formed in a '-' shape on the silicon substrate 101 in the gate region.
그 다음, 제2도의 (e)에 도시된 바와 같이 상기 다결정실리콘층(105)을 에치백(Etch Back)하여 게이트도전층(105a)을 형성한다. 따라서, 제2산화막(104) 상에 형성되는 게이트도전층(105a)은 하단부가 소오스/드레인 영역 표면위에 있는 제1산화막(117) 아래에 까지 형성된 구조를 갖게 된다. 그리고, 상기 소자의 표면은 평탄하게 되는데 표면중앙부에는 다결정실리콘으로 이루어진 게이트도전층(105a)의 상단면이, 그 양쪽으로는 질화막(111)의 상단면이 노출된다.Next, as shown in FIG. 2E, the polysilicon layer 105 is etched back to form a gate conductive layer 105a. Accordingly, the gate conductive layer 105a formed on the second oxide film 104 has a structure in which a lower end thereof is formed below the first oxide film 117 on the surface of the source / drain region. In addition, the surface of the device is flat, and the top surface of the gate conductive layer 105a made of polycrystalline silicon is exposed at the center portion thereof, and the top surface of the nitride film 111 is exposed at both sides thereof.
이어서, 제2도의 (f)에 도시된 바와 같이 상기 게이트도전층(105a)을 마스크로 이용하여 질화막(111)과 제1산화막(117)을 에칭함으로써, 게이트도전층(105a)의 측면에 질화막(111)과 제1산화막(117)으로 이루어지는 측벽스페이서(Nitride Side-Wall Spacer;111a)를 형성하고, 상기 게이트도전층(105a)와 측벽스페이서(111a)를 마스크로 이용하여 소정의 깊이로 고농도 불순물이온을 주입함으로써, 고농도 소오스/드레인 영역(113,114)을 형성한다.Subsequently, as illustrated in FIG. 2F, the nitride film 111 and the first oxide film 117 are etched using the gate conductive layer 105 a as a mask, thereby forming a nitride film on the side surface of the gate conductive layer 105 a. A sidewall spacer 111a including a 111 and a first oxide film 117 is formed, and the gate conductive layer 105a and the sidewall spacer 111a are used as a mask to have a high concentration at a predetermined depth. By implanting impurity ions, high concentration source / drain regions 113 and 114 are formed.
마지막으로, 제2도의 (g)에 도시된 바와 같이 상기 고농도 소오스/드레인 영역(113,114)에 대해 Ar가스 등이 포함된 분위기하에서 열처리 함으로써, 불순물이 확산되어 측벽스페이서(111a) 아래의 실리콘기판(101) 즉, 상기 고농도 이온영역(113,114)의 측면에 저농도 소오스/드레인 영역(109,110)을 형성한다. 이 때, 게이트도전층(105a) 및 이 게이트도전층(105a)의 하부단면과 하부측면을 절연하는 제2산화막(104)이 소오스/드레인 영역(109,110,113,114)의 기판표면보다 낮게 형성되어 있기 때문에, 상기와 같이 형성된 저농도영역(109,110)은 게이트영역 아래의 채널영역보다 높은 부분에 형성된다. 따라서 상기 LDD영역과 채널영역의 오우버랩(Overlap)이 발생하지 않게 된다.Finally, as shown in FIG. 2 (g), heat treatment is performed on the high concentration source / drain regions 113 and 114 in an atmosphere containing Ar gas, whereby impurities are diffused to form a silicon substrate under the sidewall spacer 111a. In other words, low concentration source / drain regions 109 and 110 are formed on the side surfaces of the high concentration ion regions 113 and 114. At this time, since the gate conductive layer 105a and the second oxide film 104 which insulate the lower end surface and the lower side surface of the gate conductive layer 105a are formed lower than the substrate surface of the source / drain regions 109, 110, 113, and 114, The low concentration regions 109 and 110 formed as described above are formed at a portion higher than the channel region under the gate region. Therefore, the overlap between the LDD region and the channel region does not occur.
확산을 위한 상기 열처리공정에 대한 다른 실시예로서, H2O 또는 O2 분위기에서 500-1000℃ 온도로 실시한다.As another embodiment of the heat treatment process for diffusion, it is carried out at a temperature of 500-1000 ℃ in H2O or O2 atmosphere.
그리고 저농도 소오스/드레인 영역(109,110)의 윤곽(Profile)에 대한 다른 실시예로서, 상기 1실시예의 측면확산과 더불어 고농도 영역(113,114)의 하단부로 불순물이온을 확산시켜 저농도 소오스/드레인 영역이 고농도 영역을 포위하도록 소오스/드레인 영역을 형성한다.As another embodiment of the profile of the low concentration source / drain regions 109 and 110, the impurity ions are diffused to the lower ends of the high concentration regions 113 and 114 together with the side diffusion of the first embodiment so that the low concentration source / drain regions become high concentration regions. The source / drain regions are formed to surround the.
상술한 바와 같이 본 발명에 따른 MOS FET의 제조방법은 공정이 단순하고 공정제어가 용이한 방법으로써, 셀프얼라인 방식으로 형성되는 게이트가 고미세하고 정교한 패턴으로 형성되는 장점이 있다.As described above, the method of manufacturing the MOS FET according to the present invention is a simple process and easy process control, and has the advantage that a gate formed in a self-aligned manner is formed in a fine and sophisticated pattern.
그리고, 셀프얼라인 방식과 질화물측벽스페이서를 이용하여 고농도 소오스/드레인 영역을 형성한 후에 확산공정을 통하여 저농도 소오스/드레인 영역을 형성함으로써, 제조공정이 단순하고 균일한 소오스/드레인 PN접합을 형성하며 접합깊이도 얇게 형성할 수 있는 효과가 있다.Then, after forming a high concentration source / drain region using a self-alignment method and a nitride sidewall spacer, a low concentration source / drain region is formed through a diffusion process, thereby forming a simple and uniform source / drain PN junction. The bonding depth can be formed thinner.
또한, 게이트영역 아래의 실리콘기판에만 채널스토퍼영역 형성용 불순물이온을 주입함으로써, 소오스/드레인 영역의 캐패시턴스 및 저항 성분을 감소시키고, 이와 더불어 핫캐리어 효과를 저감시키며, 채널 및 PN접합부의 파괴전압을 증가시켜 소자의 특성을 개선할 수 있는 장점이 있다.In addition, by implanting impurity ions for forming the channel stopper region only into the silicon substrate under the gate region, the capacitance and resistance components of the source / drain regions are reduced, the hot carrier effect is reduced, and the breakdown voltage of the channel and PN junctions is reduced. There is an advantage to improve the characteristics of the device by increasing.
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