JP7391326B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7391326B2 JP7391326B2 JP2019236007A JP2019236007A JP7391326B2 JP 7391326 B2 JP7391326 B2 JP 7391326B2 JP 2019236007 A JP2019236007 A JP 2019236007A JP 2019236007 A JP2019236007 A JP 2019236007A JP 7391326 B2 JP7391326 B2 JP 7391326B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- epitaxial layer
- substrate
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 134
- 239000000758 substrate Substances 0.000 claims description 69
- 239000000853 adhesive Substances 0.000 claims description 64
- 230000001070 adhesive effect Effects 0.000 claims description 64
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 27
- 239000012212 insulator Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 230000005684 electric field Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000005685 electric field effect Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
[2]前記第2の電極が導電性接着材を介して前記凸部に電気的に接続され、前記導電性接着材が前記平坦部上の前記外周部の直下に位置する場合、前記外周部と前記外周部の直下に位置する前記導電性接着材との間隔が3μm以上であり、前記導電性接着材が前記平坦部上の前記外周部の直下に位置しない場合、前記外周部と前記平坦部との間隔が3μm以上である、上記[1]に記載の半導体装置。
[3]前記凸部と前記平坦部が一体である、上記[1]又は[2]に記載の半導体装置。
[4]前記リードフレームが、前記凸部の裏側に凹部を有する、上記[3]に記載の半導体装置。
[5]前記凸部と前記平坦部が電気的に接続された別体である、上記[1]又は[2]に記載の半導体装置。
[6]前記基板が、前記エピタキシャル層と反対側の面に凹部を有し、前記凹部の底面上の前記第1の電極にボンディングワイヤーが接続された、上記[1]~[5]のいずれか1項に記載の半導体装置。
[7]リードフレームと、Ga 2 O 3 系半導体からなる基板と、前記基板上のGa 2 O 3 系半導体からなるエピタキシャル層と、前記基板側に接続された第1の電極と、前記エピタキシャル層側に接続された第2の電極とを有する半導体素子と、を備え、前記半導体素子が、前記リードフレーム上にフェイスダウン実装され、前記エピタキシャル層と前記リードフレームとの間隔が、3μm以上であり、前記基板が、前記エピタキシャル層と反対側の面に凹部を有し、前記凹部の底面上の前記第1の電極にボンディングワイヤーが接続された、半導体装置。
[8]リードフレームと、Ga 2 O 3 系半導体からなる基板と、前記基板上のGa 2 O 3 系半導体からなるエピタキシャル層と、前記基板側に接続された第1の電極と、前記エピタキシャル層側に接続された第2の電極とを有する半導体素子と、前記第2の電極の外周部と側面を覆う絶縁体と、を備え、前記半導体素子が、前記リードフレーム上に前記絶縁体に支えられてフェイスダウン実装され、前記第2の電極が導電性接着材を介して前記リードフレームに電気的に接続され、前記エピタキシャル層と前記リードフレームとの間隔が、3μm以上である、半導体装置。
本発明の第1の実施の形態では、縦型の半導体素子としてショットキーバリアダイオード(SBD)を用いる。
図1(a)、(b)は、第1の実施の形態に係る半導体装置1の垂直断面図である。半導体装置1は、リードフレーム20と、リードフレーム20上にフェイスダウン実装されたSBD10とを備える。SBD10は、導電性接着材30によりリードフレーム20に固定され、かつ、電気的に接続されている。
本発明の第2の実施の形態は、リードフレームの構成において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略又は簡略化する場合がある。
図6は、第2の実施の形態に係る半導体装置3の垂直断面図である。半導体装置3は、リードフレーム40と、リードフレーム40上にフェイスダウン実装されたSBD10とを備える。SBD10は、導電性接着材30によりリードフレーム40に固定され、かつ、電気的に接続されている。
本発明の第3の実施の形態は、リードフレームに凸部を設けずにエピタキシャル層とリードフレームとの間隔を広げている点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略又は簡略化する場合がある。
図8は、第3の実施の形態に係る半導体装置4の垂直断面図である。半導体装置4は、リードフレーム50と、リードフレーム50上にフェイスダウン実装されたSBD10とを備える。SBD10は、導電性接着材30によりリードフレーム50に固定され、かつ、電気的に接続されている。
本発明の第4の実施の形態は、基板の上面に凹部が設けられている点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略又は簡略化する場合がある。
図9は、第4の実施の形態に係る半導体装置5の垂直断面図である。半導体装置5は、リードフレーム20と、リードフレーム20上にフェイスダウン実装されたSBD10aとを備える。SBD10aは、導電性接着材30によりリードフレーム20に固定され、かつ、電気的に接続されている。
本発明の第5の実施の形態は、縦型の半導体素子としてトレンチ型SBDを用いる点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略又は簡略化する場合がある。
図10は、第5の実施の形態に係る半導体装置6の垂直断面図である。半導体装置6は、リードフレーム20と、リードフレーム20上にフェイスダウン実装されたトレンチ型SBD60とを備える。SBD60は、導電性接着材30によりリードフレーム20の凸部200上に固定され、かつ、電気的に接続されている。
本発明の第6の実施の形態は、縦型の半導体素子として接合型電界効果トランジスタ(JFET)を用いる点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略又は簡略化する場合がある。
図11は、第6の実施の形態に係る半導体装置7の垂直断面図である。半導体装置7は、リードフレーム80と、リードフレーム80上にフェイスダウン実装されたJFET70とを備える。JFET70は、導電性接着材30によりリードフレーム80に固定され、かつ、電気的に接続されている。
上記第1~6の実施の形態によれば、Ga2O3系半導体からなる縦型の半導体素子をフェイスダウン実装し、また、エピタキシャル層の外周部とその直下のリードフレームや導電性接着材との距離を大きくすることにより、電界効果による耐圧の低下を抑えつつ、半導体素子の放熱性を向上させることができる。
Claims (8)
- 表面に凸部を有するリードフレームと、
Ga2O3系半導体からなる基板と、前記基板に積層されたGa2O3系半導体からなるエピタキシャル層と、前記基板の前記エピタキシャル層と反対側の面に接続された第1の電極と、前記エピタキシャル層の前記基板と反対側の面に接続され、外周部にフィールドプレート部を有する第2の電極とを有する、前記リードフレーム上にフェイスダウン実装された半導体素子と、
を備え、
前記半導体素子が前記凸部上に固定され、
前記エピタキシャル層の前記フィールドプレート部の外側に位置する外周部が、前記リードフレームの前記凸部が設けられていない部分である平坦部の直上に位置する、
半導体装置。 - 前記第2の電極が導電性接着材を介して前記凸部に電気的に接続され、
前記導電性接着材が前記平坦部上の前記外周部の直下に位置する場合、前記外周部と前記外周部の直下に位置する前記導電性接着材との間隔が3μm以上であり、前記導電性接着材が前記平坦部上の前記外周部の直下に位置しない場合、前記外周部と前記平坦部との間隔が3μm以上である、
請求項1に記載の半導体装置。 - 前記凸部と前記平坦部が一体である、
請求項1又は2に記載の半導体装置。 - 前記リードフレームが、前記凸部の裏側に凹部を有する、
請求項3に記載の半導体装置。 - 前記凸部と前記平坦部が電気的に接続された別体である、
請求項1又は2に記載の半導体装置。 - 前記基板が、前記エピタキシャル層と反対側の面に凹部を有し、
前記凹部の底面上の前記第1の電極にボンディングワイヤーが接続された、
請求項1から5のいずれか1項に記載の半導体装置。 - リードフレームと、
Ga2O3系半導体からなる基板と、前記基板上のGa2O3系半導体からなるエピタキシャル層と、前記基板側に接続された第1の電極と、前記エピタキシャル層側に接続された第2の電極とを有する半導体素子と、
を備え、
前記半導体素子が、前記リードフレーム上にフェイスダウン実装され、
前記エピタキシャル層と前記リードフレームとの間隔が、3μm以上であり、
前記基板が、前記エピタキシャル層と反対側の面に凹部を有し、
前記凹部の底面上の前記第1の電極にボンディングワイヤーが接続された、
半導体装置。 - リードフレームと、
Ga2O3系半導体からなる基板と、前記基板上のGa2O3系半導体からなるエピタキシャル層と、前記基板側に接続された第1の電極と、前記エピタキシャル層側に接続された第2の電極とを有する半導体素子と、
前記第2の電極の外周部と側面を覆う絶縁体と、
を備え、
前記半導体素子が、前記リードフレーム上に前記絶縁体に支えられてフェイスダウン実装され、
前記第2の電極が導電性接着材を介して前記リードフレームに電気的に接続され、
前記エピタキシャル層と前記リードフレームとの間隔が、3μm以上である、
半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019236007A JP7391326B2 (ja) | 2019-12-26 | 2019-12-26 | 半導体装置 |
EP20905852.8A EP4084064A4 (en) | 2019-12-26 | 2020-12-21 | SEMICONDUCTOR DEVICE |
CN202080090359.6A CN114846593A (zh) | 2019-12-26 | 2020-12-21 | 半导体装置 |
PCT/JP2020/047652 WO2021132144A1 (ja) | 2019-12-26 | 2020-12-21 | 半導体装置 |
US17/788,860 US20230034806A1 (en) | 2019-12-26 | 2020-12-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019236007A JP7391326B2 (ja) | 2019-12-26 | 2019-12-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2021106190A JP2021106190A (ja) | 2021-07-26 |
JP7391326B2 true JP7391326B2 (ja) | 2023-12-05 |
Family
ID=76574754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019236007A Active JP7391326B2 (ja) | 2019-12-26 | 2019-12-26 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230034806A1 (ja) |
EP (1) | EP4084064A4 (ja) |
JP (1) | JP7391326B2 (ja) |
CN (1) | CN114846593A (ja) |
WO (1) | WO2021132144A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020014919A (ja) * | 2019-10-31 | 2020-01-30 | 株式会社三洋物産 | 遊技機 |
JP2020014971A (ja) * | 2019-11-06 | 2020-01-30 | 株式会社三洋物産 | 遊技機 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004214368A (ja) | 2002-12-27 | 2004-07-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2017045969A (ja) | 2015-08-28 | 2017-03-02 | 株式会社タムラ製作所 | ショットキーバリアダイオード |
US20180114744A1 (en) | 2015-06-19 | 2018-04-26 | Osram Opto Semiconductors Gmbh | Method of producing an optoelectronic component and optoelectronic component |
JP2018078177A (ja) | 2016-11-09 | 2018-05-17 | Tdk株式会社 | ショットキーバリアダイオード及びこれを備える電子回路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2851946A1 (en) * | 2013-09-19 | 2015-03-25 | Nxp B.V. | Surge protection device |
JP6563093B1 (ja) | 2018-08-10 | 2019-08-21 | ローム株式会社 | SiC半導体装置 |
-
2019
- 2019-12-26 JP JP2019236007A patent/JP7391326B2/ja active Active
-
2020
- 2020-12-21 EP EP20905852.8A patent/EP4084064A4/en active Pending
- 2020-12-21 WO PCT/JP2020/047652 patent/WO2021132144A1/ja unknown
- 2020-12-21 CN CN202080090359.6A patent/CN114846593A/zh active Pending
- 2020-12-21 US US17/788,860 patent/US20230034806A1/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004214368A (ja) | 2002-12-27 | 2004-07-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US20180114744A1 (en) | 2015-06-19 | 2018-04-26 | Osram Opto Semiconductors Gmbh | Method of producing an optoelectronic component and optoelectronic component |
JP2017045969A (ja) | 2015-08-28 | 2017-03-02 | 株式会社タムラ製作所 | ショットキーバリアダイオード |
JP2018078177A (ja) | 2016-11-09 | 2018-05-17 | Tdk株式会社 | ショットキーバリアダイオード及びこれを備える電子回路 |
Also Published As
Publication number | Publication date |
---|---|
CN114846593A (zh) | 2022-08-02 |
EP4084064A1 (en) | 2022-11-02 |
EP4084064A4 (en) | 2024-01-24 |
WO2021132144A1 (ja) | 2021-07-01 |
US20230034806A1 (en) | 2023-02-02 |
JP2021106190A (ja) | 2021-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107210241B (zh) | 功率半导体装置 | |
JP5240966B2 (ja) | 窒化ガリウム半導体素子 | |
JP6043970B2 (ja) | 半導体装置 | |
JPWO2019003861A1 (ja) | 酸化物半導体装置、および、酸化物半導体装置の製造方法 | |
JP2008545279A (ja) | サージ能力が向上されたショットキーダイオード | |
WO2021132144A1 (ja) | 半導体装置 | |
JP2013239607A (ja) | 半導体装置 | |
JP6102598B2 (ja) | パワーモジュール | |
WO2020213603A1 (ja) | SiC半導体装置 | |
US8937317B2 (en) | Method and system for co-packaging gallium nitride electronics | |
JP2014187086A (ja) | 半導体装置 | |
US10727332B2 (en) | Semiconductor device | |
JP7231382B2 (ja) | 半導体装置 | |
US20240006364A1 (en) | Semiconductor device | |
US20230030874A1 (en) | Semiconductor element, method for manufacturing semiconductor element, semiconductor device, and method for manufacturing semiconductor device | |
CN113410288B (zh) | 半导体装置 | |
JP2019145667A (ja) | 半導体装置および半導体装置の製造方法 | |
JP6579653B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP7313197B2 (ja) | 半導体装置 | |
JP6951311B2 (ja) | 半導体装置 | |
US20210384091A1 (en) | Power Semiconductor Device with Free-Floating Packaging Concept | |
JP2015026669A (ja) | 窒化物半導体装置 | |
JP2004214368A (ja) | 半導体装置 | |
JP2008177475A (ja) | 電子部品 | |
US20230411319A1 (en) | Semiconductor device and method of making semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20221215 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20221219 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230801 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230926 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20231024 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20231114 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7391326 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |