JP7367580B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7367580B2
JP7367580B2 JP2020051131A JP2020051131A JP7367580B2 JP 7367580 B2 JP7367580 B2 JP 7367580B2 JP 2020051131 A JP2020051131 A JP 2020051131A JP 2020051131 A JP2020051131 A JP 2020051131A JP 7367580 B2 JP7367580 B2 JP 7367580B2
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Prior art keywords
interlayer film
electrode
semiconductor device
wire
polysilicon layer
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JP2020051131A
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JP2021150587A (ja
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大介 平田
晃央 山本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2020051131A priority Critical patent/JP7367580B2/ja
Priority to US17/070,617 priority patent/US11410946B2/en
Priority to DE102020133695.0A priority patent/DE102020133695A1/de
Priority to CN202110291207.9A priority patent/CN113437139A/zh
Publication of JP2021150587A publication Critical patent/JP2021150587A/ja
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Publication of JP7367580B2 publication Critical patent/JP7367580B2/ja
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Description

本開示は、半導体装置に関する。
アルミ電極にワイヤボンディングする際に、超音波振動方向に沿ってアルミニウムが排斥される。従って、ワイヤとアルミ電極の接合強度にばらつきが発生するため、半導体装置の信頼性を低下させる一因となっていた。これに対して、ボンディング領域においてアルミ電極の下に部分的に層間膜を設けた半導体装置が開示されている（例えば、特許文献１参照）。これにより、アルミ電極の表面に凹凸が生じるため、ワイヤボンディング時のアルミニウムの排斥を抑制することができる。
特開２０１２－１０９４１９号公報
アルミ電極の下にバリアメタル層が形成されている場合がある。バリアメタルと層間膜との密着性は弱いため、半導体装置の信頼性が低下するという問題があった。
本開示は、上述のような課題を解決するためになされたもので、その目的はワイヤボンドの接合強度のばらつきを低減し、信頼性を向上させることができる半導体装置を得るものである。
本開示に係る半導体装置は、ワイヤとのボンディング領域を備える半導体装置であって、半導体基板と、前記ボンディング領域において前記半導体基板の主面に設けられた酸化膜と、前記酸化膜の上に設けられたポリシリコン層と、前記ポリシリコン層の上に部分的に設けられた層間膜と、前記ポリシリコン層と前記層間膜の上に直接的に設けられたバリアメタルと、前記バリアメタルの上に設けられた電極とを備え、前記電極の表面は前記層間膜のパターンに合わせて凹凸形状になっており、前記層間膜は、前記主面に対して垂直な平面視でドット状のパターンを有し、前記ドット状のパターンのドットの縦横の幅とドットの間隔は共に２ｕｍ～５ｕｍであり、前記電極の凸部に前記ワイヤをボンディングし、前記ワイヤと前記電極の表面との接合の最外郭により囲まれた面積が前記電極に直接的に接する前記ワイヤの面積より大きいことを特徴とする。
本開示では、ボンディング領域において層間膜が部分的に設けられ、その上にバリアメタル及びアルミ電極が設けられている。これにより、ワイヤボンディング時に層間膜がバリアメタル及びアルミ電極に対してアンカーとなるため、アルミ電極の構成金属の排斥を抑制することができる。従って、ワイヤボンドの接合強度のばらつきを低減することができる。また、層間膜の下にポリシリコン層を形成する。バリアメタルとポリシリコン層との密着性はバリアメタルと層間膜との密着性よりも強い。従って、バリアメタルと層間膜との密着性の弱さをポリシリコン層が補うことでバリアメタルの密着性が向上するため、半導体装置の信頼性を向上させることができる。
実施の形態１に係る半導体装置を示す断面図である。 実施の形態１に係る半導体装置のボンディング領域における層間膜のパターンを示す平面図である。 実施の形態２に係る半導体装置のボンディング領域における層間膜のパターンを示す平面図である。
実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、実施の形態１に係る半導体装置を示す断面図である。半導体基板１はｐ型であり、半導体基板１の表層にｎ型のソース領域２及びドレイン領域３が互いに離間して設けられている。ソース領域２とドレイン領域３の間の半導体基板１の上にゲート絶縁膜４を介してゲート電極５が形成されている。ゲート電極５は層間膜７で覆われている。層間膜７は酸化膜であり、例えばＴＥＯＳ／ＢＰＳＧ／ＴＥＯＳの積層構造である。
ソース電極８が層間膜７の開口を介してソース領域２に接続されている。ドレイン電極９が層間膜７の開口を介してドレイン領域３に接続されている。ソース電極８及びドレイン電極９はバリアメタル１０及びアルミ電極１１で構成されている。バリアメタル１０はアルミ電極１１と半導体基板１のコンタクト抵抗の増大を抑制するために設けられ、例えばＴｉ／ＴｉＮの積層構造である。このように、半導体基板１の上にＭＯＳＦＥＴなどのトランジスタ１２が構成されている。
半導体装置は、トランジスタ１２又はダイオードなど半導体素子の電気的特性に影響を及ぼさない無効領域において、ワイヤ１４とのボンディング領域を備える。ボンディング領域において、半導体基板１の上に膜厚１６００ｎｍの酸化膜６が設けられている。酸化膜６は半導体素子間の分離層であり、例えばＳｉＯ２などである。酸化膜６の上に膜厚４５０ｎｍのポリシリコン層１３が設けられている。ポリシリコン層１３の上に膜厚１５００ｎｍの層間膜７が部分的に設けられている。膜厚１００ｎｍのバリアメタル１０がポリシリコン層１３と層間膜７の上に直接的に設けられ、ポリシリコン層１３と層間膜７に接触している。バリアメタル１０の上に膜厚１３０００ｎｍのアルミ電極１１が設けられている。
ここで、層間膜７の上方が凸、層間膜７同士の間の領域の上方が凹になる。即ち、アルミ電極１１の表面は層間膜７のパターンに合わせて凹凸形状になっている。ボンディング領域において、表面が凹凸形状のアルミ電極１１にワイヤ１４がボンディングされる。ワイヤ１４は例えば銅細線である。なお、銅細線は硬度が高く、ボンディング性が悪いため、ボンディング時にアルミ電極１１の構成金属が排斥されやすい。
ボンディング領域のアルミ電極１１は、トランジスタ１２のソース電極８又はドレイン電極９に電気的に接続されている。従って、ワイヤ１４を介してトランジスタ１２は外部回路と接続される。
本実施の形態では、ボンディング領域において層間膜７が部分的に設けられ、その上にバリアメタル１０及びアルミ電極１１が設けられている。これにより、ワイヤボンディング時に層間膜７がバリアメタル１０及びアルミ電極１１に対してアンカーとなるため、アルミ電極１１の構成金属であるアルミニウムの排斥を抑制することができる。従って、ワイヤボンドの接合強度のばらつきを低減することができる。また、層間膜７の下にポリシリコン層１３を形成する。バリアメタル１０とポリシリコン層１３との密着性はバリアメタル１０と層間膜７との密着性よりも強い。従って、バリアメタル１０と層間膜７との密着性の弱さをポリシリコン層１３が補うことでバリアメタル１０の密着性が向上するため、半導体装置の信頼性を向上させることができる。
ポリシリコン層１３とゲート電極５は同じ材質からなる。このため、製造プロセスにおいて両者を同時に形成することができる。ただし、ポリシリコン層１３とゲート電極５は互いに接続されていない。
ソース電極８及びドレイン電極９を半導体基板１にコンタクトさせるため、層間膜７をエッチングして開口を形成する。この際にボンディング領域における層間膜７もパターニングする。図２は、実施の形態１に係る半導体装置のボンディング領域における層間膜のパターンを示す平面図である。層間膜７は、半導体基板１の主面に対して垂直な平面視でドット状のパターンを有する。ドットの縦横の幅をＸ、ドットの間隔をＹとすると、Ｘ，Ｙ共に２ｕｍ～５ｕｍである。ドット状の層間膜７の上に設けられたアルミ電極１１も同様にドット状に***する。従って、ワイヤ１４とアルミ電極１１の接触面積が狭くなるのでアルミ電極１１のアルミニウムの排斥のばらつきを抑えることができる。
実施の形態２．
図３は、実施の形態２に係る半導体装置のボンディング領域における層間膜のパターンを示す平面図である。層間膜７は、半導体基板１の主面に対して垂直な平面視でメッシュ状のパターンを有する。メッシュの開口の縦横の幅をＸ、メッシュの開口の間隔をＹとすると、Ｘ，Ｙ共に２ｕｍ～５ｕｍである。その他の構成は実施の形態１と同様である。
層間膜７がメッシュ状であるため、層間膜７がドット状の場合に比べてワイヤ１４とアルミ電極１１の接触面積が広くなる。これにより、ドット状の場合よりも弱い力でボンディングすることができるため、半導体素子へのダメージが軽減される。ただし、アルミ電極１１のアルミニウムの排斥は少しばらつく。
なお、半導体基板１は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体装置は、許容電流密度が高いため、ワイヤ径の大口径化又はワイヤ本数の増加による接合強度のばらつきを低減することができる。この半導体装置を用いることで、この半導体装置を組み込んだ半導体モジュールも小型化・高集積化できる。また、半導体装置の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、半導体装置の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
１ 半導体基板、６ 酸化膜、７ 層間膜、１０ バリアメタル、１１ アルミ電極、１３ ポリシリコン層、１４ ワイヤ

Claims (3)

  1. ワイヤとのボンディング領域を備える半導体装置であって、
    半導体基板と、
    前記ボンディング領域において前記半導体基板の主面に設けられた酸化膜と、
    前記酸化膜の上に設けられたポリシリコン層と、
    前記ポリシリコン層の上に部分的に設けられた層間膜と、
    前記ポリシリコン層と前記層間膜の上に直接的に設けられたバリアメタルと、
    前記バリアメタルの上に設けられた電極とを備え、
    前記電極の表面は前記層間膜のパターンに合わせて凹凸形状になっており、
    前記層間膜は、前記主面に対して垂直な平面視でドット状のパターンを有し、
    前記ドット状のパターンのドットの縦横の幅とドットの間隔は共に２ｕｍ～５ｕｍであり、
    前記電極の凸部に前記ワイヤをボンディングし、
    前記ワイヤと前記電極の表面との接合の最外郭により囲まれた面積が前記電極に直接的に接する前記ワイヤの面積より大きいことを特徴とする半導体装置。
  2. 前記半導体基板に設けられ、ゲート電極を有するトランジスタを更に備え、
    前記ポリシリコン層と前記ゲート電極は同じ材質からなることを特徴とする請求項１に記載の半導体装置。
  3. 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１又は２に記載の半導体装置。
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