JP7352660B2 - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
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- JP7352660B2 JP7352660B2 JP2021572928A JP2021572928A JP7352660B2 JP 7352660 B2 JP7352660 B2 JP 7352660B2 JP 2021572928 A JP2021572928 A JP 2021572928A JP 2021572928 A JP2021572928 A JP 2021572928A JP 7352660 B2 JP7352660 B2 JP 7352660B2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
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- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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Description
Claims (9)
- 半導体デバイスであって、
共通ソース層、基板に配置されたゲート層および絶縁層を含む層のスタックであって、前記ゲート層および絶縁層が交互に積み重ねられ、前記共通ソース層は導電層およびソース層を含む、層のスタック、
アレイ領域に形成されたチャネル構造のアレイであって、チャネル構造が直列構成のトランジスタのスタックを形成する前記層のスタックを通って延び、前記チャネル構造が前記共通ソース層と導電して接続されたチャネル層を含み、前記共通ソース層がアレイ領域と階段領域に延びる、チャネル構造のアレイ、
前記階段領域に配置されたコンタクト構造であって、前記共通ソース層との導電性接続を形成する、コンタクト構造、および
前記共通ソース層と導電的に接続された下部導電層を備えたゲートラインカット構造を含み、
前記下部導電層は、前記導電層とは異なる材料を含む、半導体デバイス。 - 前記導電層が金属およびシリコンを含む金属ケイ化物層から形成され、前記金属がチタン(Ti)、コバルト(Co)、ニッケル(Ni)、および白金(Pt)のうちの少なくとも1つを含み、前記ソース層はシリコン材料である、請求項1に記載の半導体デバイス。
- 前記ゲートラインカット構造が、前記下部導電層の上にある上部絶縁部分を含む、請求項1に記載の半導体デバイス。
- 前記下部導電層が、
前記共通ソース層の前記導電層と導電して接続されているケイ化物層を含む、請求項1に記載の半導体デバイス。 - 前記アレイ領域は、ブロック内の第1のアレイ領域であり、前記コンタクト構造は、前記ブロック内の前記第1のアレイ領域と第2のアレイ領域との間に位置する、前記階段領域に配置される、請求項1に記載の半導体デバイス。
- 前記コンタクト構造が第1のコンタクト構造であり、前記階段領域が前記アレイ領域の第1の側に位置する第1の階段領域であり、前記半導体デバイスがさらに、
前記アレイ領域の前記第1の側と反対の第2の側に位置する第2の階段領域に配置された第2のコンタクト構造であって、前記第2の階段領域上に前記共通ソース層が延び、前記共通ソース層と導電して接続されている第2のコンタクト構造、を備える、請求項1に記載の半導体デバイス。 - 表側および裏側を有する半導体層、
前記半導体層の前記表側に形成されたトランジスタ、
前記半導体層の前記表側の結合構造であって、前記基板の前記表側の対応する結合構造と整列および結合されている結合構造、および
前記基板の前記裏側に配置されたコンタクトパッドをさらに備える、請求項1に記載の半導体デバイス。 - 表側および裏側を有する半導体層、
前記半導体層の前記表側に形成されたトランジスタ、
前記半導体層の前記表側の結合構造であって、前記基板の前記表側の対応する結合構造と整列および結合されている結合構造、および
前記半導体層の前記裏側に配置されたコンタクトパッドをさらに備える、請求項1に記載の半導体デバイス。 - 前記半導体デバイスは、前記基板の前記裏側または前記半導体層の前記裏側から外部回路に接続されている、請求項7または8に記載の半導体デバイス。
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WO2021237643A1 (en) | 2021-12-02 |
KR20220004207A (ko) | 2022-01-11 |
JP2022539668A (ja) | 2022-09-13 |
US11948901B2 (en) | 2024-04-02 |
US20240250050A1 (en) | 2024-07-25 |
TW202145524A (zh) | 2021-12-01 |
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