JP7350768B2 - 検知装置、半導体装置 - Google Patents
検知装置、半導体装置 Download PDFInfo
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- JP7350768B2 JP7350768B2 JP2020552182A JP2020552182A JP7350768B2 JP 7350768 B2 JP7350768 B2 JP 7350768B2 JP 2020552182 A JP2020552182 A JP 2020552182A JP 2020552182 A JP2020552182 A JP 2020552182A JP 7350768 B2 JP7350768 B2 JP 7350768B2
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Images
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Description
図2Aは、半導体装置を説明するブロック図である。図2B1、図2B2、及び図2Cは、半導体装置を説明する回路図である。
図3は、半導体装置を説明するブロック図である。
図4A1乃至図4A3、及び図4Bは、半導体装置を説明する回路図である。
図5は、半導体装置を説明するブロック図である。
図6A1乃至図6A4は、半導体装置を説明する回路図である。
図7は、半導体装置を説明する回路図である。
図8Aは、半導体装置を説明するブロック図である。図8Bは、半導体装置を説明する回路図である。
図9Aは、半導体装置を説明する回路図である。図9Bは、半導体装置を説明するタイミングチャートである。
図10Aは、半導体装置を説明する回路図である。図10Bは、半導体装置を説明するタイミングチャートである。
図11は、半導体装置を説明する回路図である。
図12は、半導体装置を説明する回路図である。
図13Aは、トランジスタの一例を示す上面図である。図13B及び図13Cは、トランジスタの一例を示す断面図である。
図14Aは、トランジスタの一例を示す上面図である。図14B及び図14Cは、トランジスタの一例を示す断面図である。
図15は、半導体装置を説明するブロック図である。
図16Aは、バッテリ保護ICのブロック図である。図16Bは、バッテリ保護ICの斜視図である。
図17A及び図17Bは、電子機器を説明する図である。
図18A乃至図18Cは、電子機器を説明する図である。
図19A1及び図19A2、ならびに図19B1乃至図19B4は、電子機器を説明する図である。
図20は、試作デバイスを説明するブロック図である。
図21Aは、試作デバイス写真である。図21Bは、トランジスタの断面を説明する図である。
図22は、試作デバイスの測定データを説明する図である。
図23Aは、試作デバイスシミュレーションデータである。図23Bは、試作デバイスの測定データである。
本実施の形態では、半導体装置について、図1乃至図12を用いて説明する。本実施の形態で説明する半導体装置は、ラッチ回路として機能する。また複数のラッチ回路をカスケード接続することで、カウンタ回路として機能させることができる。
本実施の形態では、実施の形態1に示すトランジスタの一例について、図13、及び図14を用いて説明する。
本実施の形態では、実施の形態1で説明したラッチ回路を有するカウンタ回路を適用した半導体装置について説明する。最初に、図2で説明した3進カウンタ回路、図3で説明した6進カウンタ回路、図5で説明した10進カウンタ回路の出力を時計に適用した例を説明する。次に、3進カウンタ回路、6進カウンタ回路、10進カウンタ回路の出力をバッテリ保護ICに適用した例を説明する。
本実施の形態では、トランジスタのチャネル形成領域に好適に用いることができる金属酸化物について説明する。
本実施の形態では、本発明の一態様に係る半導体装置を用いることができる電子機器の一例を説明する。
Claims (4)
- ダイナミック回路で構成されるラッチ回路を有する半導体装置であって、
前記ラッチ回路は、第1の回路と、第2の回路と、第1乃至第3の容量素子と、第1乃至第6のクロック入力端子と、信号入力端子と、第1の出力端子と、第2の出力端子とを有し、
前記第1の回路は、デコード機能を有し、
前記第1乃至第6のクロック入力端子には、順に第1乃至第6のクロック信号が与えられる機能を有し、
前記第1のクロック信号に”H”の信号が与えられる期間において、
前記第1の回路は、前記信号入力端子を介して複数の入力信号が与えられる機能を有し、
前記第1の容量素子の電位は、前記第1の回路がデコードした結果によって更新される機能を有し、
前記第2のクロック信号に”H”の信号が与えられる期間において、
前記第2の容量素子の電位は、前記第1の容量素子の電位に応じて更新される機能を有し、
前記第1の出力端子には、前記第2の容量素子の電位が、第1の出力信号として与えられる機能を有し、
前記第3のクロック信号に”H”の信号が与えられる期間において、
前記第3の容量素子の電位は、前記第2の容量素子の電位に応じて更新される機能を有し、
前記第2の出力端子には、前記第3の容量素子の電位が、第2の出力信号として与えられる機能を有し、
前記第4のクロック信号に”H”の信号が与えられる期間において、
前記第1の容量素子は、プリチャージされ、
前記第5のクロック信号に”H”の信号が与えられる期間において、
前記第2の容量素子は、プリチャージされ、
前記第6のクロック信号に”H”の信号が与えられる期間において、
前記第3の容量素子は、プリチャージされ、
前記第2の回路は、前記第2のクロック入力端子に与えられる前記第2のクロック信号から、第7のクロック信号と、第8のクロック信号とを生成し、
前記第7のクロック信号に”H”の信号が与えられる期間において、前記ラッチ回路は、前記入力信号をデコードした結果をラッチし、前記ラッチした結果を前記第1の出力信号に出力する機能を有し、
前記第8のクロック信号に”H”の信号が与えられる期間において、
前記第5のクロック入力端子に前記第5のクロック信号が与えられることで前記第2の容量素子は、プリチャージされ、
前記第1の出力信号が”H”の信号であれば、前記プリチャージされた前記第2の容量素子の電位が、”H”の信号として前記第1の出力信号に出力され、
前記第1の出力信号が”L”の信号であれば、前記第2の出力信号によって前記第2の容量素子の電位が放電され、
前記第2の容量素子の電位が、”L”の信号として前記第1の出力信号に出力される半導体装置。 - 請求項1において、
カスケード接続された複数の前記ラッチ回路を有し、
複数の前記ラッチ回路が、カウンタ回路として機能する、半導体装置。 - 請求項1または2のラッチ回路は、
第1乃至第5のトランジスタを有し、
前記第1のクロック入力端子は、前記第1のトランジスタのゲートと電気的に接続され、
前記第3のクロック入力端子は、前記第3のトランジスタのゲートと電気的に接続され、
前記第5のクロック入力端子は、前記第5のトランジスタのゲートと電気的に接続され、
前記第2の容量素子の電極の一方は、前記第4のトランジスタのゲートと電気的に接続され前記第3の容量素子の電極の一方は、前記第5のトランジスタのゲートと電気的に接続され前記第1乃至第5のトランジスタは、半導体層に金属酸化物を有し、
前記第1乃至第5のトランジスタは、バックゲートを有し、
前記第1乃至第3のトランジスタのバックゲートには、前記第4、第5のトランジスタのバックゲートと異なる電位が与えられる半導体装置。 - 請求項2に記載の半導体装置と、検知回路と、バッテリと、を有する検知装置であって、
前記半導体装置の出力信号が、前記検知回路に与えられ、
前記検知回路は、前記出力信号を前記バッテリの出力電位を監視するモニタ周期として用いる検知装置。
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JP2000349163A (ja) | 1999-06-04 | 2000-12-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2016105590A (ja) | 2014-11-21 | 2016-06-09 | 株式会社半導体エネルギー研究所 | 論理回路、および論理回路を有する半導体装置 |
JP6010498B2 (ja) | 2013-03-29 | 2016-10-19 | ユニチカトレーディング株式会社 | 汗滲防止機能を有するインナー用編地 |
JP7177000B2 (ja) | 2019-05-16 | 2022-11-22 | 日立Astemo株式会社 | 演算装置および演算方法 |
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JPS51112142A (en) | 1976-03-08 | 1976-10-04 | Toshiba Corp | Dynamic type shift register circuit |
JPS6010498A (ja) | 1983-06-30 | 1985-01-19 | Asahi Glass Co Ltd | シフトレジスタ |
JPH07177000A (ja) | 1993-12-17 | 1995-07-14 | Kawasaki Steel Corp | Tフリップフロップ |
CN100340060C (zh) | 2003-08-20 | 2007-09-26 | 松下电器产业株式会社 | 半导体集成电路 |
JP4606810B2 (ja) | 2003-08-20 | 2011-01-05 | パナソニック株式会社 | 半導体集積回路 |
US7466572B1 (en) * | 2006-04-10 | 2008-12-16 | Marvell International Ltd. | Three phase voltage tripler |
US20130214851A1 (en) * | 2012-02-16 | 2013-08-22 | International Business Machines Corporation | Voltage pump using high-performance, thin-oxide devices and methods of use |
JP2015032325A (ja) * | 2013-07-31 | 2015-02-16 | マイクロン テクノロジー, インク. | 半導体装置 |
JP6546452B2 (ja) * | 2015-06-02 | 2019-07-17 | ローム株式会社 | 電池残量推定装置、電池残量推定システム、およびバッテリーパック |
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JP2000349163A (ja) | 1999-06-04 | 2000-12-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP6010498B2 (ja) | 2013-03-29 | 2016-10-19 | ユニチカトレーディング株式会社 | 汗滲防止機能を有するインナー用編地 |
JP2016105590A (ja) | 2014-11-21 | 2016-06-09 | 株式会社半導体エネルギー研究所 | 論理回路、および論理回路を有する半導体装置 |
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JPWO2020084407A1 (ja) | 2021-12-23 |
KR20210079307A (ko) | 2021-06-29 |
US11909397B2 (en) | 2024-02-20 |
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