JP7134077B2 - 半導体装置および電子装置 - Google Patents
半導体装置および電子装置 Download PDFInfo
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- JP7134077B2 JP7134077B2 JP2018219901A JP2018219901A JP7134077B2 JP 7134077 B2 JP7134077 B2 JP 7134077B2 JP 2018219901 A JP2018219901 A JP 2018219901A JP 2018219901 A JP2018219901 A JP 2018219901A JP 7134077 B2 JP7134077 B2 JP 7134077B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、本実施の形態の半導体装置PKG1の概要構成について、図1~図4を用いて説明する。図1は本実施の形態の半導体装置の斜視図、図2は、図1に示す半導体装置の上面図である。また、図3は、図1に示す半導体装置の下面図である。また、図4は図1のA-A線に沿った断面図である。なお、図示は省略するが、端子(端子2PD、ランド2LD、外部端子30)の数は、図1~図4に示す態様以外にも種々の変形例が適用できる。
次に、図4に示す半導体チップが備える回路構成例について説明する。図5は、図4に示す半導体チップが有する回路構成例を模式的に示す説明図である。また、図6は、図1に示す半導体チップの表面(電極配置面)の平面図である。図6は平面図であるが、複数の電極1PDv、複数の電極1PDg、および複数の電極1PDsのそれぞれを識別するため、ドットパターンやハッチングを付している。図6において、円形で示される複数の電極1PDのうち、電極1PDsは、白抜きで示され、電極1PDvは、ドットパターンで示され、電極1PDgはハッチングで示される。
次に、図4に示す配線基板20が有する各配線層における配線レイアウトについて図面を用いて詳細に説明する。図7は、図2に示す配線基板の上面において、半導体チップおよびアンダフィル樹脂を取り除いた状態を示す平面図である。図8は、図7に示す配線基板において、最上層の絶縁膜を取り除いた第1層目の配線層のレイアウトの例を示す平面図である。図7および図8では、図7に示すチップ搭載領域と重なっている領域を拡大して示している。図9は、図7に示す配線基板において、第2層目の配線層のレイアウトの例を示す平面図である。図10は、図9に示す配線層の中央部分を拡大した拡大平面図である。図11は、図7に示す配線基板において、第3層目の配線層のレイアウトの例を示す平面図である。図12は、図4に示す配線基板において、第4層目の配線層のレイアウトの例を示す平面図である。図13は、図4に示す配線基板において、第5層目の配線層のレイアウトの例を示す平面図である。図14は、図4に示す配線基板において、第6層目の配線層のレイアウトの例を示す平面図である。図7~図14のそれぞれは平面図であるが、信号伝送経路と、電源電位の供給経路と、基準電位の供給経路と、をそれぞれ識別するため、図6と同様の模様を付している。すなわち、図7~図10において、信号伝送経路は白抜きで示され、電源電位の供給経路は、ドットパターンで示され、基準電位の供給経路はハッチングで示される。なお、既に説明した図3では、領域2R1およびその周辺にのみ、図6から図14と同様のルールに則ってドットパターンまたはハッチングを付している。
次に、半導体装置PKG1の端子レイアウトの詳細について説明する。図15は、図4に示す配線基板の反り変形のモデルを示す断面図である。図16は、図3に示す配線基板の中央部周辺の拡大平面図である。半導体装置PKG1のように、配線基板20上に半導体チップ10が搭載された半導体パッケージの場合、配線基板20の線膨張係数と半導体チップ10の線膨張係数の違いに起因して、配線基板20に反り変形が生じやすい。半導体装置PKG1の製造工程には、例えば、半導体チップ10を配線基板20上に搭載するダイボンディング工程、アンダフィル樹脂40(図4参照)を熱硬化させるキュア工程、および外部端子30をランド2LD(図4参照)に接合するボールマウント工程など、種々の加熱プロセスが存在する。また、半導体装置PKG1が完成した後、後述する図20に示す実装基板50に搭載する際にも、外部端子30を実装基板50の端子(図20に示す上面端子51)と接合するために、加熱処理が実施される。このため、図15に例示するように、配線基板20に反り変形が生じることを前提として、反り変形が生じた場合の対策を施すことが重要である。
次に、上記した領域2R1における領域2R3と領域2R4との面積割合についての検討結果について説明する。今回の検討では、以下の2つの条件を満たす範囲内で、図16に示す領域2R1(または領域2R1および領域2R5)に配置可能な外部端子30の最大数に対して、何個の外部端子30を減らすことができるかを検討した。上記した条件の一つ目は、領域2R4に配置される複数の電源端子30vの数は、領域2R4に配置される複数の基準端子30gの数より多いという条件である。二つ目は、複数の電源端子30vのそれぞれと隣り合って配置される複数の外部端子30には、一つ以上の電源端子30vが含まれるという条件である。なお、以下では、今回検討した多数の配列パターンのうち、領域2R1の面積に対する領域2R3の面積の割合が最も大きくなる場合、言い換えれば、外部端子30を配置可能な最大数に対して外部端子30を減らせる割合が最も大きくなる場合についての配列パターンを例示的に示して説明する。図17から図19のそれぞれは、図16に示す配線基板の変形例を示す拡大平面図である。
次に、図1~図19を用いて説明した半導体装置を実装基板に実装して得られる電子装置の構成例について説明する。図20は、図4に示す半導体装置を実装基板に搭載した電子装置の断面図である。図21は、図20に示す実装基板の上面の拡大平面図である。図21では、図16に示す配線基板20の領域2R1および領域2R5と対向する領域を示している。図22は、図20に示す実装基板の下面の拡大平面図である。図23は、図22のコンデンサが搭載された領域周辺の拡大平面図である。
図24は、図5に対する変形例である半導体装置の回路構成例を模式的に示す説明図である。図25は、図24に示す半導体装置の配線基板の上面における端子レイアウトの構成例を示す平面図である。図25では、図7と同様のルールにより、複数の端子2PDにドットパターンやハッチングを付している。また、図25では、複数の端子2PDv2のそれぞれには、複数の端子2PDv1より濃いドットパターンを付している。図5に示す半導体装置PKG1の場合、半導体チップ10に供給される電源電位VDが一種類である場合について説明した。半導体チップ10に複数種類の電源電位が供給されても良い。例えば、図24に示す半導体装置PKG2の場合、半導体チップ10の入出力回路11には、コア回路12に供給される電源電位VD1とは異なる電源電位VD2が供給される。
図26は、図15に対する変形例を示す断面図である。図26に示す半導体装置PKG3は、配線基板20上にカバー部材(リッド)CV1が配置されている点で、図15に示す半導体装置PKG1と相違する。カバー部材CV1は、例えば金属製の部材であって、配線基板20の上面20tの周縁部および半導体チップ10の裏面10bに接着固定されている。半導体チップ10の裏面10bとカバー部材CV1との間には、金属粒子など、高い放熱性を示す多数の放熱粒子を含む接着材(放熱接着材)60が配置される。放熱性の高い接着材60を介して半導体チップ10と金属製のカバー部材CV1とを接着することで、半導体装置PKG3は、放熱特性を向上させることができる。
図27は、図15に示す半導体装置に対する他の変形例を示す断面図である。図28は、図27に示す配線基板において、第1層目の配線層のレイアウトの例を示す平面図である。図29は、図27に示す配線基板において、最下層の配線層のレイアウトの例を示す平面図である。なお、半導体装置PKG4の配線基板は、図28に示す第1層目の配線層WL1と、図29に示す第2層目の配線層WL2とから成る2層構造である。また、図27では、配線基板20の第1層目の配線層および第2層目の配線層を覆う絶縁膜の図示を省略している。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
2b,2Cb 下面
2Ca,2t 上面
2CR 絶縁層(コア層、コア材、コア絶縁層)
2e,2e1,2e2 絶縁膜
2LD,2LDg,2LDs,2LDv ランド(端子、外部端子、電極、外部電極)
2PD,2PDg,2PDs,2PDv,2PDv1,2PDv2 端子(端子部、パッド、半導体チップ接続用端子)
2Pg1,2Pg2,2Pv,2Pv1,2Pv2,2Pv3,5Pg,5Pv 導体パターン
2PL 導体プレーン
2R1,2R2,2R3,2R3,2R4,2R5,5R1,5R2,5R3,5R4,5R6,5R7 領域
2s 側面
2TW,2TWg,2TWs,2TWv,5TW,5Twg,5TWs,5TWv スルーホール配線(層間導電路)
2v,2vg,2vs,2vv ビア配線(ビア、層間導電路)
2VLg,2VLv ビアランド(導体パターン)
2w,2ws 配線
10,10A 半導体チップ
10b 裏面(主面、下面)
10r チップ搭載領域
10s 側面
10t 表面(主面、上面)
11 入出力回路
12 コア回路
20,20A,20B,20C 配線基板
20b 下面(面、主面、被実装面)20s 側面
20t 上面(面、主面、チップ搭載面)
30 外部端子(半田ボール、半田材、端子、外部端子、電極、外部電極)
30g 基準端子
30r1,30r2,30r5 端子
30v 電源端子
40 アンダフィル樹脂(絶縁性樹脂)
50 実装基板(配線基板)
50b 下面
50t 上面
51 上面端子(端子)
51g,52g 基準端子
51r1,51r2 端子
51v,52v 電源端子
52 下面端子(端子)
53,53g,53v 配線
54,54g,54v 端子
60 接着材(放熱接着材)
61 接着材
65 ワイヤ
CC1,CC2,CC3 コンデンサ(チップコンデンサ)
CE1,CE2,CE3,CE4,CE5 電極
CSL 長辺
CSS 短辺
CV1 カバー部材(リッド)
EDV1 電子装置
MR 封止体
P51 中心間距離
PKG1,PKG2,PKG3,PKG4 半導体装置(半導体パッケージ)
SB 突起電極
SIG 電気信号
Ti チタン
VD,VD1,VD2 電源電位
VG 基準電位
WL1,WL2,WL3,WL4,WL5,WL6 配線層
Claims (13)
- 第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記配線基板の前記第1上面上に搭載された半導体チップと、
を含み、
前記配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第3領域の面積は、前記第1領域の面積に対して56%以下であり、
前記第4領域に配置される前記複数の第1電源端子の数は、前記第4領域に配置される前記複数の基準端子の数より多い、半導体装置。 - 請求項1において、
前記複数の第1電源端子のそれぞれと隣り合って配置される複数の端子には、一つ以上の基準端子が含まれる、半導体装置。 - 請求項2において、
前記複数の第1電源端子のそれぞれと隣り合って配置される複数の端子には、一つ以上の第1電源端子が含まれる、半導体装置。 - 請求項2において、
前記第2領域は、前記第4領域の周囲を囲む第5領域を含み、
前記第5領域には、前記複数の第2端子に含まれる複数の第5領域端子が、前記第4領域の周囲を囲むように一列で配置され、
前記複数の第5領域端子は、前記複数の第1電源端子および前記複数の基準端子を含む、半導体装置。 - 第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記配線基板の前記第1上面上に搭載された半導体チップと、
を含み、
前記配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第3領域の面積は、前記第1領域の面積に対して56%以下であり、
前記複数の第1領域端子の最大配置数は、36個以上、かつ、169個以下であり、
前記第3領域の面積は、前記第1領域の面積に対して25%以下である、半導体装置。 - 請求項5において、
前記第2領域は、前記第4領域の周囲を囲む第5領域を含み、
前記第5領域には、前記複数の第2端子に含まれる複数の第5領域端子が、前記第4領域の周囲を囲むように一列で配置され、
前記複数の第5領域端子は、前記複数の基準端子を含み、かつ、前記複数の第1電源端子を含まない、半導体装置。 - 第1配線基板、および前記第1配線基板に搭載された半導体チップを備える半導体パッケージと、
前記半導体パッケージが搭載される第2配線基板と、
を有し、
前記半導体パッケージは、
第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する前記第1配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記第1配線基板の前記第1上面上に搭載された前記半導体チップと、
を含み、
前記第2配線基板は、前記半導体パッケージが搭載される第2上面、前記第2上面に形成され、前記第1配線基板の前記複数の第2端子のそれぞれと電気的に接続される複数の第3端子、および前記第2上面の反対側の第2下面を有し、
前記第1配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第2配線基板は、前記第2上面および前記第2下面の一方から他方までを貫通するように設けられた複数のスルーホール配線を有し、
前記複数のスルーホール配線には、前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続される第1電源スルーホール配線と、前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続される基準スルーホール配線と、を含み、
前記第2配線基板の前記第2下面は、前記第1配線基板の前記第3領域と重なる第6領域を有し、
前記第6領域には第1電極および第2電極を有する第1コンデンサが搭載され、
前記第1電極は、前記第1電源スルーホール配線を介して前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続され、
前記第2電極は、前記基準スルーホール配線を介して前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続され、
前記第1コンデンサは、前記第2配線基板の前記第2下面からの平面視において、前記第1コンデンサは第1短辺および第1長辺を有し、
前記第1短辺の長さは、前記第2上面に配置される前記複数の第3端子のうち、互いに隣り合って配置される第3端子の中心間距離より長い、電子装置。 - 第1配線基板、および前記第1配線基板に搭載された半導体チップを備える半導体パッケージと、
前記半導体パッケージが搭載される第2配線基板と、
を有し、
前記半導体パッケージは、
第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する前記第1配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記第1配線基板の前記第1上面上に搭載された前記半導体チップと、
を含み、
前記第2配線基板は、前記半導体パッケージが搭載される第2上面、前記第2上面に形成され、前記第1配線基板の前記複数の第2端子のそれぞれと電気的に接続される複数の第3端子、および前記第2上面の反対側の第2下面を有し、
前記第1配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第2配線基板は、前記第2上面および前記第2下面の一方から他方までを貫通するように設けられた複数のスルーホール配線を有し、
前記複数のスルーホール配線には、前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続される第1電源スルーホール配線と、前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続される基準スルーホール配線と、を含み、
前記第2配線基板の前記第2下面は、前記第1配線基板の前記第3領域と重なる第6領域を有し、
前記第6領域には第1電極および第2電極を有する第1コンデンサが搭載され、
前記第1電極は、前記第1電源スルーホール配線を介して前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続され、
前記第2電極は、前記基準スルーホール配線を介して前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続され、
前記第2配線基板の前記第2下面は、前記第1配線基板の前記第4領域と重なる第7領域を有し、
前記第7領域には、第2コンデンサが搭載され、
前記第2配線基板の前記第2下面からの平面視において、前記第1コンデンサの面積は、前記第2コンデンサの面積より大きい、電子装置。 - 第1配線基板、および前記第1配線基板に搭載された半導体チップを備える半導体パッケージと、
前記半導体パッケージが搭載される第2配線基板と、
を有し、
前記半導体パッケージは、
第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する前記第1配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記第1配線基板の前記第1上面上に搭載された前記半導体チップと、
を含み、
前記第2配線基板は、前記半導体パッケージが搭載される第2上面、前記第2上面に形成され、前記第1配線基板の前記複数の第2端子のそれぞれと電気的に接続される複数の第3端子、および前記第2上面の反対側の第2下面を有し、
前記第1配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第2配線基板は、前記第2上面および前記第2下面の一方から他方までを貫通するように設けられた複数のスルーホール配線を有し、
前記複数のスルーホール配線には、前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続される第1電源スルーホール配線と、前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続される基準スルーホール配線と、を含み、
前記第2配線基板の前記第2下面は、前記第1配線基板の前記第3領域と重なる第6領域を有し、
前記第6領域には第1電極および第2電極を有する第1コンデンサが搭載され、
前記第1電極は、前記第1電源スルーホール配線を介して前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続され、
前記第2電極は、前記基準スルーホール配線を介して前記第1配線基板の前記複数の基準端子のいずれかと電気的に接続され、
前記第1コンデンサは、前記第1電極、前記第2電極の他、前記第1電源スルーホール配線を介して前記第1配線基板の前記複数の第1電源端子のいずれかと電気的に接続される第3電極を有する、電子装置。 - 第1配線基板、および前記第1配線基板に搭載された半導体チップを備える半導体パッケージと、
前記半導体パッケージが搭載される第2配線基板と、
を有し、
前記半導体パッケージは、
第1上面、前記第1上面に形成された複数の第1端子、前記第1上面の反対側の第1下面、および前記第1下面に形成され、前記複数の第1端子のそれぞれと電気的に接続された複数の第2端子を有する前記第1配線基板と、
第1表面、前記第1表面に形成された複数の第1電極パッド、および前記第1表面の反対側の第1裏面を有し、前記第1配線基板の前記第1上面上に搭載された前記半導体チップと、
を含み、
前記第2配線基板は、前記半導体パッケージが搭載される第2上面、前記第2上面に形成され、前記第1配線基板の前記複数の第2端子のそれぞれと電気的に接続される複数の第3端子、および前記第2上面の反対側の第2下面を有し、
前記第1配線基板の前記第1下面は、前記第1上面に搭載された前記半導体チップと重なる第1領域と、前記第1領域を囲み、かつ、前記半導体チップと重ならない第2領域と、を含み、
前記第1領域は、前記複数の第2端子が配置されない第3領域と、前記第3領域を囲み、かつ、前記複数の第2端子が配置される第4領域と、を含み、
前記複数の第2端子は、前記第1領域の前記第4領域に配置される複数の第1領域端子と、前記第2領域に配置される複数の第2領域端子と、を含み、
前記複数の第1領域端子は、前記半導体チップの回路に第1電源電位を供給する複数の第1電源端子、および前記半導体チップの回路に基準電位を供給する複数の基準端子、を含み、
前記第4領域に配置される前記複数の第1電源端子の数は、前記第4領域に配置される前記複数の基準端子の数より多い、電子装置。 - 請求項10において、
前記複数の第1電源端子のそれぞれと隣り合って配置される複数の端子には、一つ以上の基準端子が含まれる、電子装置。 - 請求項11において、
前記複数の第1電源端子のそれぞれと隣り合って配置される複数の端子には、一つ以上の第1電源端子が含まれる、電子装置。 - 請求項12において、
前記第2領域は、前記第4領域の周囲を囲む第5領域を含み、
前記第5領域には、前記複数の第2端子に含まれる複数の第5領域端子が、前記第4領域の周囲を囲むように一列で配置され、
前記複数の第5領域端子は、前記複数の第1電源端子および前記複数の基準端子を含む、電子装置。
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