JP7097952B2 - 高バンド・ギャップ材料を含むストリング・ドライバを備えたデバイス及びシステム、並びに形成の方法 - Google Patents
高バンド・ギャップ材料を含むストリング・ドライバを備えたデバイス及びシステム、並びに形成の方法 Download PDFInfo
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- JP7097952B2 JP7097952B2 JP2020510085A JP2020510085A JP7097952B2 JP 7097952 B2 JP7097952 B2 JP 7097952B2 JP 2020510085 A JP2020510085 A JP 2020510085A JP 2020510085 A JP2020510085 A JP 2020510085A JP 7097952 B2 JP7097952 B2 JP 7097952B2
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Description
本願は、その開示の全体が参照により本明細書に組み込まれる2017年8月29日出願の米国仮特許出願第62/551,353号の35U.S.C.§119(e)の下での利益を主張する。本願はまた、「DEVICES AND SYSTEMS WITH STRING DRIVERS INCLUDING HIGH BAND GAP MATERIAL AND METHODS OF FORMATION」に関して2018年8月23日に出願された米国特許出願第16/110,217号に対する優先権を主張する。この出願は、前述した米国仮特許出願の正式な変換である。
Claims (19)
- ストリング・ドライバを備えたデバイスであって、前記ストリング・ドライバは、
電極の対の間に垂直方向に延在する少なくとも1つのピラーであって、前記少なくとも1つのピラーは、
ドレイン領域とソース領域との間のチャネル領域と、
前記少なくとも1つのピラーの中央部分内の誘電性材料であって、前記チャネル領域は、前記誘電性材料を横方向に取り囲む、前記誘電性材料と
を備え、前記チャネル領域、前記ドレイン領域、又は前記ソース領域のうちの少なくとも1つは、高バンド・ギャップ材料を備えた、
前記少なくとも1つのピラーと、
前記高バンド・ギャップ材料に隣接し、前記高バンド・ギャップ材料から離間されたゲート領域であって、前記電極の対の各電極は、前記高バンド・ギャップ材料の一部分により横方向に取り囲まれた垂直方向に延在する部分を備えた、前記ゲート領域と
を備えた、デバイス。 - 前記高バンド・ギャップ材料は、酸化亜鉛、インジウム・ガリウム亜鉛酸化物、インジウム亜鉛酸化物、炭化ケイ素、酸化スズ、及びガリウム砒素から成る群から選択された、請求項1に記載のデバイス。
- 前記ドレイン領域及び前記ソース領域はおのおの、0.20マイクロメートル未満(0.20μm未満)のオフセット領域によって、前記チャネル領域から離間された、請求項1に記載のデバイス。
- ストリング・ドライバを備えたデバイスであって、前記ストリング・ドライバは、
ドレイン領域とソース領域との間のチャネル領域であって、前記ドレイン領域及び前記ソース領域は、高バンド・ギャップ材料を備え、前記チャネル領域は、低バンド・ギャップ材料を備えた、前記チャネル領域と、
前記高バンド・ギャップ材料に隣接し、前記高バンド・ギャップ材料から離間されたゲート領域と
を備えた、デバイス。 - 前記低バンド・ギャップ材料は、ゲルマニウム(Ge)、シリコン・ゲルマニウム(SiGe)、及びインジウム・ガリウム砒素(InGaAs)から成る群から選択された、請求項4に記載のデバイス。
- ストリング・ドライバを備えたデバイスであって、前記ストリング・ドライバは、
ドレイン領域とソース領域との間のチャネル領域であって、前記チャネル領域は、高バンド・ギャップ材料と、別の高バンド・ギャップ材料とを備えた、前記チャネル領域と、
前記高バンド・ギャップ材料に隣接し、前記高バンド・ギャップ材料から離間されたゲート領域と
を備えた、デバイス。 - 電荷ストレージ・デバイスのアレイと、
電荷ストレージ・デバイスの前記アレイと動作可能に通信するアクセス・ラインとをさらに備え、
前記ストリング・ドライバは、前記アクセス・ラインのうちの少なくとも1つのアクセス・ラインと動作可能に通信し、
前記ドレイン領域及び前記ソース領域は、前記高バンド・ギャップ材料を備え、
前記チャネル領域は、前記高バンド・ギャップ材料又は低バンド・ギャップ材料を備え、
前記チャネル領域は、前記ドレイン領域と前記ソース領域との間に延在する、請求項1に記載のデバイス。 - ストリング・ドライバを備えたデバイスであって、前記ストリング・ドライバは、
ドレイン領域とソース領域との間の複数のチャネル領域であって、高バンド・ギャップ材料を備えた前記複数のチャネル領域と、
前記高バンド・ギャップ材料に隣接し、前記高バンド・ギャップ材料から離間されたゲート領域と
を備えた、デバイス。 - 前記ソース領域は、少なくとも1つのドーパントでドープされた前記高バンド・ギャップ材料を備え、
前記ドレイン領域は、前記少なくとも1つのドーパントでドープされた前記高バンド・ギャップ材料を備え、
前記少なくとも1つのドーパントは、アルミニウム(Al)及びシリコン(Si)から成る群から選択された、請求項1から3及び7のいずれか一項に記載のデバイス。 - 前記チャネル領域は、前記ソース領域と前記ドレイン領域との間に横方向に配置された、請求項4に記載のデバイス。
- デバイスのストリング・ドライバを形成する方法であって、
高バンド・ギャップ材料を形成することと、
前記高バンド・ギャップ材料の領域の間の低バンド・ギャップ材料、又は
前記高バンド・ギャップ材料に沿った別の高バンド・ギャップ材料
のいずれかを形成することと、
前記高バンド・ギャップ材料に隣接して、誘電性材料を形成することと、
前記誘電性材料に隣接して、導電性材料の領域を形成することとを備え、前記導電性材料の前記領域は、少なくとも前記誘電性材料によって、前記高バンド・ギャップ材料から離間された、方法。 - 前記高バンド・ギャップ材料を形成する前に、別の誘電性材料を形成することをさらに備え、
前記高バンド・ギャップ材料を形成することは、前記別の誘電性材料に隣接して、前記高バンド・ギャップ材料を形成することを備えた、請求項11に記載の方法。 - 前記高バンド・ギャップ材料のドープされていない部分及び前記別の高バンド・ギャップ材料のドープされていない部分、又は、前記低バンド・ギャップ材料のドープされていない部分によって、ドープされた高バンド・ギャップ材料の少なくとも1つのソース領域から離間された、ドープされた高バンド・ギャップ材料の少なくとも1つのドレイン領域を形成するために、前記高バンド・ギャップ材料の一部分にドーピングすることをさらに備えた、請求項11に記載の方法。
- 前記高バンド・ギャップ材料を形成する前に、
別の導電性材料を形成することと、
前記別の導電性材料に少なくとも1つのドーパントをドーピングすることをさらに備え、
前記方法は、前記高バンド・ギャップ材料の上に前記別の高バンド・ギャップ材料を形成することを備え、
前記高バンド・ギャップ材料を形成すること、及び前記別の高バンド・ギャップ材料を形成することは、前記少なくとも1つのドーパントでドープされた前記別の導電性材料と物理的に接触する前記高バンド・ギャップ材料及び前記別の高バンド・ギャップ材料を形成することを備え、
前記高バンド・ギャップ材料の前記一部分にドーピングすることは、
前記高バンド・ギャップ材料の少なくとも下部部分及び前記別の高バンド・ギャップ材料の少なくとも下部部分を熱に曝して、前記少なくとも1つのドーパントを、前記別の導電性材料から、前記高バンド・ギャップ材料の前記下部部分に、及び前記別の高バンド・ギャップ材料の前記下部部分に拡散させることと、
追加の量の前記少なくとも1つのドーパントを、前記高バンド・ギャップ材料の上部部分に、及び前記別の高バンド・ギャップ材料の上部部分に注入することとを備えた、請求項13に記載の方法。 - 前記高バンド・ギャップ材料の前記一部分にドーピングすることは、前記高バンド・ギャップ材料の前記一部分に少なくとも1つのドーパントを注入することを備え、前記一部分は、前記低バンド・ギャップ材料のドープされていない部分に、横方向に隣接した、請求項13に記載の方法。
- 前記方法は、前記高バンド・ギャップ材料の上に前記別の高バンド・ギャップ材料を形成することを備え、
前記導電性材料の前記領域を形成することは、前記誘電性材料を形成すること、前記高バンド・ギャップ材料を形成すること、及び前記別の高バンド・ギャップ材料を形成することに先行し、
前記誘電性材料を形成することは、
前記導電性材料を貫通して開口部を形成することと、
前記開口部に露出された前記導電性材料に隣接して、前記誘電性材料を形成することとを備え、
前記高バンド・ギャップ材料を形成することは、前記誘電性材料に隣接して、前記高バンド・ギャップ材料を形成することを備えた、請求項11に記載の方法。 - 前記方法は、前記高バンド・ギャップ材料に沿って、前記別の高バンド・ギャップ材料を形成することを備え、
前記誘電性材料を形成することは、前記高バンド・ギャップ材料及び前記別の高バンド・ギャップ材料を形成することに先行し、
前記導電性材料を形成することは、前記誘電性材料を形成することに先行し、
前記誘電性材料は、前記導電性材料を、前記高バンド・ギャップ材料から離間させる、請求項11に記載の方法。 - 前記方法は、前記高バンド・ギャップ材料の前記領域の間に前記低バンド・ギャップ材料を形成することを備え、
前記誘電性材料を形成することは、前記高バンド・ギャップ材料及び前記低バンド・ギャップ材料を形成することに後続し、
前記導電性材料の前記領域を形成することは、前記誘電性材料を形成することに後続する、請求項11に記載の方法。 - 前記高バンド・ギャップ材料を形成することは、前記高バンド・ギャップ材料を、400℃未満の温度で、堆積させることを備えた、請求項11から18のいずれか一項に記載の方法。
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