CN110265484B - 薄膜晶体管、阵列基板、显示装置 - Google Patents

薄膜晶体管、阵列基板、显示装置 Download PDF

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CN110265484B
CN110265484B CN201910563193.4A CN201910563193A CN110265484B CN 110265484 B CN110265484 B CN 110265484B CN 201910563193 A CN201910563193 A CN 201910563193A CN 110265484 B CN110265484 B CN 110265484B
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layer
electrode
substrate
thin film
film transistor
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CN110265484A (zh
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强朝辉
强力
罗超
张惠勤
黄睿
王治
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BOE Technology Group Co Ltd
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Priority to PCT/CN2020/095047 priority patent/WO2020259273A1/zh
Priority to US17/413,221 priority patent/US11996413B2/en
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Abstract

本发明提供一种薄膜晶体管、阵列基板、显示装置，涉及显示技术领域，用于解决薄膜晶体管漏电流高的问题。薄膜晶体管，包括衬底，还包括：第一电极，设置在衬底上；有源层，包括层叠设置的第一掺杂层、半导体层以及第二掺杂层；第一掺杂层设置在第一电极远离衬底一侧，且与第一电极电连接；第一掺杂层和第二掺杂层互为电子掺杂层和空穴掺杂层；栅绝缘层，设置在有源层远离衬底一侧；栅绝缘层上设置有露出有源层的第一过孔；栅极设置在栅绝缘层远离衬底一侧；栅极与有源层并排设置，栅极朝向有源层的第一侧面所在平面为参考平面，半导体层在参考平面上的正投影位于栅极在参考平面上的正投影内；第二电极，设置在栅极远离衬底一侧，与有源层电连接。

Description

薄膜晶体管、阵列基板、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板、显示装置。
背景技术
近年来，随着各种显示技术，如LCD(Liquid Crystal Display，液晶显示器)显示、OLED(Organic Light-Emitting Diode，有机发光二极管)显示、柔性显示等的不断发展，采用大尺寸、高分辨率显示面板的产品层出不穷。传统的硅基薄膜晶体管因迁移率低已不能满足实际需求。
低温多晶硅薄膜晶体管因其可实现玻璃基板上的驱动集成，可实现更高的分辨率、更快的响应速度、更高的稳定性的显示装置，而引起广泛的关注。
然而，现有技术中的低温多晶硅薄膜晶体管因其具有较大的漏电流，导致显示装置的功耗明显增加，这成为本领域技术人员急需解决的技术问题。
发明内容
本发明的实施例提供一种薄膜晶体管、阵列基板、显示装置，用于解决薄膜晶体管漏电流高的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种薄膜晶体管，包括衬底，还包括：第一电极，设置在所述衬底上；有源层，包括沿远离所述衬底的方向依次层叠设置的第一掺杂层、半导体层以及第二掺杂层；所述第一掺杂层设置在所述第一电极远离所述衬底一侧，且与所述第一电极电连接；所述第一掺杂层和所述第二掺杂层互为电子掺杂层和空穴掺杂层；栅绝缘层，设置在所述有源层远离所述衬底一侧；所述栅绝缘层上设置有第一过孔，所述第一过孔露出所述有源层；栅极，设置在所述栅绝缘层远离所述衬底一侧；所述栅极与所述有源层并排设置，所述栅极朝向所述有源层的第一侧面所在平面为参考平面，所述半导体层在所述参考平面上的正投影位于所述栅极在所述参考平面上的正投影内；第二电极，设置在所述栅极远离所述衬底一侧，所述第二电极通过所述第一过孔与所述有源层电连接。
可选的，所述栅极在所述衬底上的正投影的轮廓围成有凹陷区域；所述有源层在所述衬底上的正投影落入所述凹陷区域。
可选的，所述栅极的所述第一侧面与所述栅绝缘层接触。
可选的，所述薄膜晶体管还包括设置在所述第一电极与所述衬底之间的缓冲层；所述缓冲层上设置有凹槽，所述第一电极位于所述凹槽内。
可选的，缓冲层包括第一子层和第二子层，所述第二子层设置在所述第一子层远离所述衬底一侧；所述第二子层上设置有第二过孔，所述第一电极位于所述第二过孔内。
可选的，所述薄膜晶体管还包括设置在所述栅极与所述第二电极之间的层间绝缘层；所述层间绝缘层上设置有第三过孔，所述第三过孔与所述第一过孔导通。
第二方面，提供一种阵列基板，包括至少一个如第一方面任一项所述的薄膜晶体管。
可选的，所述阵列基板包括两个所述薄膜晶体管；两个所述薄膜晶体管的第一电极电连接，两个所述薄膜晶体管的第二电极电连接。
可选的，所述阵列基板包括两个所述薄膜晶体管；两个所述薄膜晶体管的栅极电连接。
第三方面，提供一种显示装置，包括第二方面任一项所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种显示装置的框架示意图；
图2为本申请实施例提供的一种显示屏的像素分布图；
图3a为本申请实施例提供的一种显示模组的结构示意图；
图3b为本申请实施例提供的另一种显示模组的结构示意图；
图3c为本申请实施例提供的一种阵列基板中像素电路的结构示意图；
图4a为本申请实施例提供的又一种显示模组的结构示意图；
图4b为本申请实施例提供的又一种显示模组的结构示意图；
图4c为本申请实施例提供的一种阵列基板中像素电路的结构示意图；
图5为本申请实施例提供的一种薄膜晶体管的结构示意图；
图6为本申请实施例提供的另一种薄膜晶体管的结构示意图；
图7为本申请实施例提供的又一种薄膜晶体管的结构示意图；
图8为本申请实施例提供的又一种薄膜晶体管的结构示意图；
图9为本申请实施例提供的又一种薄膜晶体管的结构示意图；
图10a为本申请实施例提供的一种薄膜晶体管的俯视示意图；
图10b为一种沿图10a中A-A′向的剖视示意图；
图11为本申请实施例提供的又一种薄膜晶体管的结构示意图；
图12为本申请实施例提供的又一种薄膜晶体管的结构示意图；
图13为本申请实施例提供的一种阵列基板的结构示意图；
图14a为本申请实施例提供的另一种薄膜晶体管的俯视示意图；
图14b为本申请实施例提供的又一种薄膜晶体管的俯视示意图；
图14c为一种沿图14a和图14b中B-B′向的剖视示意图；
图15为本申请实施例提供的一种显示装置的结构示意图。
附图标记：
01-显示装置；10-显示模组；101-显示屏；1010-子像素；1011-阵列基板；10111-像素电路；1012-对置基板；10121-彩色滤光层；1013-液晶层；1014-封框胶；1016-发光器件；1017-封装层；102-第一偏振层；103-第二偏振层；104-背光模组；105-第三偏振层；11-中框；12-壳体；13-盖板；20-衬底；21-第一电极；22-有源层；221-第一掺杂层；222-半导体层；223-第二掺杂层；23-栅绝缘层；231-第一过孔；24-栅极；241-参考平面；241-第一侧面；25-第二电极；26-层间绝缘层；261-第三过孔；27-平坦层；271-第四过孔；28-缓冲层；281-凹槽；282-第一子层；283-第二子层；284-第二过孔；30-像素界定层；40-支撑柱。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书以及权利要求书中使用的术语“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“左”、“右”、“上”以及“下”等方位术语是相对于附图中的显示装置示意放置的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据显示装置所放置的方位的变化而相应地发生变化。
本申请实施例提供一种如图1所示的显示装置01。该显示装置01包括例如手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等。本申请实施例对上述显示装置01的具体形式不做特殊限制。以下为了方便说明，是以显示装置01为手机为例进行的说明。
上述显示装置01，如图1所示，主要包括显示模组10、中框11、壳体12以及盖板13，显示模组10和中框11设置于壳体12内。
其中，上述中框11位于显示模组10和壳体12之间，中框11远离显示模组10的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(Camera)、天线等内部元件。
上述显示装置01还包括设置于PCB上的中央处理器(Central Processing Unit，CPU)。
盖板13位于显示模组10远离中框11一侧，盖板13例如可以是盖板玻璃(coverglass，CG)，该盖板玻璃可以具有一定的韧性。
显示模组10具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组10的背面靠近中框11，盖板13设置在显示模组10的出光侧。
上述显示模组10，包括显示屏(display panel，DP)。
如图2所示，显示屏101包括多个像素(pixel)，每个像素包括多个子像素(subpixel)1010，该多个子像素1010包括第一颜色子像素、第二颜色子像素和第三颜色子像素。
示例的，第一颜色为红色，第二颜色为绿色，第三颜色为蓝色。
子像素1010围成的区域构成显示装置01的显示区A，位于显示区A***的区域作为显示装置01的周边区B。
图2中对显示区A和周边区B的划分仅为一种示意，不做任何限定。
在本申请的一些实施例中，如图3a所示，上述显示屏101可以为液晶显示(liquidcrystal display，LCD)屏。
在此情况下，该显示模组10还包括：靠近显示屏101出光侧的第一偏振层102，靠近显示屏101背面的第二偏振层103，用于向该液晶显示屏提供光源的背光模组(back lightunit，BLU)104。
如图3b所示，液晶显示屏包括阵列基板1011、对置基板1012、液晶层1013。液晶层1013设置于阵列基板1011和对置基板1012之间。阵列基板1011和对置基板1012通过封框胶1014对合在一起，从而将液晶层1013限定在阵列基板1011、对置基板1012以及封框胶1014围成的液晶盒内。
如图3c所示，阵列基板1011包括多个像素电路10111，每个子像素1010中设置有一像素电路10111，像素电路10111用于改变各个子像素1010中液晶分子的偏振光方向。
图3c中以像素电路10111包括薄膜晶体管M1为例进行示意，不做任何限定，但像素电路10111中必然包括至少一个薄膜晶体管。
像素电路10111中的L，是指由阵列基板1011、液晶层1013、对置基板1012围成的液晶盒中，位于与该像素电路10111对应的子像素1010中的部分。
其中，为了使得液晶显示屏能够实现彩色显示，该液晶显示屏如图3b所示，还包括彩色滤光层10121。该彩色滤光层10121可以设置于对置基板1012上，此时对置基板1012可以称为彩膜基板。彩色滤光层10121包括与每个位于每个子像素1010中的彩色滤光图案。
如图3a所示，液晶显示屏中的第一偏振层102可以为制作好的偏振片(polarizer)。在此情况下，可以将偏振片贴附于显示屏101的出光侧的表面上。
或者，如图3b所示，第一偏振层102可以为线栅偏振层(grid polarizer，GP)。示例的，在对置基板1012的制备过程中，可以采用溅射、纳米压印、光刻等方式将线栅偏振层集成在对置基板1012中。
构成线栅偏振层的材料可以为金属。示例的，构成线栅偏振层的材料包括但不限于铝(Al)、铜(Cu)、银(Ag)、金(Au)和铬(Cr)等。
此外，如图3a所示，第二偏振层103可以为制作好的偏光片。在此情况下，第二偏振层103设置在显示屏101背面的表面上。
或者，如图3b所示，第二偏振层103可以为在阵列基板1011的制作过程中，集成于阵列基板1011中的线栅偏振层。
包括液晶显示屏的显示装置01的显示原理为：背光模组104发出白光，经过第二偏振层103形成有特定偏振方向的白色偏振光，射入阵列基板1011，再通过液晶层1013以及对置基板1012上的彩色滤光层过滤形成红绿蓝三基色的偏振光。
当该偏振光的偏振方向与第一偏振层102的偏振方向垂直时，偏振光不能穿过第一偏振层102，此时无光线出射。
当该偏振光的偏振方向与第一偏振层102的偏振方向平行时，偏振光可以穿过第一偏振层102，此时出射光的光强最强。
由于液晶层1013中的液晶分子对偏振光有旋光特性，特定的分子排布方向可使该偏振光的偏振方向发生改变，通过阵列基板1011上的像素电路10111改变各个子像素1010中液晶分子的偏振光方向，可以控制偏振光与第一偏振层102的夹角，从而控制各个子像素1010中从第一偏振层102出射的多少，以显示不同的灰阶图像。
因此，包括液晶显示屏的显示装置01在第一偏振层102、第二偏振层103、液晶层1013三者的共同作用下，控制背光模组104发出的光从第一偏振层102出射的量，以完成显示。
或者，在本申请的另一些实施例中，如图4a所示，上述显示屏101为有机发光二极管(organic light emitting diode，OLED)显示屏。在此情况下，该显示模组10还包括：第三偏振层105。OLED显示屏能够实现自发光，因此，显示模组10中无需设置上述BLU。
如图4b所示，OLED显示屏包括：阵列基板1011、设置在阵列基板1011上的多个发光器件1016、设置在发光器件1016远离阵列基板1011一侧的封装层1017。
如图4a所示，第三偏振层105可以为偏光片。在此情况下，第三偏振层105设置在显示屏101出光侧的表面上。
或者，如图4b所示，第三偏振层105可以为线栅偏振层，线栅偏振层集成于显示屏101中。在此情况下，为了确保线栅偏振层能够发挥改变光的偏振方向的作用，线栅偏振层设置在发光器件1016远离阵列基板1011一侧。
如图4c所示，阵列基板1011包括多个像素电路10111，每个子像素1010中设置有一像素电路10111。像素电路10111与该子像素1010中的发光器件1016电连接，用于向发光器件1016传输电信号。
如图4c所示的像素电路10111包括两个薄膜晶体管(M1和M2)，仅为一种示意，不做任何限定，但每个像素电路10111中必然包括至少一个薄膜晶体管。
需要说明的是，上述OLED显示屏可以为柔性显示屏。也可以为硬质显示屏。
包括OLED显示屏的显示装置01的发光原理为：发光器件1016发出的自然光经过第三偏振层105，形成单一偏振方向的显示光，以实现清晰的显示。通过控制像素电路10111向发光器件1016输入的电信号的大小，可控制各个发光器件1016的发光亮度。
以下，为了便于说明，以显示装置01包括的显示屏101为OLED显示屏为例进行说明。
由上述可知，OLED显示屏的阵列基板1011包括多个像素电路10111，像素电路10111与该子像素1010中的发光器件1016电连接，用于向发光器件1016传输电信号。
每个像素电路10111包括至少一个薄膜晶体管，薄膜晶体管的性能决定了像素电路10111的性能，从而决定了发光器件1016的发光亮度。
基于此，如图5所示，本申请实施例提供一种薄膜晶体管M，薄膜晶体管M包括衬底20。
其中，衬底20可以由柔性材料制成，也可以由硬质材料制成。衬底20的表面可以为平面，也可以为曲面。
薄膜晶体管M还包括：第一电极21，设置在衬底20上。
第一电极21例如可以是通过磁控溅射工艺形成导电薄膜，并采用光工艺和干刻工艺完成图案化。第一电极21的厚度例如可以是
Figure BDA0002108818170000081
例如为
Figure BDA0002108818170000082
Figure BDA0002108818170000083
在一些实施例中，为了保证第一电极21的性能，第一电极21包括层叠设置的钛(Ti)金属层、铝(Al)金属层和钛金属层。
其中，钛金属层的厚度例如为
Figure BDA0002108818170000084
铝金属层的厚度例如为
Figure BDA0002108818170000091
可以理解的是，如图5所示，第一电极21可以直接设置在衬底20的表面上，也就是说第一电极21与衬底20之间不设置其他膜层。
在一些实施例中，为了提高第一电极21与衬底20连接的稳定性，如图6所示，薄膜晶体管M还包括：设置在第一电极21与衬底20之间的缓冲层28。
缓冲层28例如可以通过等离子体增强化学的气相沉积法(Plasma EnhancedChemical Vapor Deposition，简称PECVD)形成。缓冲层28的材料例如可以是树脂材料，例如为SiNx(氮化硅)或SiO2(氧化硅)等。
由于缓冲层28和衬底20的材料均为树脂材料，因此，缓冲层28和衬底20的连接效果比第一电极21和衬底20的连接效果好。
从外，通过在衬底20上设置缓冲层28，可以避免其他杂质进入到薄膜晶体管M的内部。
在此基础上，如图7所示，缓冲层28上设置有凹槽281，第一电极21位于凹槽281内。
为了便于制备，在一些实施例中，凹槽281在衬底20上的正投影与第一电极21在衬底20上的正投影重合。
通过在缓冲层28上设置凹槽281，并使第一电极21位于凹槽281内，相比图6所示的第一电极21位于缓冲层28的表面，可以降低薄膜晶体管M的厚度。
在此基础上，为了便于凹槽281的形成，如图8所示，缓冲层28包括第一子层282和第二子层283，第二子层283设置在第一子层282远离衬底20一侧。
第二子层283上设置有第二过孔284，第一电极21位于第二过孔284内。
也就是说，第二子层283上的第二过孔284作为缓冲层28上的凹槽281。
第一子层282例如可以为一层厚度为30-80nm的氮化硅层，第二子层283例如可以为一层厚度为300-800nm的氧化硅层。
这样一来，可以先形成一整层第一子层282，然后形成第二子层283后，对第二子层283进行图案化，在第二子层283上形成第二过孔284。采用现有的制备工艺即可制备的到缓冲层28。可以避免在缓冲层28上形成凹槽281时，因工艺问题影响凹槽281的形状，从而影响薄膜晶体管M的性能的问题。
如图8所示，薄膜晶体管M还包括：有源层22。
有源层22包括沿远离衬底20的方向依次层叠设置的第一掺杂层221、半导体层222以及第二掺杂层223。
第一掺杂层221设置在第一电极21远离衬底20一侧，且与第一电极21电连接。
如图8所示，第一掺杂层221可以直接设置在第一电极21层远离衬底20的表面上。第一掺杂层221和第一电极21之间也可以设置有绝缘层，第一掺杂层221通过绝缘层上的过孔与第一电极21电连接。
第一掺杂层221和第二掺杂层223互为电子掺杂层(也称为N型掺杂层)和空穴掺杂层(也称为P型掺杂层)。
电子掺杂层可以是在半导体薄膜中掺杂磷、氮等，以使电子掺杂层以电子为多数载流子，空穴掺杂层可以是在半导体薄膜中掺杂硼、铝等，以使空穴掺杂层以空穴为多数载流子。
也就是说，第一掺杂层221为电子掺杂层，则第二掺杂层223为空穴掺杂层。反之，第一掺杂层221为空穴掺杂层，则第二掺杂层223为电子掺杂层。
第一掺杂层221例如可以通过金属有机化合物化学气相沉淀(Metal-organicChemical Vapor Deposition，简称MOCVD)工艺制备得到半导体薄膜，随后通过光刻和干法刻蚀工艺完成图案化，最后进行空穴或电子的掺杂。
半导体薄膜例如是厚度为10-100nm的砷化镓(GaAs)薄膜。
半导体层222例如可以通过MOCVD工艺制备得到半导体薄膜，随后通过光刻和干法刻蚀工艺完成图案化。
半导体薄膜例如是厚度为10-100nm的砷化镓(GaAs)薄膜。
第二掺杂层223例如可以通过MOCVD工艺制备得到半导体薄膜，随后通过光刻和干法刻蚀工艺完成图案化，最后进行空穴或电子的掺杂。
半导体薄膜例如是厚度为10-100nm的砷化镓(GaAs)薄膜。
如图8所示，薄膜晶体管M还包括：栅绝缘层23。
栅绝缘层23设置在有源层22远离衬底20一侧；栅绝缘层23上设置有第一过孔231，第一过孔231露出有源层22。
栅绝缘层23例如可以通过PECVD制备形成绝缘薄膜，并通过光刻和干法刻蚀等工艺，对绝缘薄膜图案化，形成第一过孔231。
可以理解的是，形成栅绝缘层23上的第一过孔231，可以是在形成栅极24之后再形成，也可以是在形成栅极24之前形成。具体顺序与栅极24的制备工艺有关，保证栅极24与有源层22不电连接即可。
栅绝缘层23的厚度例如可以为400-600nm，例如为150nm、500nm、550nm。栅绝缘层23的材料例如可以为SiNx或SiO2等。
其中，图8中所示的第一过孔231的形状仅为一种示意，第一过孔231在衬底20上的正投影位于有源层22的第二掺杂层223在衬底20上的正投影内(包括重合)即可。
如图8所示，薄膜晶体管M还包括：栅极24。
栅极24设置在栅绝缘层23远离衬底20一侧且栅极24与有源层22并排设置。
如图9所示，栅极24朝向有源层22的第一侧面241所在平面为参考平面241，半导体层222在参考平面241上的正投影位于栅极24在参考平面241上的正投影内。
也就是说，将衬底20近似看作一个平面，栅极24靠近衬底20的表面到衬底20的距离h1，小于等于半导体层222靠近衬底20的表面到衬底20的距离h2，并且，栅极24远离衬底20的表面到衬底20的距离h3，大于等于半导体层222远离衬底20的表面到衬底20的距离h4。
在一些实施例中，为了提高栅极24向有源层22传出信号的效果和速率，以提高薄膜晶体管M开关的灵敏性。如图9所示，栅极24的朝向有源层22的第一侧面241与栅绝缘层23接触。
在一些实施例中，如图10a所示，栅极24在衬底20上的正投影的轮廓围成有凹陷区域；有源层22在衬底20上的正投影落入凹陷区域。
示例的，栅极24在衬底20上的正投影的轮廓类似与C型，围绕有源层22设置。
基于此，如图10b所示，有源层22的多侧设置有栅极24，栅极24的面积增大。
相当于薄膜晶体管M采用多栅极24驱动，可降低栅极24的驱动电压，节省功耗。
如图10b所示，薄膜晶体管M还包括：第二电极25。
第二电极25设置在栅极24远离衬底20一侧，第二电极25通过第一过孔231与有源层22电连接。
其实，也就是第二电极25通过第一过孔231与有源层22中的第二掺杂层223电连接。
第二电极25例如可以通过磁控溅射工艺形成导电薄膜，并采用光工艺和干刻工艺完成图案化。
第二电极25的材料例如可以为Mo(钼)。第二电极25的厚度可以为200-300nm。例如为250nm。
第一电极21为源极，第二电极25为漏极。或者，第一电极21为漏极，第二电极25为源极。
在一些实施例中，如图11所示，薄膜晶体管M还包括设置在栅极24与第二电极25之间的层间绝缘层26。
层间绝缘层26上设置有第三过孔261，第三过孔261与第一过孔231导通。
也就是说，第二电极25通过层间绝缘层26上的第三过孔261和栅绝缘层23上的第一过孔231，与有源层22电连接。
层间绝缘层26，例如可以通过PECVD制备形成绝缘薄膜，并通过光刻和干法刻蚀等工艺，对绝缘薄膜图案化，形成第三过孔261。
层间绝缘层26的厚度例如可以为100-300nm，例如为150nm、200nm、250nm。栅绝缘层23的材料例如可以为SiNx或SiO2等。
若在栅极24和第二电极25之间不设置层间绝缘层26，为了避免栅极24和第二电极25电连接，对第二电极25的制备工艺和制备精度要求较高，增加制备成本。因此，在栅极24和第二电极25之间设置层间绝缘层26后，只要确保第二电极25与有源层22电连接即可，不用担心第二电极25与栅极24之间会电连接，可降低对制备工艺的要求。
本申请实施例提供的薄膜晶体管M，通过将薄膜晶体管M的结构设计为半导体层222位于中间，第一掺杂层221和第二掺杂层223分别位于半导体层222两侧，且第一掺杂层221和第二掺杂层223互为电子掺杂层和空穴掺杂层的结构。这样一来，在栅极24传输信号时，可改变半导体层222的能带，使得半导体层222的能带与空穴掺杂层的能带相同，进而使得半导体层222的能带与电子掺杂层的能带发生极度的弯曲，最终发生隧穿，使得薄膜晶体管M导通，形成隧穿电流。
而由于在栅极24不传输信号，也就是薄膜晶体管M处于关闭状态的情况下，第一电极21和半导体层222之间的势垒比较大，第二电极25和半导体层222之间的势垒也比较大。这就使得，第一电极21和第二电极25之间很难有载流子通过，从而使得薄膜晶体管M的漏电流较小，可降低薄膜晶体管M的功耗。
这样一来，阵列基板1011上的像素电路10111包括上述薄膜晶体管M时，可降低像素电路10111的功耗，从而降低显示装置01的功耗。
此外，由于薄膜晶体管M的沟道越小，漏电流越大。而本申请实施例提供的薄膜晶体管M，在与现有技术中提供的薄膜晶体管的沟道大小相同时，漏电流较小，因此可适用于亚微米沟道设置的薄膜晶体管。
基于此，为了便于位于薄膜晶体管M上方的发光器件1016的制备。在一些实施例中，如图12所示，薄膜晶体管M还包括设置在第二电极25远离衬底20一侧的平坦层27。
平坦层27上设置有第四过孔271，第四过孔271露出第二电极25。
在此基础上，考虑到采用隧穿电流的薄膜晶体管M，的开态电流较小，在形成隧穿电流时需要向栅极24传输较大的电压信号，才能使半导体层222的能带与电子掺杂层的能带发生隧穿。
如图13所示，阵列基板1011上设置有两个上述薄膜晶体管M。
两个薄膜晶体管M的第一电极21电连接，两个薄膜晶体管M的第二电极25电连接。
两个薄膜晶体管M的第一电极21电连接，如图13所示，可以是两个薄膜晶体管M的第一电极21共用，即为一体结构。也可以是两个薄膜晶体管M的第一电极21通过导电结构电连接。
同理，两个薄膜晶体管M的第二电极25电连接，如图13所示，可以是两个薄膜晶体管M的第二电极25共用，即为一体结构。也可以是两个薄膜晶体管M的第二电极25通过导电结构电连接。
两个薄膜晶体管M的第一电极21和第二电极25分别电连接，相当于两个薄膜晶体管M并联，这样一来，两个并联的薄膜晶体管M同时接收信号并传输，相当于对信号进行了翻倍，可提高薄膜晶体管M的开态电流，满足显示装置01的显示要求。
在此基础上，在一些实施例中，如图14a所示，两个薄膜晶体管M的栅极24电连接。
可以理解的是，两个薄膜晶体管M的栅极24电连接，那么，两个薄膜晶体管M的栅极24可以为一体结构。
如图14a中所示的两个薄膜晶体管M的栅极24的结构仅为一种示意，两个薄膜晶体管M的栅极24的结构也可以如图14b所示。当然也可以为其他的结构。
这样一来，两个薄膜晶体管M只需要一根信号线即可完成对两个薄膜晶体管M的信号传输，可减少信号线的排布。
在一些实施例中，如图14c所示，两个薄膜晶体管M的栅极24中的部分共用。
共用部分可以同时向连个薄膜晶体管M传输电信号，进一步降低薄膜晶体管M的栅极24驱动电压。
基于此，在像素电路10111中的驱动晶体管为上述的薄膜晶体管M时，如图15所示，上述发光器件1016通过平坦层27上的第四过孔271与薄膜晶体管M的第二电极25电连接。
如图15所示，发光器件1016包括沿远离衬底20的方向依次层叠设置的阳极(anode，简称a)、空穴注入层(hole inject layer，简称HIL)、空穴传输层(hole transportlayer，简称HTL)、电致发光层(emitting material layer，简称EML)、电子传输层(electron transport layer，简称ETL)、电子注入层(electron inject layer，简称EIL)以及阴极(cathode，简称c)。
发光器件1016中的阳极a通过平坦层27上的第四过孔271与薄膜晶体管M的第二电极25电连接。
可以理解的是，如图15所示，上述显示装置01中，相邻发光器件1016之间设置有用于防止相邻发光器件1016发出的光发生混光的像素界定层30。
为了避免发光器件1016和薄膜晶体管M受压损伤，显示装置01还包括位于发光器件1016远离衬底20一侧的支撑柱40。随后采用封装层1017完成封装。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (7)

1.一种阵列基板，其特征在于，包括至少两个薄膜晶体管；
所述薄膜晶体管包括：
衬底；
第一电极，设置在所述衬底上；
有源层，包括沿远离所述衬底的方向依次层叠设置的第一掺杂层、半导体层以及第二掺杂层；所述第一掺杂层设置在所述第一电极远离所述衬底一侧，且与所述第一电极电连接；所述第一掺杂层和所述第二掺杂层互为电子掺杂层和空穴掺杂层；
栅绝缘层，设置在所述有源层远离所述衬底一侧；所述栅绝缘层上设置有第一过孔，所述第一过孔露出所述有源层；
栅极，设置在所述栅绝缘层远离所述衬底一侧；所述栅极与所述有源层并排设置，且所述栅极三面环绕所述有源层；所述栅极朝向所述有源层的第一侧面所在平面为参考平面，所述半导体层在所述参考平面上的正投影位于所述栅极在所述参考平面上的正投影内；
第二电极，设置在所述栅极远离所述衬底一侧，所述第二电极通过所述第一过孔与所述有源层电连接；
至少两个所述薄膜晶体管的第一电极电连接，至少两个所述薄膜晶体管的第二电极电连接；至少两个所述薄膜晶体管的栅极位于至少两个所述薄膜晶体管的有源层之间的部分栅极共用。
2.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管的栅极在所述衬底上的正投影的轮廓围成有凹陷区域；
所述有源层在所述衬底上的正投影落入所述凹陷区域。
3.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管的栅极的所述第一侧面与所述栅绝缘层接触。
4.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管还包括设置在所述第一电极与所述衬底之间的缓冲层；
所述缓冲层上设置有凹槽，所述第一电极位于所述凹槽内。
5.根据权利要求4所述的阵列基板，其特征在于，所述薄膜晶体管的缓冲层包括第一子层和第二子层，所述第二子层设置在所述第一子层远离所述衬底一侧；
所述第二子层上设置有第二过孔，所述第一电极位于所述第二过孔内。
6.根据权利要求1-5任一项所述的阵列基板，其特征在于，所述薄膜晶体管还包括设置在所述栅极与所述第二电极之间的层间绝缘层；
所述层间绝缘层上设置有第三过孔，所述第三过孔与所述第一过孔导通。
7.一种显示装置，其特征在于，包括权利要求1-6任一项所述的阵列基板。
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