JP7097742B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP7097742B2 JP7097742B2 JP2018088248A JP2018088248A JP7097742B2 JP 7097742 B2 JP7097742 B2 JP 7097742B2 JP 2018088248 A JP2018088248 A JP 2018088248A JP 2018088248 A JP2018088248 A JP 2018088248A JP 7097742 B2 JP7097742 B2 JP 7097742B2
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- 239000004065 semiconductor Substances 0.000 title claims description 262
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000000523 sample Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 11
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 97
- 238000012360 testing method Methods 0.000 description 91
- 238000012216 screening Methods 0.000 description 70
- 239000011229 interlayer Substances 0.000 description 53
- 230000004048 modification Effects 0.000 description 30
- 238000012986 modification Methods 0.000 description 30
- 238000010586 diagram Methods 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 230000003071 parasitic effect Effects 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 19
- 239000000758 substrate Substances 0.000 description 19
- 238000009413 insulation Methods 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- 230000008859 change Effects 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 239000000356 contaminant Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 101710149695 Clampless protein 1 Proteins 0.000 description 2
- 101001089083 Daboia russelii C-type lectin domain-containing protein 2 Proteins 0.000 description 2
- 102100023504 Polyribonucleotide 5'-hydroxyl-kinase Clp1 Human genes 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 102100032912 CD44 antigen Human genes 0.000 description 1
- 241000711969 Chandipura virus Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000015951 Cytophagic histiocytic panniculitis Diseases 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 108010069264 keratinocyte CD44 Proteins 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L27/0203—Particular design considerations for integrated circuits
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
- H02M1/348—Passive dissipative snubbers
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Description
現実のパワートランジスタにおいては、寄生インダクタンスの影響によって、ターンオン時やターンオフ時にサージ電圧が発生する。このようなサージ電圧がパワートランジスタの耐圧を超えると、パワートランジスタは破壊されてしまう。さらには、サージ電圧が発生すると、サージ電圧に起因する電磁ノイズが発生して、周辺機器への電磁ノイズに起因する誤動作に代表される悪影響が懸念される。このことから、ターンオン時やターンオフ時に発生するサージ電圧を抑制する必要がある。
例えば、上述したスナバ容量は、パワーMOSFETが形成された半導体チップの外部に設けられることが一般的である。ところが、パワーMOSFETが形成された半導体チップの外部にスナバ容量を設ける場合、パワーMOSFETとスナバ容量とを接続する配線の長さが長くなることから、寄生インダクタンスが増加することになる。そして、逆起電力(サージ電圧)の大きさは、寄生インダクタンスの大きさに比例することから、寄生インダクタンスが大きくなると、寄生インダクタンスに基づく逆起電力(サージ電圧)が大きくなる。したがって、パワーMOSFETが形成された半導体チップの外部にスナバ容量を設ける構成(外付け)では、スナバ容量によって、電流変化率を緩和できる一方で、寄生インダクタンスの大きさを低減することが難しいことから、効果的に大きな逆起電力(サージ電圧)の発生を抑制することが困難となる。
ここで、パワーMOSFETが形成された半導体チップの内部にスナバ容量を設ける構成を採用すると、スナバ容量の信頼性を確保する観点から、パワーMOSFETを含む半導体装置を製造する工程において、スナバ容量の信頼性試験(スクリーニング試験)が必要となる。なぜなら、パワーMOSFETが形成された半導体チップの内部にスナバ容量が含まれる半導体装置では、スナバ容量が不良になると、パワーMOSFETが良品であっても、パワーMOSFETとスナバ容量とを含む半導体装置としては不良品と判断する必要があるからである。つまり、パワーMOSFETとスナバ容量とを含む半導体装置においては、パワーMOSFETに対する信頼性試験を実施する必要があるだけでなく、スナバ容量に対する信頼性試験も実施する必要性が生じるのである。
このように、効果的に大きな逆起電力(サージ電圧)の発生を抑制する観点から、パワーMOSFETが形成された半導体チップの内部にスナバ容量を設ける構成を採用すると、スナバ容量の信頼性を確保するために、パワーMOSFETとスナバ容量とを含む半導体装置の製造工程において、スナバ容量の信頼性を担保するスクリーニング試験を実施する必要性が生じる。この点に関し、本発明者は、パワーMOSFETと混載されるスナバ容量のスクリーニング試験を実施するにあたって工夫を施す必要性を新規に見出した。すなわち、本発明者は、パワーMOSFETが形成された半導体チップの内部にスナバ容量を設ける構成を採用すると、新たな改善の余地が顕在化することを見出した。そこで、以下では、まず、新たに顕在化する改善の余地について説明する。
スナバ容量の容量絶縁膜となるため、スナバ容量の容量絶縁膜は、プラズマCVD法で形成された酸化シリコン膜から構成されることになる。そして、スナバ容量の容量絶縁膜には、サージ電圧が印加されても絶縁破壊されない絶縁耐性が要求される。ところが、プラズマCVD法で形成された酸化シリコン膜においては、部分的に汚染物質が混入する可能性があり、この汚染物質に起因して、容量絶縁膜の絶縁耐性が低下するおそれがある。つまり、図2に示すデバイス構造のようにして、パワーMOSFETとスナバ容量とを混載する場合、スナバ容量を構成する容量絶縁膜の絶縁耐性が良好であるかをテストする必要がある。なぜなら、スナバ容量を構成する容量絶縁膜の絶縁不良が生じると、スナバ容量が不良となるため、このような製品は、スクリーニング試験を施すことによって除外する必要があるからである。そこで、上述したように、パワーMOSFETとスナバ容量とを含む半導体装置においては、パワーMOSFETに対する信頼性試験を実施する必要があるだけでなく、スナバ容量に対する信頼性試験も実施する必要性が生じる。
まず、パワーMOSFETとスナバ容量とを混載する半導体装置においては、スナバ容量のスクリーニング試験を実施する際には工夫を施さないと、スクリーニング試験を実施できなくなることについて説明する。
次に、パワートランジスタの一種であるIGBT(Insulated Gate Bipolar Transistor)とスナバ容量とを混載する半導体装置においても、スナバ容量のスクリーニング試験を実施する際には工夫を施さないと、スクリーニング試験を実施できなくなることについて説明する。図5は、IGBT200とスナバ容量SCとを混載する半導体装置においても、工夫を施さないと、スクリーニング試験を実施できなくなることを説明する図である。図5において、IGBT200のコレクタCとソースEとの間にスナバ容量SCが並列接続されている。このとき、スナバ容量SCを構成する容量絶縁膜の絶縁耐性が良好であるかをテストするスクリーニング試験においては、スナバ容量SCの容量電極間にパルス電圧を印加する。そして、スナバ容量SCの容量電極間にパルス電圧を印加した状態において、容量電極間に挟まれた容量絶縁膜に流れるパルス電流を測定することにより、スナバ容量SCを構成する容量絶縁膜の絶縁耐性が良好であるかがテストされる。
そこで、本実施の形態では、パワーMOSFETやIGBTに代表されるパワートランジスタと並列接続されたスナバ容量を備える半導体装置において、スナバ容量を構成する容量絶縁膜の絶縁耐性をテストするスクリーニング試験を実施するための工夫を施している。以下では、この工夫を施した実施の形態における基本思想について説明する。
次に、本実施の形態における半導体装置の構成について説明する。図9は、本実施の形態における半導体装置SA1の外観構成を示す図である。図9において、本実施の形態における半導体装置SA1は、平面形状が略矩形形状の封止体MRを有し、この封止体MRからは、ゲートリードGLと、リードLと、ソースリードSLとが突出している。
本実施の形態における半導体装置SA1は、上記のように構成されており、以下に、その製造方法について、図面を参照しながら説明することにする。
続いて、本実施の形態における特徴点について説明する。本実施の形態における第1特徴点は、例えば、図10に示すように、パワーMOSFETとスナバ容量とが形成された半導体チップCHPの表面に、スナバ容量パッドSNPとドレインパッドDPとが形成され、かつ、スナバ容量パッドSNPとドレインパッドDPとが接続部材(ワイヤW)で接続されている点にある。これにより、スナバ容量を構成する容量絶縁膜の絶縁耐性をテストするスクリーニング試験の段階においては、スナバ容量パッドSNPとドレインパッドDPとを接続部材(ワイヤW)で接続せずに、パワーMOSFETのドレインパッドDPとスナバ容量のスナバ容量パッドSNPとを電気的に接続しないように構成することができる(図13~図15参照)。一方、スクリーニング試験を実施した後の段階においては、スナバ容量パッドSNPとドレインパッドDPとを接続部材(ワイヤW)で接続することにより、ドレインパッドDPとスナバ容量パッドSNPとを電気的に接続することができる(図22参照)。
図24は、実施の形態の変形例1における半導体装置SA1の模式的な構成を示す図である。図24において、本変形例1では、ゲートパッドGPとスナバ容量パッドSNPとドレインパッドDPが、半導体チップCHPにチップ辺CS1に沿って配置されている。このように、スナバ容量パッドSNPとドレインパッドDPとをレイアウト配置することもできる。この場合においても、スナバ容量を構成する容量絶縁膜の絶縁耐性をテストする段階においては、パワーMOSFETのドレインパッドDPとスナバ容量のスナバ容量パッドSNPとを電気的に接続しない一方、スクリーニング試験を実施した後の段階においては、ドレインパッドDPとスナバ容量パッドSNPとを電気的に接続するという基本思想を実現することができる。
図25は、実施の形態の変形例2における半導体装置SA1の模式的な構成を示す図である。図25において、本変形例2では、ゲートパッドGPは、チップ辺CS1とチップ辺CS3の交点に近接配置されている。言い換えれば、ゲートパッドGPは、チップ辺CS1とチップ辺CS3との交差する角部に配置されている。そして、ゲートパッドGPとスナバ容量パッドSNPは、チップ辺CS1に沿って配置され、かつ、ゲートパッドGPとドレインパッドDPは、チップ辺CS3に沿って配置されている。また、逆に、ゲートパッドGPとスナバ容量パッドSNPとを、チップ辺CS3に沿って配置し、かつ、ゲートパッドGPとドレインパッドDPとを、チップ辺CS1に沿って配置することもできる。このように、スナバ容量パッドSNPとドレインパッドDPとをレイアウト配置することもできる。この場合においても、スナバ容量を構成する容量絶縁膜の絶縁耐性をテストする段階においては、パワーMOSFETのドレインパッドDPとスナバ容量のスナバ容量パッドSNPとを電気的に接続しない一方、スクリーニング試験を実施した後の段階においては、ドレインパッドDPとスナバ容量パッドSNPとを電気的に接続するという基本思想を実現することができる。
図26は、実施の形態の変形例3における半導体装置SA1の模式的な構成を示す図である。図26において、本変形例3では、ゲートパッドGPとスナバ容量パッドSNPとドレインパッドDPは、チップ辺CS3に沿って配置されている。このように、スナバ容量パッドSNPとドレインパッドDPとをレイアウト配置することもできる。この場合においても、スナバ容量を構成する容量絶縁膜の絶縁耐性をテストする段階においては、パワーMOSFETのドレインパッドDPとスナバ容量のスナバ容量パッドSNPとを電気的に接続しない一方、スクリーニング試験を実施した後の段階においては、ドレインパッドDPとスナバ容量パッドSNPとを電気的に接続するという基本思想を実現することができる。
図27は、実施の形態の変形例4における半導体装置SA1の模式的な構成を示す図である。図27において、本変形例4では、半導体チップCHPの表面に形成されているソースパッドSPとソースリードSL(ソースリードSLのポスト部)とが、例えば、銅からなるクリップCLP1で接続されている。同様に、本変形例4では、スナバ容量パッドSNPとドレインパッドDPとが、クリップCLP2で接続されている。
図28は、実施の形態の変形例5における半導体装置SA1の模式的な構成を示す図である。図28において、本変形例5では、スナバ容量パッドSNPとドレインパッドDPとが、導電性接着材ADHで接続されている。
図29は、実施の形態の変形例6における半導体装置SA1の模式的な構成を示す図である。例えば、図29に示すように、半導体チップCHPは、半田SDを介して、チップ搭載部TAB上に搭載されることから、チップ搭載部TABは、半導体基板と電気的に接続されることになる。つまり、チップ搭載部TABもパワーMOSFETのドレインと同電位となる。このことから、例えば、図29において、本変形例6では、パワーMOSFETとスナバ容量とを並列接続するために、半導体チップCHPの表面に形成されているスナバ容量パッドSNPと、半導体チップCHPが搭載されていないチップ搭載部TAB上の一部分とをワイヤWで接続している。この場合、半導体チップCHPの表面にドレインパッド(DP)を設ける必要はなくなる。
図30は、実施の形態の変形例7における半導体装置SA1の模式的な構成を示す図である。図30において、本変形例7では、半導体チップCHPの中央部にスナバ容量パッドSNPとドレインパッドDPが設けられており、このスナバ容量パッドSNPとドレインパッドDPとがワイヤWで接続されている。
実施の形態では、パワートランジスタの一例として、パワーMOSFETを例に挙げて説明したが、実施の形態における技術的思想は、これに限らず、例えば、パワートランジスタとして、IGBTを採用する場合にも適用することができる。このとき、パワーMOSFETを含む半導体装置SA1と、IGBTを含む半導体装置との対応関係としては、以下のようになる。すなわち、ソースリードSLは、エミッタリードとなり、かつ、ソース領域は、エミッタ領域となり、かつ、ドレイン領域は、コレクタ領域となり、かつ、ドレインパッドDPは、コレクタパッドとなる。
200 IGBT
ADH 導電性接着材
CE2 容量電極
CHP 半導体チップ
CLP1 クリップ
CLP2 クリップ
CS1 チップ辺
CS2 チップ辺
CS3 チップ辺
CS4 チップ辺
DP ドレインパッド
GE ゲート電極
GL ゲートリード
GP ゲートパッド
GW ゲートワイヤ
L リード
SL ソースリード
SNP スナバ容量パッド
SR ソース領域
SW ソースワイヤ
S1 辺
TAB チップ搭載部
W ワイヤ
Claims (17)
- 第1辺を有するチップ搭載部と、
前記チップ搭載部上に搭載された半導体チップと、
前記チップ搭載部から離間し、かつ、前記チップ搭載部の前記第1辺に沿って配置された複数のリードと、
を備える、半導体装置であって、
前記複数のリードは、
ゲートリードと、
第1リードと、
を含み、
前記半導体チップは、
パワートランジスタと、
前記パワートランジスタと並列接続されたスナバ容量と、
を有し、
前記パワートランジスタは、
前記ゲートリードと電気的に接続されたゲート電極と、
前記第1リードと電気的に接続された第1領域と、
前記チップ搭載部と電気的に接続された第2領域と、
を有し、
前記スナバ容量は、
前記第1領域と電気的に接続された第1容量電極と、
前記第1容量電極から離間し、かつ、前記第1容量電極と対向するように配置された第2容量電極と、
を有し、
前記半導体チップの表面には、前記スナバ容量の前記第2容量電極と電気的に接続されたスナバ容量パッドが形成されており、
前記半導体チップの表面には、前記チップ搭載部を経由することなく前記パワートランジスタの前記第2領域と電気的に接続された第2パッドが形成されており、
前記スナバ容量パッドと前記第2パッドとは、接続部材を介して互いに、かつ、電気的に接続されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記接続部材は、ワイヤである、半導体装置。 - 請求項1に記載の半導体装置において、
前記接続部材は、クリップである、半導体装置。 - 請求項1に記載の半導体装置において、
前記接続部材は、導電性接着材である、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップは、
前記チップ搭載部の前記第1辺に沿って配置された第1チップ辺と、
前記第1チップ辺の反対側に位置する第2チップ辺と、
前記第1チップ辺および前記第2チップ辺と交差する第3チップ辺と、
前記第1チップ辺および前記第2チップ辺と交差し、かつ、前記第3チップ辺の反対側に位置する第4チップ辺と、
を有する、半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの表面には、前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドが形成され、
前記ゲートパッドと前記スナバ容量パッドと前記第2パッドは、前記第1チップ辺に沿って配置されている、半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの表面には、前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドが形成され、
前記ゲートパッドと前記スナバ容量パッドと前記第2パッドは、前記第3チップ辺に沿って配置されている、半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの表面には、前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドが形成され、
前記ゲートパッドは、前記第1チップ辺と前記第3チップ辺の交点に近接配置され、
前記ゲートパッドと前記スナバ容量パッドは、前記第1チップ辺に沿って配置され、
前記ゲートパッドと前記第2パッドは、前記第3チップ辺に沿って配置されている、半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの表面には、前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドが形成され、
前記ゲートパッドは、前記第1チップ辺と前記第3チップ辺の交点に近接配置され、
前記ゲートパッドと前記スナバ容量パッドは、前記第3チップ辺に沿って配置され、
前記ゲートパッドと前記第2パッドは、前記第1チップ辺に沿って配置されている、半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの表面には、前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドが形成され、
前記ゲートパッドは、前記第1チップ辺と前記第3チップ辺の交点に近接配置され、
前記スナバ容量パッドは、前記第2チップ辺と前記第4チップ辺の交点に近接配置されている、半導体装置。 - 請求項2に記載の半導体装置において、
前記半導体チップの表面には、
前記パワートランジスタの前記第1領域と電気的に接続された第1パッドと、
前記パワートランジスタの前記ゲート電極と電気的に接続されたゲートパッドと、
が形成され、
前記第1パッドと前記第1リードとは、第1ワイヤで接続され、
前記ゲートパッドと前記ゲートリードとは、ゲートワイヤで接続され、
前記ゲートワイヤの径は、前記第1ワイヤの径よりも小さく、
前記ワイヤの径は、前記第1ワイヤの径よりも小さい、半導体装置。 - 請求項11に記載の半導体装置において、
前記ワイヤの径と前記ゲートワイヤの径とは、等しい、半導体装置。 - 請求項1に記載の半導体装置において、
前記パワートランジスタは、パワーMOSFETであり、
前記第1リードは、ソースリードであり、
前記第1領域は、ソース領域であり、
前記第2領域は、ドレイン領域であり、
前記第2パッドは、ドレインパッドである、半導体装置。 - 請求項1に記載の半導体装置において、
前記パワートランジスタは、IGBTであり、
前記第1リードは、エミッタリードであり、
前記第1領域は、エミッタ領域であり、
前記第2領域は、コレクタ領域であり、
前記第2パッドは、コレクタパッドである、半導体装置。 - (a)パワートランジスタと、前記パワートランジスタと電気的に接続されたスナバ容量とが形成されたチップ領域を備え、
前記パワートランジスタは、
第1領域と、
第2領域と、
前記第1領域と前記第2領域との間を流れる電流を制御するゲート電極と、
を有し、
前記スナバ容量は、
前記第1領域と電気的に接続された第1容量電極と、
前記第1容量電極から離間し、かつ、前記第1容量電極と対向するように配置された第2容量電極と、
を有し、
前記チップ領域の表面には、
前記スナバ容量の前記第2容量電極と電気的に接続されたスナバ容量パッドと、
前記第1領域と電気的に接続された第1パッドと、
前記第2領域と電気的に接続された第2パッドと、
前記ゲート電極と電気的に接続されたゲートパッドと、
が形成されている、半導体ウェハを用意する工程、
(b)前記スナバ容量パッドにプローブ針を接触させる工程、
(c)前記第1領域と前記スナバ容量パッドとの間に電圧を印加する工程、
(d)前記第1領域と前記スナバ容量パッドとの間に流れる電流を測定する工程、
(e)前記(d)工程で測定した前記電流に基づいて、前記スナバ容量の良否を判定する工程、
(f)前記(e)工程の後、前記半導体ウェハをダイシングすることにより、前記チップ領域を個片化して、半導体チップを取得する工程、
(g)第1辺を有するチップ搭載部と、前記チップ搭載部から離間し、かつ、前記チップ搭載部の前記第1辺に沿って配置された複数のリードと、を備え、
前記複数のリードは、
ゲートリードと、
第1リードと、
を含む、リードフレームを用意する工程、
(h)前記チップ搭載部上に前記半導体チップを搭載する工程、
(i)前記第1パッドと前記第1リードとを第1ワイヤで接続する工程、
(j)前記(i)工程の後、前記ゲートパッドと前記ゲートリードとをゲートワイヤで接続し、かつ、前記スナバ容量パッドと前記第2パッドとをワイヤで接続する工程、
を備える、半導体装置の製造方法。 - 請求項15に記載の半導体装置の製造方法において、
前記(j)工程では、同じワイヤボンディング装置を使用する、半導体装置の製造方法。 - 請求項15に記載の半導体装置の製造方法において、
前記(a)工程で用意される前記半導体ウェハの前記チップ領域に形成されている前記スナバ容量は、プラズマCVD法によって形成され、かつ、前記第1容量電極と前記第2容量電極との間に設けられた容量絶縁膜を有する、半導体装置の製造方法。
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