JP6978151B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Description
最初に、本発明の実施形態の内容を列記して説明する。一実施形態に係る半導体装置の製造方法は、窒化物半導体層上にソース電極、ドレイン電極、及びゲート電極を形成する工程と、ゲート電極を覆う部分を含む絶縁膜を窒化物半導体層上に形成する工程と、絶縁膜に開口を形成して窒化物半導体層を露出させる工程と、リフトオフ法を用いて絶縁膜上にフィールドプレートを形成する工程と、を含む。開口は、ソース電極の長手方向の端部外方に形成される。フィールドプレートを形成する工程では、フィールドプレートの配線は開口を介して窒化物半導体層に接触した状態で形成される。
本発明の実施形態に係る半導体装置の製造方法および半導体装置の具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。以下の説明では、図面の説明において同一の要素には同一の符号を付し、重複する説明を省略する。
Claims (7)
- 窒化物半導体層に、第1の活性領域と、前記第1の活性領域に対し不活性領域により互いに電気的に分離された第2の活性領域と、を形成する工程と、
前記第2の活性領域上にソース電極、ドレイン電極を形成するとともに、前記第2の活性領域を横切るように前記窒化物半導体層上にゲート電極を形成する工程と、
前記ゲート電極を覆う部分を含む絶縁膜を前記窒化物半導体層上に形成する工程と、
前記絶縁膜に開口を形成して前記窒化物半導体層を露出させる工程と、
リフトオフ法を用いて前記絶縁膜上にフィールドプレートを形成する工程と、
を含み、
前記開口は、前記第1の活性領域上に形成され、
前記フィールドプレートを形成する工程は、前記フィールドプレートに接続されるとともに前記開口を介して前記第1の活性領域に接触する配線を形成する工程を含み、
前記フィールドプレートの面積と前記配線の面積との総和に対する前記第1の活性領域の面積の割合は、0.3よりも大きい、半導体装置の製造方法。 - 前記割合は、0.5よりも大きく2.0よりも小さい、請求項1に記載の半導体装置の製造方法。
- 前記フィールドプレートを形成する工程では、前記リフトオフ法で用いたマスクを高圧洗浄によって除去する、請求項1又は請求項2に記載の半導体装置の製造方法。
- 前記高圧洗浄は、洗浄液を5MPa以上50MPa以下の圧力で吹き掛け、前記マスクを除去する工程である、請求項3に記載の半導体装置の製造方法。
- 第1の活性領域と、前記第1の活性領域に対し不活性領域により互いに電気的に分離された第2の活性領域と、を含む窒化物半導体層と、
前記第2の活性領域上に設けられたソース電極、ドレイン電極、及び前記第2の活性領域を横切るように前記窒化物半導体層上に設けられたゲート電極と、
前記窒化物半導体層上に設けられ、前記ゲート電極を覆う部分を含み、前記第1の活性領域上に開口を有する絶縁膜と、
前記絶縁膜上に設けられたフィールドプレートと、
前記フィールドプレートと接続されている配線と、
を備え、
前記配線は、前記開口を介して前記第1の活性領域に接触しており、
前記フィールドプレートの面積と前記配線の面積との総和に対する前記第1の活性領域の面積の割合は、0.3よりも大きい、半導体装置。 - 前記割合は、0.5よりも大きく2.0よりも小さい、請求項5に記載の半導体装置。
- 前記絶縁膜の前記ゲート電極を覆う部分の厚さが100nm以上500nm以下である、請求項5又は請求項6に記載の半導体装置。
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JP2017188461A JP6978151B2 (ja) | 2017-09-28 | 2017-09-28 | 半導体装置の製造方法および半導体装置 |
US16/144,727 US10833195B2 (en) | 2017-09-28 | 2018-09-27 | Semiconductor device and process of forming the same |
CN201811138593.2A CN109585543B (zh) | 2017-09-28 | 2018-09-28 | 半导体器件及形成该半导体器件的处理 |
TW107134296A TWI775953B (zh) | 2017-09-28 | 2018-09-28 | 半導體裝置及其形成方法 |
CN202210278490.6A CN114649412A (zh) | 2017-09-28 | 2018-09-28 | 半导体器件及形成该半导体器件的处理 |
US17/060,960 US11302817B2 (en) | 2017-09-28 | 2020-10-01 | Semiconductor device and process of forming the same |
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JP5649347B2 (ja) | 2010-07-20 | 2015-01-07 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
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