JP6787367B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6787367B2 JP6787367B2 JP2018117316A JP2018117316A JP6787367B2 JP 6787367 B2 JP6787367 B2 JP 6787367B2 JP 2018117316 A JP2018117316 A JP 2018117316A JP 2018117316 A JP2018117316 A JP 2018117316A JP 6787367 B2 JP6787367 B2 JP 6787367B2
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- 239000004065 semiconductor Substances 0.000 title claims description 93
- 239000010410 layer Substances 0.000 claims description 568
- 239000012535 impurity Substances 0.000 claims description 55
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 13
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 13
- 230000005684 electric field Effects 0.000 claims description 10
- 239000002344 surface layer Substances 0.000 claims description 8
- 108091006146 Channels Proteins 0.000 description 73
- 239000000758 substrate Substances 0.000 description 21
- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000036413 temperature sense Effects 0.000 description 1
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Description
なお、上記および特許請求の範囲における括弧内の符号は、特許請求の範囲に記載された用語と後述の実施形態に記載される当該用語を例示する具体物等との対応関係を示すものである。
第1実施形態について説明する。本実施形態の半導体装置は、図1に示されるように、セル領域1と、当該セル領域1を囲む外周領域2と、セル領域1と外周領域2との間の領域である中間領域3を有している。
第2実施形態について説明する。本実施形態は、第1実施形態に対してボディ層17の構造を変更したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
第3実施形態について説明する。本実施形態は、第1実施形態に対して、チャネル層14の構成を変更したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
第3実施形態の変形例について説明する。図11に示されるように、ボディ層17よりドリフト層13側のチャネル層14は、ボディ層17の底面のみと繋がるように形成されていてもよい。つまり、ゲート層16とボディ層17との間に位置するチャネル層14は、これらゲート層16およびボディ層17の深さと等しくされていてもよい。このような構成としても、上記第3実施形態と同様の効果を得ることができる。
第4実施形態について説明する。本実施形態は、第1実施形態に対してボディ層17の底面と繋がるようにN型のボディ層を形成したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
第5実施形態について説明する。本実施形態は、第1実施形態に対してボディ層17の幅を狭くしたものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
第6実施形態について説明する。本実施形態は、第1実施形態に対してシールド層を追加したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
13 ドリフト層
14 チャネル層
15 ソース層
16 ゲート層
17 ボディ層
19 ゲート配線
21 上部電極(第1電極)
22 下部電極(第2電極)
Claims (16)
- セル領域(1)を有し、前記セル領域に接合型FETが形成された半導体装置であって、
前記セル領域は、
第1導電型のドリフト層(13)と、
前記ドリフト層上に配置された第1導電型のチャネル層(14)と、
前記チャネル層の表層部に形成され、前記チャネル層よりも高不純物濃度とされた第1導電型のソース層(15)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のゲート層(16)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のボディ層(17)と、
前記ドリフト層を挟んで前記ソース層と反対側に配置されるドレイン層(11)と、
前記ゲート層と電気的に接続されるゲート配線(19)と、
前記ソース層および前記ボディ層と電気的に接続された第1電極(21)と、
前記ドレイン層と電気的に接続される第2電極(22)と、を備え、
前記ゲート層は、前記チャネル層のうちの前記ドリフト層側と反対側の表面から形成され、
前記セル領域の外側には、前記ボディ層が形成されており、
前記ボディ層の底部側では、前記ゲート層の底部側よりも電界強度が高くなる半導体装置。 - 前記ボディ層は、前記ゲート層よりも深くまで形成されている請求項1に記載の半導体装置。
- 前記ボディ層は、前記ゲート層の深さをYg、前記ボディ層の深さをYb、前記ゲート層の深さに対する前記ボディ層における前記ゲート層より深い部分の長さで示される相対突出量を(Yb−Yg)/Ygとすると、相対突出量が0.1〜0.73とされている請求項2に記載の半導体装置。
- 前記ゲート層の下方には、第2導電型とされ、前記ゲート層と離れつつ、前記ボディ層と接続されたシールド層(24)が形成されている請求項2または3に記載の半導体装置。
- 前記ゲート層および前記ボディ層は、一方向に沿って延設され、
前記シールド層は、前記一方向に沿って延設された主部(24a)と、前記主部と交差する方向に突出し、前記一方向に沿って周期的に形成された複数の突出部(24b)とを有し、前記複数の突出部が前記ボディ層と接続されている請求項4に記載の半導体装置。 - 前記ボディ層は、底部が先細り形状とされている請求項1ないし5のいずれか1つに記載の半導体装置。
- 前記ボディ層の底面は、前記ゲート層の底面が繋がる第1導電型の不純物領域(13、14)より高不純物濃度とされた第1導電型の不純物領域(14、23)と繋がっている請求項1ないし6のいずれか1つに記載の半導体装置。
- 前記チャネル層は、前記ドリフト層よりも高不純物濃度とされ、
前記ゲート層は、底面が前記ドリフト層と繋がっており、
前記ボディ層は、底面が前記チャネル層と繋がっている請求項7に記載の半導体装置。 - 前記チャネル層には、前記ボディ層の底面と繋がる状態で、前記チャネル層よりも高不純物濃度とされた第1導電型のチャネル層(23)が形成されている請求項7に記載の半導体装置。
- 前記ボディ層は、前記ゲート層よりも幅が狭くされている請求項1ないし9のいずれか1つに記載の半導体装置。
- 前記チャネル層は、前記ソース層と前記ゲート層の底面との間の長さをチャネル長さ(Lch)とすると、前記チャネル長さが1μm以上とされている請求項1ないし10のいずれか1つに記載の半導体装置。
- セル領域(1)を有し、前記セル領域に接合型FETが形成された半導体装置であって、
第1導電型のドリフト層(13)と、
前記ドリフト層上に配置された第1導電型のチャネル層(14)と、
前記チャネル層の表層部に形成され、前記チャネル層よりも高不純物濃度とされた第1導電型のソース層(15)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のゲート層(16)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のボディ層(17)と、
前記ドリフト層を挟んで前記ソース層と反対側に配置されるドレイン層(11)と、
前記ゲート層と電気的に接続されるゲート配線(19)と、
前記ソース層および前記ボディ層と電気的に接続された第1電極(21)と、
前記ドレイン層と電気的に接続される第2電極(22)と、を備え、
前記ゲート層は、前記チャネル層のうちの前記ドリフト層側と反対側の表面から形成され、
前記セル領域の外側には、前記ボディ層が形成されており、
前記ボディ層は、前記ゲート層と不純物濃度が等しくされていると共に同じ幅とされており、前記ゲート層よりも深くまで形成されている半導体装置。 - 接合型FETが形成された半導体装置であって、
第1導電型のドリフト層(13)と、
前記ドリフト層上に配置された第1導電型のチャネル層(14)と、
前記チャネル層の表層部に形成され、前記チャネル層よりも高不純物濃度とされた第1導電型のソース層(15)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のゲート層(16)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のボディ層(17)と、
前記ドリフト層を挟んで前記ソース層と反対側に配置されるドレイン層(11)と、
前記ゲート層と電気的に接続されるゲート配線(19)と、
前記ソース層および前記ボディ層と電気的に接続された第1電極(21)と、
前記ドレイン層と電気的に接続される第2電極(22)と、を備え、
前記ボディ層は、前記ゲート層と不純物濃度が等しくされていると共に同じ幅とされ、かつ深さが等しくされており、さらに底部が先細り形状とされている半導体装置。 - 接合型FETが形成された半導体装置であって、
第1導電型のドリフト層(13)と、
前記ドリフト層上に配置された第1導電型のチャネル層(14)と、
前記チャネル層の表層部に形成され、前記チャネル層よりも高不純物濃度とされた第1導電型のソース層(15)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のゲート層(16)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のボディ層(17)と、
前記ドリフト層を挟んで前記ソース層と反対側に配置されるドレイン層(11)と、
前記ゲート層と電気的に接続されるゲート配線(19)と、
前記ソース層および前記ボディ層と電気的に接続された第1電極(21)と、
前記ドレイン層と電気的に接続される第2電極(22)と、を備え、
前記ボディ層は、前記ゲート層と不純物濃度が等しくされていると共に同じ幅とされ、かつ深さが等しくされており、さらに底面が前記ゲート層の底面が繋がる第1導電型の不純物領域(13、14)より高不純物濃度とされた第1導電型の不純物領域(14、23)と繋がっている半導体装置。 - 接合型FETが形成された半導体装置であって、
第1導電型のドリフト層(13)と、
前記ドリフト層上に配置された第1導電型のチャネル層(14)と、
前記チャネル層の表層部に形成され、前記チャネル層よりも高不純物濃度とされた第1導電型のソース層(15)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のゲート層(16)と、
前記チャネル層に前記ソース層よりも深くまで形成された第2導電型のボディ層(17)と、
前記ドリフト層を挟んで前記ソース層と反対側に配置されるドレイン層(11)と、
前記ゲート層と電気的に接続されるゲート配線(19)と、
前記ソース層および前記ボディ層と電気的に接続された第1電極(21)と、
前記ドレイン層と電気的に接続される第2電極(22)と、を備え、
前記ボディ層は、前記ゲート層と不純物濃度が等しくされていると共に深さが等しくされており、前記ゲート層よりも幅が狭くされている半導体装置。 - 前記ドレイン層、前記ドリフト層、前記チャネル層、前記ソース層、前記ゲート層、および前記ボディ層は、炭化珪素で構成されている請求項1ないし15のいずれか1つに記載の半導体装置。
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