JP5864784B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 102
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000012535 impurity Substances 0.000 claims description 81
- 238000002513 implantation Methods 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 38
- 210000000746 body region Anatomy 0.000 claims description 30
- 230000001681 protective effect Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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Description
図1に示す半導体装置10は、主にSiCからなる半導体基板11、各種電極、絶縁膜、金属配線等によって構成されている。本実施例の半導体装置10は、縦型のMOSFETである。図1では、半導体基板11の表面側及び裏面側に備えられる絶縁膜、電極等の図示を省略している。
第2実施例について、第1実施例とは異なる点を中心に説明する。本実施例でも、半導体装置10の構成は第1実施例とほぼ同様である。本実施例では、半導体装置10の製造方法の一部が第1実施例とは異なる。第1実施例では、図4に示すように、トレンチ12の底部12aに第1の注入エネルギーでp型の不純物を注入する場合、トレンチ12の内側には保護膜(犠牲酸化膜等)が形成されていない。これに対し、本実施例では、図8に示すように、トレンチ12の底部12aに第1の注入エネルギーでp型の不純物を注入する際に、トレンチ12の内面に予め酸化膜80が形成されている点で第1実施例とは異なる。
第3実施例について、第1実施例とは異なる点を中心に説明する。図10に示すように、本実施例の半導体装置100は、フローティング領域30の第1層132の構成が、第1実施例とは異なる。第1実施例では、第1層32の幅は、トレンチ12の底部12aの幅とほぼ同一に形成されている。これに対し、本実施例では、第1層132の幅が、トレンチ12の底部12aの幅よりも広く形成されている。そのため、本実施例の半導体装置100では、トレンチ12のコーナー部付近に第1層132を配置することができ、コーナー部付近に電界集中することを効果的に抑制することができる。
第4実施例について、第1実施例とは異なる点を中心に説明する。図11に示すように、本実施例の半導体装置200も、フローティング領域30の第1層232の構成が、第1実施例とは異なる。本実施例では、第1層232の幅が、トレンチ12の底部12aの幅よりも狭く形成されている。そのため、本実施例の半導体装置200では、空乏層の横方向への広がりが抑制されるため、オン抵抗を低減することができる。
Claims (3)
- 半導体基板の表面側に設けられた第1導電型のコンタクト領域と、
コンタクト領域より深い位置に設けられているとともにコンタクト領域に隣接する第2導電型のボディ領域と、
ボディ領域より深い位置に設けられているとともにボディ領域によってコンタクト領域から分離されている第1導電型のドリフト領域と、
半導体基板の表面からコンタクト領域及びボディ領域を貫通して形成され、その底部がドリフト領域内に位置するトレンチと、
トレンチの内面を覆う絶縁膜と、
絶縁膜で覆われた状態でトレンチ内に収容されているゲート電極と、
ドリフト領域内のトレンチの底部より深い位置に設けられているとともに、トレンチの底部に隣接する第2導電型のフローティング領域と、
を有しており、
フローティング領域は、トレンチの底部に隣接している第1層と、第1層よりも深い位置に設けられている第2層とを有しており、第1層の幅は、第2層の幅よりも広く、かつ、トレンチの底部の幅と同一か又はそれよりも狭い、
ことを特徴とする半導体装置。 - 半導体装置を製造する方法であって、
半導体装置は、
半導体基板の表面側に設けられた第1導電型のコンタクト領域と、
コンタクト領域より深い位置に設けられているとともにコンタクト領域に隣接する第2導電型のボディ領域と、
ボディ領域より深い位置に設けられているとともにボディ領域によってコンタクト領域から分離されている第1導電型のドリフト領域と、
半導体基板の表面からコンタクト領域及びボディ領域を貫通して形成され、その底部がドリフト領域内に位置するトレンチと、
トレンチの内面を覆う絶縁膜と、
絶縁膜で覆われた状態でトレンチ内に収容されているゲート電極と、
ドリフト領域内のトレンチの底部より深い位置に設けられているとともに、トレンチの底部に隣接する第2導電型のフローティング領域と、
を有しており、
フローティング領域は、トレンチの底部に隣接している第1層と、第1層よりも深い位置に設けられている第2層とを有しており、第1層の幅は、第2層の幅よりも広く、
半導体装置を製造する方法は、
半導体基板の表面から深さ方向に伸びるトレンチを形成するトレンチ形成工程と、
形成されたトレンチの底部に、第1の注入エネルギーで第2導電型の不純物を注入することによって第1層に対応する第2導電型領域を形成する第1の不純物注入工程と、
トレンチの底部に第2導電型の不純物が注入された後に、トレンチの少なくとも側面を覆う保護膜を形成する保護膜形成工程と、
保護膜が形成された後に、さらに、トレンチの底部に、第1の注入エネルギーよりも大きい第2の注入エネルギーで第2導電型の不純物を注入することによって第2層に対応する第2導電型領域を形成する第2の不純物注入工程と、
を有しており、
第1の不純物注入工程では、形成されたトレンチの少なくとも側面に保護膜が形成されていない状態で、又は、形成されたトレンチの少なくとも側面に保護膜形成工程で形成される保護膜より厚みの薄い保護膜が形成された状態で、第2導電型の不純物を注入する、
ことを特徴とする半導体装置の製造方法。 - 保護膜形成工程において形成される保護膜は、半導体基板の表面を酸化することで形成される犠牲酸化膜であって、
第2の注入エネルギーで第2導電型の不純物が注入された後に、犠牲酸化膜を除去する犠牲酸化膜除去工程をさらに有する、
ことを特徴とする請求項2に記載の半導体装置の製造方法。
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JP6280057B2 (ja) | 2015-01-15 | 2018-02-14 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
JP6266166B2 (ja) * | 2015-03-30 | 2018-01-24 | 三菱電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
US10903163B2 (en) * | 2015-10-19 | 2021-01-26 | Vishay-Siliconix, LLC | Trench MOSFET with self-aligned body contact with spacer |
JP6623772B2 (ja) * | 2016-01-13 | 2019-12-25 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
JP6560142B2 (ja) * | 2016-02-26 | 2019-08-14 | トヨタ自動車株式会社 | スイッチング素子 |
CN107437557A (zh) * | 2016-05-25 | 2017-12-05 | 美普森半导体公司(股) | 沟槽型碳化硅mosfet器件及其制备方法 |
CN106876439B (zh) * | 2017-02-08 | 2020-04-14 | 上海华虹宏力半导体制造有限公司 | 超结器件及其制造方法 |
JP6811118B2 (ja) * | 2017-02-27 | 2021-01-13 | 株式会社豊田中央研究所 | Mosfet |
JP7068916B2 (ja) | 2018-05-09 | 2022-05-17 | 三菱電機株式会社 | 炭化珪素半導体装置、電力変換装置、および炭化珪素半導体装置の製造方法 |
JP2020072158A (ja) * | 2018-10-30 | 2020-05-07 | ローム株式会社 | 半導体装置 |
CN110112218A (zh) * | 2019-05-29 | 2019-08-09 | 西安电子科技大学 | 一种具有单侧掩蔽层的碳化硅mosfet器件 |
WO2020238588A1 (zh) * | 2019-05-29 | 2020-12-03 | 西安电子科技大学 | 一种具有掩蔽层结构的碳化硅mosfet器件 |
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