JP6694059B2 - パワーモジュール用基板およびパワーモジュール - Google Patents
パワーモジュール用基板およびパワーモジュール Download PDFInfo
- Publication number
- JP6694059B2 JP6694059B2 JP2018514623A JP2018514623A JP6694059B2 JP 6694059 B2 JP6694059 B2 JP 6694059B2 JP 2018514623 A JP2018514623 A JP 2018514623A JP 2018514623 A JP2018514623 A JP 2018514623A JP 6694059 B2 JP6694059 B2 JP 6694059B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- power module
- metal plate
- module substrate
- silver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
まず、個片(1個取り)のパワーモジュール用基板およびそれを含むパワーモジュールについて説明する。
次に、図8〜図10等を参照して、本開示の実施形態におけるパワーモジュール用基板10の製造方法を説明する。なお、多数個取りパワーモジュール用基板110を分割してパワーモジュール用基板10を作製する例の説明を行なうが、パワーモジュール用基板10は1個取りで作製しても構わない。
1a・・・凹部
2・・・・金属板
2a・・・くぼみ
3・・・・第1電気めっき層
3a・・・銀層
3b・・・ニッケル層
3bb・・・(凹凸部分の)ニッケル
3c・・・パラジウム層
4・・・・端子板
5・・・・放熱板
6・・・・第2電気めっき層(ニッケル層)
10・・・・パワーモジュール用基板
11・・・・電子部品
12・・・・樹脂層
13・・・・ボンディングワイヤ
20・・・・パワーモジュール
30・・・・放熱用部材
101・・・・絶縁母基板
102・・・・金属母板
110・・・・多数個取りパワーモジュール用基板
115・・・・ろう材ペースト層
116・・・・めっきレジスト
117・・・・エッチングレジスト
Claims (11)
- 上面および下面を有する絶縁基板と、
上面および下面を有し、該下面が前記絶縁基板の前記上面に対向して接合された金属板と、
前記金属板の上面の中央部を部分的に被覆している第1電気めっき層とを備えており、
該第1電気めっき層が少なくとも銀層を有しており、該銀層における銀の粒径が前記金属板の上面部分における金属の粒径以上の大きさであるパワーモジュール用基板。 - 前記第1電気めっき層が、前記銀層と前記金属板の上面との間に配置されたニッケル層をさらに含んでいる請求項1に記載のパワーモジュール用基板。
- 平面視において、前記第1電気めっき層の外周が凹凸を有する形状である請求項1または請求項2に記載のパワーモジュール用基板。
- 平面視において、前記第1電気めっき層の外周が、平面視において凹凸を有する形状であり、前記第1電気めっき層の外周の凹凸部分の少なくとも一部にニッケルが存在している請求項2に記載のパワーモジュール用基板。
- 前記金属板が、前記上面のうち前記第1電気めっき層の外周に沿った部分においてくぼみを有する請求項1〜請求項4のいずれかに記載のパワーモジュール用基板。
- 前記くぼみの内側面が、該くぼみの開口から底部に向かって内側に傾斜または湾曲している請求項5に記載のパワーモジュール用基板。
- 前記くぼみの内側面の表面粗さが、前記金属板の上面の表面粗さよりも大きい請求項5に記載のパワーモジュール用基板。
- 上面および下面を有しており、前記上面が前記絶縁基板の下面に対向して接合された放熱板と
該放熱板の下面を覆う第2電気めっき層とをさらに備えており、
該第2電気めっき層の外周の少なくとも一部が前記放熱板の下面の外周から離れている請求項1〜請求項7のいずれかに記載のパワーモジュール用基板。 - 前記第2電気めっき層がニッケル層を主成分とする請求項8に記載のパワーモジュール用
基板。 - 請求項1〜請求項9のいずれかに記載のパワーモジュール用基板と、
該パワーモジュール用基板の前記第1電気めっき層上に搭載された電子部品と、
前記金属板の上面のうち前記第1電気めっき層で被覆されていない部分から前記電子部品にかけて覆う樹脂層とを備えるパワーモジュール。 - 請求項8または請求項9に記載のパワーモジュール用基板と、
該パワーモジュール用基板の前記第1電気めっき層上に搭載された電子部品と、
前記放熱板の下面の外周から前記電子部品にかけて覆う樹脂層とを備えるパワーモジュール。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016088160 | 2016-04-26 | ||
JP2016088160 | 2016-04-26 | ||
JP2016185720 | 2016-09-23 | ||
JP2016185720 | 2016-09-23 | ||
PCT/JP2017/016387 WO2017188254A1 (ja) | 2016-04-26 | 2017-04-25 | パワーモジュール用基板、パワーモジュールおよびパワーモジュール用基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2017188254A1 JPWO2017188254A1 (ja) | 2019-02-28 |
JP6694059B2 true JP6694059B2 (ja) | 2020-05-13 |
Family
ID=60159657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018514623A Active JP6694059B2 (ja) | 2016-04-26 | 2017-04-25 | パワーモジュール用基板およびパワーモジュール |
Country Status (5)
Country | Link |
---|---|
US (1) | US10763184B2 (ja) |
EP (1) | EP3451372B1 (ja) |
JP (1) | JP6694059B2 (ja) |
CN (1) | CN109075132B (ja) |
WO (1) | WO2017188254A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4324307A1 (en) * | 2021-04-11 | 2024-02-21 | Telefonaktiebolaget LM Ericsson (publ) | Circuit board assembly and radio unit comprising the same |
WO2023120185A1 (ja) * | 2021-12-24 | 2023-06-29 | ローム株式会社 | 半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7202563B2 (en) | 2004-03-25 | 2007-04-10 | Kabushiki Kaisha Toshiba | Semiconductor device package having a semiconductor element with resin |
JP2006202938A (ja) | 2005-01-20 | 2006-08-03 | Kojiro Kobayashi | 半導体装置及びその製造方法 |
JP2006240955A (ja) * | 2005-03-07 | 2006-09-14 | Denki Kagaku Kogyo Kk | セラミック基板、セラミック回路基板及びそれを用いた電力制御部品。 |
TW201011936A (en) * | 2008-09-05 | 2010-03-16 | Advanced Optoelectronic Tech | Light emitting device and fabrication thereof |
JP5936407B2 (ja) * | 2012-03-26 | 2016-06-22 | 株式会社日立製作所 | パワーモジュール製造方法 |
JP6011010B2 (ja) | 2012-05-01 | 2016-10-19 | 大日本印刷株式会社 | Led用リードフレームまたは基板およびその製造方法、ならびに半導体装置およびその製造方法 |
US8716864B2 (en) * | 2012-06-07 | 2014-05-06 | Ixys Corporation | Solderless die attach to a direct bonded aluminum substrate |
CN104412382B (zh) * | 2012-07-05 | 2017-10-13 | 三菱电机株式会社 | 半导体装置 |
JP6115215B2 (ja) * | 2013-03-15 | 2017-04-19 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法及びパワーモジュールの製造方法 |
JP6262968B2 (ja) | 2013-09-09 | 2018-01-17 | Dowaメタルテック株式会社 | 電子部品搭載基板およびその製造方法 |
JP5983700B2 (ja) | 2013-12-09 | 2016-09-06 | 株式会社デンソー | 半導体装置およびその製造方法、複合成形体 |
JPWO2015114987A1 (ja) * | 2014-01-29 | 2017-03-23 | Ngkエレクトロデバイス株式会社 | パワーモジュール用基板およびそれを用いてなるパワーモジュール |
DE112015000139B4 (de) * | 2014-03-19 | 2021-10-28 | Fuji Electric Co., Ltd. | Halbleitermoduleinheit und Halbleitermodul |
-
2017
- 2017-04-25 US US16/095,060 patent/US10763184B2/en active Active
- 2017-04-25 WO PCT/JP2017/016387 patent/WO2017188254A1/ja active Application Filing
- 2017-04-25 JP JP2018514623A patent/JP6694059B2/ja active Active
- 2017-04-25 CN CN201780023054.1A patent/CN109075132B/zh active Active
- 2017-04-25 EP EP17789536.4A patent/EP3451372B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20190181066A1 (en) | 2019-06-13 |
EP3451372A4 (en) | 2019-10-23 |
CN109075132A (zh) | 2018-12-21 |
CN109075132B (zh) | 2022-03-08 |
WO2017188254A1 (ja) | 2017-11-02 |
JPWO2017188254A1 (ja) | 2019-02-28 |
US10763184B2 (en) | 2020-09-01 |
EP3451372A1 (en) | 2019-03-06 |
EP3451372B1 (en) | 2021-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6297082B2 (ja) | セラミック基板およびその製造方法 | |
WO2010052973A1 (ja) | 半導体装置及びその製造方法 | |
JP7483955B2 (ja) | パワーモジュール用基板およびパワーモジュール | |
JP2011077519A (ja) | リードフレーム及びその製造方法 | |
JP2019176034A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2023126980A (ja) | 電気めっきされたダイ取り付けを備える半導体デバイス | |
JP2017188534A (ja) | 電子装置及びその製造方法 | |
JP4604641B2 (ja) | 半導体装置 | |
JP6694059B2 (ja) | パワーモジュール用基板およびパワーモジュール | |
JP6685112B2 (ja) | リードフレーム及びリードフレームパッケージ、並びにこれらの製造方法 | |
JP2021005670A (ja) | 電子部品装置及び電子部品装置の製造方法 | |
JP4344560B2 (ja) | 半導体チップおよびこれを用いた半導体装置 | |
JP2019121698A (ja) | 半導体装置および半導体装置の製造方法 | |
JP7117960B2 (ja) | パワーモジュール用基板およびパワーモジュール | |
JP5494559B2 (ja) | 半導体装置およびその製造方法 | |
JP7221401B2 (ja) | 電気回路基板及びパワーモジュール | |
JP7170501B2 (ja) | パワーモジュール用基板およびパワーモジュール | |
JP2020077665A (ja) | 半導体素子および半導体装置 | |
TWI497670B (zh) | 基於鋁合金引線框架的半導體元件及製備方法 | |
JP4775369B2 (ja) | 半導体チップ、半導体装置および製造方法 | |
JP4749165B2 (ja) | 多数個取り配線基板 | |
JP2000195888A (ja) | 半導体装置 | |
JP3826776B2 (ja) | 半導体装置 | |
JP2015109334A (ja) | 半導体装置 | |
JP5865921B2 (ja) | 回路基板およびそれを用いた電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181009 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191008 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191118 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200317 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200416 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6694059 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |