JP6546376B2 - 電子部品 - Google Patents

電子部品 Download PDF

Info

Publication number
JP6546376B2
JP6546376B2 JP2014161240A JP2014161240A JP6546376B2 JP 6546376 B2 JP6546376 B2 JP 6546376B2 JP 2014161240 A JP2014161240 A JP 2014161240A JP 2014161240 A JP2014161240 A JP 2014161240A JP 6546376 B2 JP6546376 B2 JP 6546376B2
Authority
JP
Japan
Prior art keywords
layer
solder layer
solder
arrangement region
metal material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014161240A
Other languages
English (en)
Other versions
JP2016039240A (ja
Inventor
藤井 義磨郎
義磨郎 藤井
小栗 洋
洋 小栗
明 坂本
坂本  明
智也 田口
智也 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Priority to JP2014161240A priority Critical patent/JP6546376B2/ja
Priority to PCT/JP2015/072215 priority patent/WO2016021632A1/ja
Priority to CN201580042313.6A priority patent/CN106663641B/zh
Priority to KR1020167031733A priority patent/KR102387336B1/ko
Priority to US15/320,835 priority patent/US20170200693A1/en
Priority to TW104125674A priority patent/TWI711137B/zh
Publication of JP2016039240A publication Critical patent/JP2016039240A/ja
Application granted granted Critical
Publication of JP6546376B2 publication Critical patent/JP6546376B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/02002Arrangements for conducting electric current to or from the device in operations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0203Containers; Encapsulations, e.g. encapsulation of photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/2747Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/28105Layer connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. layer connectors on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29012Shape in top view
    • H01L2224/29013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83469Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12043Photo diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

本発明は、電子部品に関する。
フォトダイオードと、フォトダイオードの上面の受光部以外の部位に配置されている端子と、端子に配置されているバンプと、を備えた電子部品が知られている(たとえば、特許文献1参照)。この電子部品には、他の電子部品として、ICチップが実装される。
特開2000−307133号公報
本発明は、Au−Sn合金ハンダを用いて他の電子部品を実装する場合でも、当該他の電子部品の実装を適切に行うことが可能な電子部品を提供することを目的とする。
本発明に係る電子部品は、基材と、基材上に配置されている、複数の導電性金属材料層の積層体と、積層体上に配置されているAu−Sn合金ハンダからなるハンダ層と、を備え、積層体は、最外層を構成する導電性金属材料層として、Auからなる表面層を有し、表面層は、ハンダ層が配置されるハンダ層配置領域と、ハンダ層が配置されないハンダ層非配置領域と、を含み、ハンダ層配置領域とハンダ層非配置領域とは、空間的に離間していることを特徴とする。
本発明に係る電子部品では、積層体の最外層を構成するAuからなる表面層が、ハンダ層配置領域とハンダ層非配置領域とを含み、これらのハンダ層配置領域とハンダ層非配置領域とは空間的に離間している。このため、本発明に係る電子部品に他の電子部品を実装する際に、積層体上に配置されているハンダ層(Au−Sn合金ハンダ)は溶融するものの、溶融したAu−Sn合金ハンダがハンダ層配置領域からハンダ層非配置領域に流れ出すことが抑制される。
ハンダ層と表面層との熱履歴により、表面層のAuがハンダ層に拡散し、Au−Sn合金ハンダの組成が変化することがある。Au−Sn合金ハンダの組成が変化した場合、Au−Sn合金ハンダの融点にバラつきが生じたり、他の電子部品の接合状態が不均一となったりするおそれがある。上述したように、ハンダ層配置領域とハンダ層非配置領域とは空間的に離間しているので、表面層のAuがハンダ層に拡散する場合でも、ハンダ層非配置領域のAuはハンダ層に拡散することはなく、表面層からのAuの拡散量は抑制される。このため、Au−Sn合金ハンダの組成の変化が抑制される。
以上のことから、本発明によれば、Au−Sn合金ハンダを用いて他の電子部品を実装する場合でも、当該他の電子部品の実装を適切に行うことができる。
ハンダ層配置領域は、ハンダ層非配置領域に囲まれるように、ハンダ層非配置領域の内側に位置すると共に、その全周においてハンダ層非配置領域と空間的に離間していてもよい。この場合、溶融したAu−Sn合金ハンダがハンダ層配置領域からハンダ層非配置領域に流れ出すことがより一層確実に抑制できる。また、ハンダ層配置領域からのAuの拡散量がより一層抑制されるため、Au−Sn合金ハンダの組成の変化を確実に抑制することができる。
ハンダ層配置領域とハンダ層非配置領域とは、表面層に形成されたスリットにより空間的に離間していてもよい。この場合、ハンダ層配置領域とハンダ層非配置領域とが空間的に離間している構成を簡易に実現することができる。
ハンダ層は、Ptからなるバリア層を介して、積層体上に配置されていてもよい。この場合、ハンダ層配置領域からのAuの拡散が防がれるため、Au−Sn合金ハンダの組成の変化をより一層確実に抑制することができる。
本発明によれば、Au−Sn合金ハンダを用いて他の電子部品を実装する場合でも、当該他の電子部品の実装を適切に行うことが可能な電子部品を提供することができる。
本発明の実施形態に係る電子部品を示す平面図である。 図1に示されたII−II線に沿った断面構成を説明するための図である。 本実施形態の変形例に係る電子部品の断面構成を説明するための図である。 ハンダ層を形成する過程を説明するための図である。 ハンダ層配置領域とハンダ層非配置領域とが空間的に離間していない電子部品の断面構成を説明するための図である。 本実施形態の他の変形例に係る電子部品を示す平面図である。 本実施形態の他の変形例に係る電子部品の断面構成を説明するための図である。 本実施形態の他の変形例に係る電子部品を示す平面図である。
以下、図面を参照しながら、本発明の実施形態について詳細に説明する。なお、説明において、同一要素又は同一機能を有する要素には、同一符号を用いることとし、重複する説明は省略する。
図1及び図2を参照して、本実施形態に係る電子部品1Aの構成を説明する。図1は、本実施形態に係る電子部品の平面図である。図2は、図1に示されたII−II線に沿った断面構成を説明するための図である。
電子部品1Aは、基材10、積層体20、及びハンダ層30を備えている。電子部品1Aは、たとえば、他の電子部品3が実装されるサブマウント基板として機能する。他の電子部品3には、例えば、レーザーダイオードなどが挙げられる。実装には、電気的且つ物理的に接続することだけでなく、物理的にのみ接続することも含まれる。
基材10は、半導体基板11を含んでいる。半導体基板11は、互いに対向する一対の主面11a,11bと、側面11cと、を有する、第一導電型(たとえば、N型)のシリコン基板である。側面11cは、一対の主面11a,11b間を連結するように一対の主面11a,11bの対向方向に延びている。本実施形態では、半導体基板11は、図1に示されるように、平面視で矩形形状を呈しており、四つの側面11cを有する。
半導体基板11は、主面11a側に位置する第二導電型(たとえば、P型)の第一半導体領域13を有している。第一半導体領域13は、第二導電型の不純物(ボロンなど)が添加された領域であり、半導体基板11よりも不純物濃度が高い。第一半導体領域13は、たとえば、イオン注入法又は拡散法により、第二導電型の不純物を主面11a側から半導体基板11に添加することにより形成される。
基材10では、半導体基板11と第一半導体領域13とでPN接合が形成されている。すなわち、基材10は、主面11aが光入射面である表面入射型のフォトダイオードである。第一半導体領域13は、半導体基板11とで光感応領域を構成している。他の電子部品3としてレーザーダイオードが電子部品1Aに実装される場合、上記フォトダイオードは、レーザーダイオードの出力をモニタする。
基材10は、半導体基板11の主面11a上に配置されているパッシベーション膜15を含んでいる。パッシベーション膜15には、第一半導体領域13に対応する位置に開口15aが形成されている。第一半導体領域13(光感応領域)には、パッシベーション膜15に形成された開口15aを通って、光が入射する。パッシベーション膜15は、たとえばSiNからなる。パッシベーション膜15は、たとえばCVD(Chemical Vapor Deposition)法により形成される。本実施形態では、上記フォトダイオードに接続されるカソード電極(パッド)及びアノード電極(パッド)の図示を省略している。
積層体20は、基材10(パッシベーション膜15上)上に配置されている。詳細には、積層体20は、パッシベーション膜15における、開口15aが形成されていない領域上に配置されている。積層体20は、複数の導電性金属材料層(本実施形態では、三層の導電性金属材料層21,22,23)からなる。各導電性金属材料層21,22,23は、導電性金属材料からなる層である。三層の導電性金属材料層21,22,23は、基材10側から、導電性金属材料層21、導電性金属材料層22、導電性金属材料層23の順に積層されている。各導電性金属材料層21,22,23は、たとえば真空蒸着法又はスパッタリング法により形成される。
導電性金属材料層21は、基材10(パッシベーション膜15)との接触層を構成しており、基材10(パッシベーション膜15)との密着性を高める。導電性金属材料層21は、たとえばTiからなる。導電性金属材料層21の厚みは、たとえば0.1〜0.2μmである。導電性金属材料層21は、Ti以外に、Crなどからなっていてもよい。
導電性金属材料層22は、中間のバリア層を構成しており、他の導電性金属材料層21,23から金属材料(金属原子)が拡散するのを防ぐ。導電性金属材料層22は、たとえばPtからなる。導電性金属材料層22の厚みは、たとえば0.2〜0.3μmである。
導電性金属材料層23は、積層体20の最外層を構成する、すなわち表面層を構成している。導電性金属材料層23は、たとえばAuからなる。導電性金属材料層23の厚みは、たとえば0.1〜0.5μmである。
導電性金属材料層23は、ハンダ層30が配置されるハンダ層配置領域23aと、ハンダ層30が配置されないハンダ層非配置領域23bと、を含んでいる。ハンダ層配置領域23aとハンダ層非配置領域23bとは、導電性金属材料層22上において、空間的に離間している。すなわち、ハンダ層配置領域23aとハンダ層非配置領域23bとが空間的に離間している領域では、導電性金属材料層22が露出している。
本実施形態では、ハンダ層配置領域23aは、ハンダ層非配置領域23bに囲まれるように、ハンダ層非配置領域23bの内側に位置すると共に、その全周においてハンダ層非配置領域23bと空間的に離間している。ハンダ層配置領域23aとハンダ層非配置領域23bとは、導電性金属材料層23に形成されたスリット23cにより空間的に離間している。
ハンダ層30は、Au−Sn合金ハンダからなり、積層体20(導電性金属材料層23のハンダ層配置領域23a)上に配置されている。ハンダ層30は、導電性金属材料層23(ハンダ層配置領域23a)に接している。ハンダ層30は、たとえばフォトレジスト(ネガ型のフォトレジスト)を用いたリフトオフ法により形成される。ハンダ層30の厚みは、たとえば2.0〜5.0μmである。
以上のように、本実施形態では、Auからなる導電性金属材料層23が、ハンダ層配置領域23aとハンダ層非配置領域23bとを含み、これらのハンダ層配置領域23aとハンダ層非配置領域23bとは空間的に離間している。このため、電子部品1Aに他の電子部品3を実装する際に、積層体20上に配置されているハンダ層30(Au−Sn合金ハンダ)は溶融するものの、溶融したAu−Sn合金ハンダがハンダ層配置領域23aからハンダ層非配置領域23bに流れ出すことが抑制される。
電子部品1Aの製造過程におけるハンダ層30と導電性金属材料層23との熱履歴により、導電性金属材料層23のAuがハンダ層30に拡散し、Au−Sn合金ハンダの組成が変化することがある。Au−Sn合金ハンダの組成が変化した場合、Au−Sn合金ハンダの融点にバラつきが生じたり、他の電子部品3の接合状態が不均一となったりするおそれがある。
これに対し、本実施形態では、ハンダ層配置領域23aとハンダ層非配置領域23bとは空間的に離間しているので、導電性金属材料層23のAuがハンダ層30に拡散する場合でも、ハンダ層非配置領域23bのAuはハンダ層30に拡散することはなく、導電性金属材料層23からのAuの拡散量は抑制される。このため、Au−Sn合金ハンダの組成の変化が抑制される。
これらの結果、電子部品1Aによれば、Au−Sn合金ハンダを用いて他の電子部品3を実装する場合でも、他の電子部品3の実装を適切に行うことができる。
本実施形態では、ハンダ層配置領域23aは、ハンダ層非配置領域23bに囲まれるように、ハンダ層非配置領域23bの内側に位置すると共に、その全周においてハンダ層非配置領域23bと空間的に離間している。これにより、溶融したAu−Sn合金ハンダがハンダ層配置領域23aからハンダ層非配置領域23bに流れ出すことがより一層確実に抑制できる。また、ハンダ層配置領域23aからのAuの拡散量がより一層抑制されるため、Au−Sn合金ハンダの組成の変化を確実に抑制することができる。
本実施形態では、ハンダ層配置領域23aとハンダ層非配置領域23bとは、導電性金属材料層23に形成されたスリットにより空間的に離間している。これにより、ハンダ層配置領域23aとハンダ層非配置領域23bとが空間的に離間している構成を簡易に実現することができる。
次に、図3を参照して、本実施形態の変形例に係る電子部品1Bの構成を説明する。図3は、本実施形態の変形例に係る電子部品の断面構成を説明するための図である。
電子部品1Bは、基材10、積層体20、ハンダ層30、及びバリア層40を備えている。電子部品1Bも、電子部品1Aと同様に、たとえば、他の電子部品3が実装されるサブマウント基板として機能する。
バリア層40は、積層体20とハンダ層30との間に配置されている。バリア層40は、積層体20(導電性金属材料層23)に接すると共に、ハンダ層30に接している。すなわち、ハンダ層30は、バリア層40を介して、積層体20上に配置されている。バリア層40は、Ptからなる。バリア層40は、たとえば、リフトオフ法によりハンダ層30と共に形成される。バリア層40の厚みは、たとえば0.2〜0.3μmである。
本変形例では、バリア層40により、導電性金属材料層23(ハンダ層配置領域23a)からのAuの拡散が防がれる。したがって、電子部品1Bにおいて、Au−Sn合金ハンダの組成の変化をより一層確実に抑制することができる。
バリア層40が積層体20とハンダ層30との間に配置されている場合、ハンダ層配置領域23aとハンダ層非配置領域23bとが空間的に離間していなくても、ハンダ層配置領域23aからハンダ層非配置領域23bへの溶融したAu−Sn合金ハンダの流れ出しが抑制されることが期待される。しかしながら、以下の事象により、バリア層40が存在している場合でも、上述した溶融したAu−Sn合金ハンダの流れ出しは抑制され難い。
ハンダ層30が上述したリフトオフ法により形成されている場合、フォトレジスト50の形状に起因して、図4及び図5に示されるように、ハンダ層30がバリア層40よりも広く形成される。すなわち、ハンダ層30は、バリア層40を覆うと共に積層体20(導電性金属材料層23)に接するように形成される。ハンダ層30の厚みは、一般に、バリア層40の厚みよりも大きい。このため、ハンダ層30は、当該ハンダ層30に平行な方向に広がりやすく、ハンダ層30がバリア層40よりもより一層広く形成されてしまう。ハンダ層30が導電性金属材料層23に接していると、溶融したAu−Sn合金ハンダは、導電性金属材料層23上を濡れ広がるおそれがあり、ハンダ層配置領域23aからハンダ層非配置領域23bに流れ出してしまう。
本変形例では、電子部品1Aと同様に、ハンダ層配置領域23aとハンダ層非配置領域23bとは空間的に離間しているので、溶融したAu−Sn合金ハンダのハンダ層配置領域23aからハンダ層非配置領域23bへの流れ出しが確実に抑制される。
以上、本発明の実施形態について説明してきたが、本発明は必ずしも上述した実施形態に限定されるものではなく、その要旨を逸脱しない範囲で様々な変更が可能である。
基材10は、表面入射型のフォトダイオードに限られない。基材10は、図6及び図7に示されるように、少なくともいずれか一つの側面11cが光入射面である側面入射型のフォトダイオードであってもよい。図6及び図7に示された電子部品1Aでは、パッシベーション膜15から露出するように、カソード電極(パッド)61と、アノード電極(パッド)63と、が配置されている。図6は、本実施形態の他の変形例に係る電子部品を示す平面図である。図7は、本実施形態の他の変形例に係る電子部品の断面構成を説明するための図である。
ハンダ層配置領域23aは、ハンダ層非配置領域23bに囲まれるように、ハンダ層非配置領域23bの内側に位置すると共に、その全周においてハンダ層非配置領域23bと空間的に離間している必要はない。たとえば、ハンダ層配置領域23aとハンダ層非配置領域23bとは、図8に示されるように、直線状のスリット23cで分割されるように空間的に離間していてもよい。
積層体20は、三層の導電性金属材料層21,22,23からなる必要はない。積層体20は、二層の導電性金属材料層からなっていてもよく、また、四層以上の導電性金属材料層からなっていてもよい。これらの場合でも、積層体20における最外層を構成する導電性金属材料層、すなわち表面層がAuからなっていればよい。
基材10は、フォトダイオードでなくてもよく、また、基材10は、半導体基板11を含んでいる必要はない。基材10は、半導体基板11の代わりに、たとえばセラミック基板又はガラス基板などを含んでいてもよい。セラミック基板には、窒化アルミニウム(AlN)基板又はアルミナ(Al)基板などが用いられる。
電子部品1A,1Bに実装される他の電子部品3は、レーザーダイオードである必要はない。他の電子部品3は、たとえば受光素子、発光素子、半導体パッケージ、回路基板、能動部品、又は受動部品であってもよい。
1A,1B…電子部品、10…基材、20…積層体、21,22,23…導電性金属材料層、23a…ハンダ層配置領域、23b…ハンダ層非配置領域、23c…スリット、30…ハンダ層、40…バリア層。

Claims (5)

  1. 基材と、
    前記基材上に配置されている、複数の導電性金属材料層の積層体と、
    前記積層体上に配置されている、Au−Sn合金ハンダからなるハンダ層と、を備え、
    前記積層体は、最外層を構成する前記導電性金属材料層として、Auからなる表面層を有し、
    前記表面層は、前記ハンダ層が配置されるハンダ層配置領域と、前記ハンダ層が配置されないハンダ層非配置領域と、を含み、
    前記ハンダ層配置領域と前記ハンダ層非配置領域とは、前記ハンダ層非配置領域のAuが前記ハンダ層に拡散することがないように空間的に離間しており、
    前記ハンダ層配置領域と前記ハンダ層非配置領域とが空間的に離間している領域では、前記表面層下の前記導電性金属材料層が露出していることを特徴とする電子部品。
  2. 前記ハンダ層配置領域は、前記ハンダ層非配置領域に囲まれるように、前記ハンダ層非配置領域の内側に位置すると共に、その全周において前記ハンダ層非配置領域と空間的に離間していることを特徴とする請求項1に記載の電子部品。
  3. 前記ハンダ層配置領域と前記ハンダ層非配置領域とは、前記表面層に形成されたスリットにより空間的に離間していることを特徴とする請求項1又は2に記載の電子部品。
  4. 前記ハンダ層は、Ptからなるバリア層を介して、前記積層体上に配置されていることを特徴とする請求項1〜3のいずれか一項に記載の電子部品。
  5. 前記複数の導電性金属材料層は、前記基材との接触層を構成している導電性金属材料層と、当該導電性金属材料層と前記表面層との間に位置していると共にバリア層を構成している導電性金属材料層と、を含み、
    前記ハンダ層配置領域と前記ハンダ層非配置領域とが空間的に離間している前記領域では、前記バリア層を構成している導電性金属材料層が露出していることを特徴とする請求項1〜4のいずれか一項に記載の電子部品。
JP2014161240A 2014-08-07 2014-08-07 電子部品 Expired - Fee Related JP6546376B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2014161240A JP6546376B2 (ja) 2014-08-07 2014-08-07 電子部品
PCT/JP2015/072215 WO2016021632A1 (ja) 2014-08-07 2015-08-05 電子部品
CN201580042313.6A CN106663641B (zh) 2014-08-07 2015-08-05 电子部件
KR1020167031733A KR102387336B1 (ko) 2014-08-07 2015-08-05 전자 부품
US15/320,835 US20170200693A1 (en) 2014-08-07 2015-08-05 Electronic component
TW104125674A TWI711137B (zh) 2014-08-07 2015-08-06 電子零件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014161240A JP6546376B2 (ja) 2014-08-07 2014-08-07 電子部品

Publications (2)

Publication Number Publication Date
JP2016039240A JP2016039240A (ja) 2016-03-22
JP6546376B2 true JP6546376B2 (ja) 2019-07-17

Family

ID=55263893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014161240A Expired - Fee Related JP6546376B2 (ja) 2014-08-07 2014-08-07 電子部品

Country Status (6)

Country Link
US (1) US20170200693A1 (ja)
JP (1) JP6546376B2 (ja)
KR (1) KR102387336B1 (ja)
CN (1) CN106663641B (ja)
TW (1) TWI711137B (ja)
WO (1) WO2016021632A1 (ja)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4201432B2 (ja) 1999-04-23 2008-12-24 ローム株式会社 光検出用モジュール
JP3700598B2 (ja) * 2001-03-21 2005-09-28 セイコーエプソン株式会社 半導体チップ及び半導体装置、回路基板並びに電子機器
JP2004039988A (ja) * 2002-07-05 2004-02-05 Shinko Electric Ind Co Ltd 素子搭載用回路基板及び電子装置
FR2848338B1 (fr) * 2002-12-05 2005-05-13 Cit Alcatel Procede de fabrication d'un module electronique comportant un composant actif sur une embase
JP2006086453A (ja) * 2004-09-17 2006-03-30 Yamato Denki Kogyo Kk 表面処理方法、および電子部品の製造方法
JP5526336B2 (ja) * 2007-02-27 2014-06-18 Dowaエレクトロニクス株式会社 半田層及びそれを用いたデバイス接合用基板並びにその製造方法
JP2008258459A (ja) * 2007-04-06 2008-10-23 Toshiba Corp 発光装置及びその製造方法
JP5882014B2 (ja) * 2011-10-04 2016-03-09 エスアイアイ・セミコンダクタ株式会社 半導体装置
JP5716627B2 (ja) * 2011-10-06 2015-05-13 オムロン株式会社 ウエハの接合方法及び接合部の構造
JP2013125768A (ja) * 2011-12-13 2013-06-24 Japan Oclaro Inc はんだ接合デバイス及び受信モジュール
US9520370B2 (en) * 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures

Also Published As

Publication number Publication date
JP2016039240A (ja) 2016-03-22
CN106663641B (zh) 2019-07-16
CN106663641A (zh) 2017-05-10
KR20170040119A (ko) 2017-04-12
TW201606966A (zh) 2016-02-16
US20170200693A1 (en) 2017-07-13
WO2016021632A1 (ja) 2016-02-11
TWI711137B (zh) 2020-11-21
KR102387336B1 (ko) 2022-04-15

Similar Documents

Publication Publication Date Title
US8450760B2 (en) Semiconductor light emitting device with integrated electronic components
JP6029760B2 (ja) オプトエレクトロニクス半導体モジュール
JP6195689B1 (ja) パワーモジュール
US20050194605A1 (en) Flip-chip light emitting diode device without sub-mount
JP2006210777A (ja) 半導体装置
TWI414082B (zh) 具有過電壓保護之發光二極體晶片
JP5813138B2 (ja) キャリア基板、および半導体チップの製造方法
JP2016219505A (ja) 発光装置
JP2005354060A (ja) 表面実装型チップスケールパッケージ
JP2017130527A (ja) 半導体装置
JP2019083328A (ja) Led用担体
JP6546376B2 (ja) 電子部品
US20180159006A1 (en) Light emitting device and solder bond structure
US10483256B2 (en) Optoelectronic semiconductor device and apparatus with an optoelectronic semiconductor device
US20130163632A1 (en) Light emitting device
JP2014120502A (ja) 発光装置
JP2013069988A (ja) 半導体装置とその製造方法
US11735507B2 (en) Wiring substrate, electronic device, and electronic module
US10651038B2 (en) Semiconductor device
JP7517917B2 (ja) 半導体発光装置
US11177233B2 (en) Solder pads of variable thickness in an optoelectronic semiconductor chip, on a connection substrate for mounting a semiconductor chip, method of producing an optoelectronic component, and optoelectronic component having the solder pads
JP2009076614A (ja) 半導体装置
JP2020061544A (ja) 配線基板
JP2007158165A (ja) 半導体装置および半導体装置実装基板
JP2009038127A (ja) 半導体装置

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170324

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20171121

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20180117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180904

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20181031

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181226

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190528

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190621

R150 Certificate of patent or registration of utility model

Ref document number: 6546376

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees