JP6533089B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP6533089B2 JP6533089B2 JP2015086436A JP2015086436A JP6533089B2 JP 6533089 B2 JP6533089 B2 JP 6533089B2 JP 2015086436 A JP2015086436 A JP 2015086436A JP 2015086436 A JP2015086436 A JP 2015086436A JP 6533089 B2 JP6533089 B2 JP 6533089B2
- Authority
- JP
- Japan
- Prior art keywords
- connector
- connection pad
- conductor layer
- wiring board
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
2 導体層
2A 表層導体層
6 コネクタ接続パッド
13 挿抜コネクタ
C 括れ部
P 突起部
T 頂部
Claims (1)
- 複数の絶縁層が積層されて成る絶縁基体の表面に、挿抜コネクタが半田接続されるコネクタ接続パッドを形成する銅箔から成る表層導体層が埋入されて成る配線基板であって、前記表層導体層は、前記絶縁基体の表面に埋入された側の主面が多数の突起部を有するピークカウントが15以上のマット面から成り、前記突起部の先端部に括れ部と、該括れ部よりも2〜5μm径大であり、互いに隣接するもの同士が離隔した状態で位置する頂部とを形成する電解銅めっきが被着されていることを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015086436A JP6533089B2 (ja) | 2015-04-21 | 2015-04-21 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015086436A JP6533089B2 (ja) | 2015-04-21 | 2015-04-21 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016207794A JP2016207794A (ja) | 2016-12-08 |
JP6533089B2 true JP6533089B2 (ja) | 2019-06-19 |
Family
ID=57490207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015086436A Active JP6533089B2 (ja) | 2015-04-21 | 2015-04-21 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6533089B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6985477B1 (ja) * | 2020-09-25 | 2021-12-22 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3441368B2 (ja) * | 1998-05-29 | 2003-09-02 | 京セラ株式会社 | 多層配線基板およびその製造方法 |
JP4129166B2 (ja) * | 2002-10-29 | 2008-08-06 | 京セラ株式会社 | 電解銅箔、電解銅箔付きフィルム及び多層配線基板と、その製造方法 |
JP2004319976A (ja) * | 2003-03-28 | 2004-11-11 | Matsushita Electric Ind Co Ltd | 転写シート及びそれを用いた配線基板とその製造方法 |
KR100974373B1 (ko) * | 2008-02-28 | 2010-08-05 | 엘에스엠트론 주식회사 | 인쇄회로용 동박의 표면처리 방법과 그 동박 및 도금장치 |
-
2015
- 2015-04-21 JP JP2015086436A patent/JP6533089B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2016207794A (ja) | 2016-12-08 |
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