JP6505726B2 - 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 - Google Patents
半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 Download PDFInfo
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- JP6505726B2 JP6505726B2 JP2016549259A JP2016549259A JP6505726B2 JP 6505726 B2 JP6505726 B2 JP 6505726B2 JP 2016549259 A JP2016549259 A JP 2016549259A JP 2016549259 A JP2016549259 A JP 2016549259A JP 6505726 B2 JP6505726 B2 JP 6505726B2
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Description
表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板、
表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板、及び
第1のガラス基板と第2のガラス基板の間に配されて、第1のガラス基板の第2の主表面を第2のガラス基板の第1の主表面に接合している、インタフェース、
を有することができる。例として、CTE1をCTE2より小さくすることができ、第1のガラス基板の第1の主表面は1つ以上の半導体チップを係合するためにはたらき、第2のガラス基板の第2の主表面は有機基板を係合するためにはたらく。
表裏をなす第1及び第2の主表面を有する第3のガラス基板であって、第3の熱膨張係数(CTE3)を有する第3のガラス基板、
をさらに有し、
第2のガラス基板と第3のガラス基板は第2のガラス基板の第2の主表面が第3のガラス基板の第1の主表面に接合されるように融着される。
CTE1がCTE2より小さく、CTE3がCTE2より小さい、
にしたがうことができる。あるいは、それぞれのCTEは以下の関係:
CTE1がCTE2より小さく、CTE2がCTE3より小さい、
にしたがうことができる。
1≦CTE1(ppm/℃)≦10及び5≦CTE2(ppm/℃)≦15
にしたがうことができる。さらに、またはあるいは、1つ以上の実施形態は以下の関係:
3≦CTE1(ppm/℃)≦5及び8≦CTE2(ppm/℃)≦10
にしたがうことができる。
第1のガラス基板110-1の第1の主表面(図示されるように上面)は1つ以上の半導体チップ10-1、10-2を係合するために適合される、及び
第3のガラス基板110-3の第2の主表面(図示されるように下面)は有機パッケージ基板20を係合するために適合される、
で用いられると想定される。
1≦CTE1(ppm/℃)≦10、5≦CTE2(ppm/℃)≦15、及び
1≦CTE3(ppm/℃)≦10、
にしたがうことができる。あるいは、1つ以上の実施形態において、CTEは以下の関係:
3≦CTE1(ppm/℃)≦5、8≦CTE2(ppm/℃)≦10、及び
3≦CTE3(ppm/℃)≦5、
にしたがうことができる。
1≦CTE1(ppm/℃)≦10、3≦CTE2(ppm/℃)≦12、及び
5≦CTE3(ppm/℃)≦15、
にしたがうことができる。あるいは、1つ以上の実施形態において、CTEは以下の関係:
3≦CTE1(ppm/℃)≦5、5≦CTE2(ppm/℃)≦8、及び
8≦CTE3(ppm/℃)≦10、
にしたがうことができる。
半導体パッケージ内で1つ以上の半導体チップを有機基板と相互接続するためのインタポーザにおいて、前記インタポーザが、
表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板、
表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板、及び
前記第1のガラス基板と前記第2のガラス基板の間に配され、前記第1のガラス基板の前記第2の主表面を前記第2のガラス基板の前記第1の主表面に接合する、インタフェース、
を有し、
前記CTE1が前記CTE2より小さく、前記第1のガラス基板の前記第1の主表面が前記1つ以上の半導体チップを係合するためにはたらき、前記第2のガラス基板の前記第2の主表面が前記有機基板を係合するためにはたらく、
インタポーザ。
1≦CTE1(ppm/℃)≦10及び5≦CTE2(ppm/℃)≦15である、実施形態1に記載のインタポーザ。
3≦CTE1(ppm/℃)≦5及び8≦CTE2(ppm/℃)≦10である、実施形態1に記載のインタポーザ。
前記インタフェースが接着剤で形成される、実施形態1から3のいずれかに記載のインタポーザ。
前記インタフェースがシリコン−酸化物接合で形成される、実施形態1から3のいずれかに記載のインタポーザ。
前記インタフェースが前記第1のガラス基板及び前記第2のガラス基板の融解温度よりかなり低い融解温度を有するガラス材料で形成される、実施形態1から5のいずれかに記載のインタポーザ。
半導体パッケージ内で1つ以上の半導体チップを有機基板と相互接続するためのインタポーザにおいて、前記インタポーザが、
表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板、
表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板、及び
表裏をなす第1及び第2の主表面を有する第3のガラス基板、前記第3のガラス基板は第3の熱膨張係数(CTE3)を有する、
を有し、
前記第1のガラス基板と前記第2のガラス基板は、前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第2のガラス基板と前記第3のガラス基板は、前記第2のガラス基板の前記第2の主表面が前記第3のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第1のガラス基板の前記第1の主表面は前記1つ以上の半導体チップを係合するためにはたらき、前記第3のガラス基板の前記第2の主表面は前記有機基板を係合するためにはたらく、
インタポーザ。
前記CTE1が前記CTE2より小さく、前記CTE3が前記CTE2より小さい、実施形態7に記載のインタポーザ。
1≦CTE1(ppm/℃)≦10、5≦CTE2(ppm/℃)≦15、及び1≦CTE3(ppm/℃)≦10である、実施形態8に記載のインタポーザ。
3≦CTE1(ppm/℃)≦5、8≦CTE2(ppm/℃)≦10、及び3≦CTE3(ppm/℃)≦5である、実施形態8に記載のインタポーザ。
前記CTE1が前記CTE2より小さく、前記CTE2が前記CTE3より小さい、実施形態7に記載のインタポーザ。
1≦CTE1(ppm/℃)≦10、3≦CTE2(ppm/℃)≦12、及び5≦CTE3(ppm/℃)≦15である、実施形態11に記載のインタポーザ。
3≦CTE1(ppm/℃)≦5、5≦CTE2(ppm/℃)≦8、及び8≦CTE3(ppm/℃)≦10である、実施形態11に記載のインタポーザ。
半導体パッケージを作製する方法において、
少なくとも1つの半導体チップを提供する工程、
有機基板を提供する工程、及び
前記半導体チップと前記有機基板の間にインタポーザを配する工程、
を含み、
前記インタポーザが、
(i)表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板、
(ii)表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板、及び
(iii)前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に直接または間接に結合されるような、前記第1のガラス基板と前記第2のガラス基板の相互結合手段、
を有し、
前記CTE1が前記CTE2より小さく、
前記第1のガラス基板の前記第1の主表面が前記少なくとも1つの半導体チップを直接または間接に係合し、
前記第2のガラス基板の前記第2の主表面が前記有機基板を直接または間接に係合する、
方法。
1≦CTE1(ppm/℃)≦10及び5≦CTE2(ppm/℃)≦15、及び
3≦CTE1(ppm/℃)≦5及び8≦CTE2(ppm/℃)≦10、
の少なくとも一方である、実施形態14に記載の方法。
前記インタポーザが、
表裏をなす第1及び第2の主表面を有する第3のガラス基板であって、第3の熱膨張係数(CTE3)を有する第3のガラス基板、
をさらに有し、
前記第1のガラス基板と前記第2のガラス基板は、前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第2のガラス基板と前記第3のガラス基板は、前記第2のガラス基板の前記第2の主表面が前記第3のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第1のガラス基板の前記第1の主表面は前記少なくとも1つの半導体チップを直接または間接に係合し、
前記第3のガラス基板の前記第2の主表面は前記有機基板を直接または間接に係合する、
実施形態14または15に記載の方法。
前記CTE1が前記CTE2より小さく、前記CTE3が前記CTE2より小さい、実施形態16に記載の方法。
1≦CTE1(ppm/℃)≦10、5≦CTE2(ppm/℃)≦15及び1≦CTE3(ppm/℃)≦10、及び
3≦CTE1(ppm/℃)≦5、8≦CTE2(ppm/℃)≦10及び3≦CTE3(ppm/℃)≦5
の少なくとも一方である、実施形態17に記載の方法。
前記CTE1が前記CTE2より小さく、前記CTE2が前記CTE3より小さい、実施形態16に記載の方法。
1≦CTE1(ppm/℃)≦10、3≦CTE2(ppm/℃)≦12
及び5≦CTE3(ppm/℃)≦15、及び
3≦CTE1(ppm/℃)≦5、5≦CTE2(ppm/℃)≦8及び8≦CTE3(ppm/℃)≦10
の少なくとも一方である、実施形態19に記載の方法。
20 有機パッケージ基板
30-1,30-2,30-3,30-4 接続機構
40 ハウジング
50-1,50-2 バイア
100,100-1 縦集積化構造
102,102-1,102-2,102-3,102-4,102-5 インタポーザ
104,106 インタポーザの主表面
110,110-1,110-2,110-3 ガラス基板
112,112-1,112-2,112-3 インタフェース
114-1,114-2,116-1,116-2 ガラス基板の主表面
Claims (10)
- 半導体パッケージ内で1つ以上の半導体チップを有機基板と相互接続するためのインタポーザにおいて、前記インタポーザが、
表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板と、
表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板と、
前記第1のガラス基板と前記第2のガラス基板の間に配され、前記第1のガラス基板の前記第2の主表面を前記第2のガラス基板の前記第1の主表面に接合する、インタフェースと、を有し、
前記CTE1が前記CTE2より小さく、前記第1のガラス基板の前記第1の主表面が前記1つ以上の半導体チップを係合するためにはたらき、前記第2のガラス基板の前記第2の主表面が前記有機基板を係合するためにはたらき、
前記インタフェースが、前記第1のガラス基板及び前記第2のガラス基板の融解温度より低い融解温度である中間ガラス材料からなることを特徴とするインタポーザ。 - 1≦CTE1(ppm/℃)≦10及び5≦CTE2(ppm/℃)≦15、あるいは、
3≦CTE1(ppm/℃)≦5及び8≦CTE2(ppm/℃)≦10であることを特徴とする請求項1に記載のインタポーザ。 - 前記インタフェースの厚さは、10μmから20μmの範囲内の値である、請求項1または2に記載のインタポーザ。
- 半導体パッケージ内で1つ以上の半導体チップを有機基板と相互接続するためのインタポーザにおいて、前記インタポーザが、
表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板と、
表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板と、
表裏をなす第1及び第2の主表面を有する第3のガラス基板であって、第3の熱膨張係数(CTE3)を有する第3のガラス基板と、
前記第1のガラス基板と前記第2のガラス基板との間に配され、前記第1のガラス基板の前記第2の主表面を前記第2のガラス基板の前記第1の主表面に接合する、インタフェースと、を有し、
前記インタフェースが、前記第1のガラス基板及び前記第2のガラス基板の融解温度より低い融解温度である中間ガラス材料からなるものであり、
前記第1のガラス基板と前記第2のガラス基板は、前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第2のガラス基板と前記第3のガラス基板は、前記第2のガラス基板の前記第2の主表面が前記第3のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第1のガラス基板の前記第1の主表面は前記1つ以上の半導体チップを係合するために適合され、前記第3のガラス基板の前記第2の主表面は前記有機基板を係合するために適合された、ことを特徴とするインタポーザ。 - 前記CTE1が前記CTE2より小さく、前記CTE3が前記CTE2より小さい、及び
1≦CTE1(ppm/℃)≦10、5≦CTE2(ppm/℃)≦15及び1≦CTE3(ppm/℃)≦10、あるいは、3≦CTE1(ppm/℃)≦5、8≦CTE2(ppm/℃)≦10及び3≦CTE3(ppm/℃)≦5、
であることを特徴とする請求項4に記載のインタポーザ。 - 前記CTE1が前記CTE2より小さく、前記CTE2が前記CTE3より小さい、及び
1≦CTE1(ppm/℃)≦10、3≦CTE2(ppm/℃)≦12及び5≦CTE3(ppm/℃)≦15、あるいは、3≦CTE1(ppm/℃)≦5、5≦CTE2(ppm/℃)≦8及び8≦CTE3(ppm/℃)≦10、
であることを特徴とする請求項4に記載のインタポーザ。 - 半導体パッケージを作製する方法において、
少なくとも1つの半導体チップを提供する工程と、
有機基板を提供する工程と、
前記半導体チップと前記有機基板の間にインタポーザを配する工程と、
を含み、
前記インタポーザが、
(i)表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板と、
(ii)表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板と、
(iii)前記第1のガラス基板と前記第2のガラス基板の、前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に直接または間接に結合されるような、相互結合手段と、を有し、
前記CTE1が前記CTE2より小さく、
前記第1のガラス基板の前記第1の主表面が前記少なくとも1つの半導体チップを直接または間接に係合し、
前記第2のガラス基板の前記第2の主表面が前記有機基板を直接または間接に係合し、
前記相互結合手段が、前記第1のガラス基板及び前記第2のガラス基板の融解温度より低い融解温度である中間ガラス材料からなるインタフェースを含むことを特徴とする方法。 - 1≦CTE1(ppm/℃)≦10及び5≦CTE2(ppm/℃)≦15、あるいは、
3≦CTE1(ppm/℃)≦5及び8≦CTE2(ppm/℃)≦10、
であることを特徴とする請求項7に記載の方法。 - 半導体パッケージを作製する方法において、
少なくとも1つの半導体チップを提供する工程と、
有機基板を提供する工程と、
前記半導体チップと前記有機基板の間にインタポーザを配する工程と、
を含み、
前記インタポーザが、
(i)表裏をなす第1及び第2の主表面を有する第1のガラス基板であって、第1の熱膨張係数(CTE1)を有する第1のガラス基板と、
(ii)表裏をなす第1及び第2の主表面を有する第2のガラス基板であって、第2の熱膨張係数(CTE2)を有する第2のガラス基板と、
(iii)表裏をなす第1及び第2の主表面を有する第3のガラス基板であって、第3の熱膨張係数(CTE3)を有する第3のガラス基板と、を有し、
前記第1のガラス基板と前記第2のガラス基板は、前記第1のガラス基板の前記第2の主表面が前記第2のガラス基板の前記第1の主表面に接合されるように、前記第1のガラス基板及び前記第2のガラス基板の融解温度より低い融解温度である中間ガラス材料からなるインタフェースを介して融着され、
前記第2のガラス基板と前記第3のガラス基板は、前記第2のガラス基板の前記第2の主表面が前記第3のガラス基板の前記第1の主表面に接合されるように、融着され、
前記第1のガラス基板の前記第1の主表面は前記少なくとも1つの半導体チップに直接または間接に係合され、
前記第3のガラス基板の前記第2の主表面は前記有機基板に直接または間接に係合される、
ことを特徴とする方法。 - 前記CTE1が前記CTE2より小さく、前記CTE3が前記CTE2より小さい、及び
1≦CTE1(ppm/℃)≦10、5≦CTE2(ppm/℃)≦15及び1≦CTE3(ppm/℃)≦10、あるいは、3≦CTE1(ppm/℃)≦5、8≦CTE2(ppm/℃)≦10及び3≦CTE3(ppm/℃)≦5、
であることを特徴とする請求項9に記載の方法。
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EP (1) | EP3100300A1 (ja) |
JP (1) | JP6505726B2 (ja) |
KR (1) | KR20160114710A (ja) |
CN (1) | CN106165088B (ja) |
TW (1) | TWI653713B (ja) |
WO (1) | WO2015116749A1 (ja) |
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US20180190583A1 (en) * | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
KR20190092584A (ko) | 2016-12-29 | 2019-08-07 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
WO2018183739A1 (en) | 2017-03-31 | 2018-10-04 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
DE202018006774U1 (de) | 2017-06-15 | 2022-12-13 | Chiaro Technology Limited | Brustpumpensystem |
WO2019027893A1 (en) * | 2017-07-31 | 2019-02-07 | Corning Incorporated | LAMINATE ARTICLE HAVING A CENTRAL NON-GLASS PART AND A GLASS ENVELOPE AND ASSOCIATED METHODS |
TWI653919B (zh) * | 2017-08-10 | 2019-03-11 | 晶巧股份有限公司 | 高散熱等線距堆疊晶片封裝結構和方法 |
US10622311B2 (en) | 2017-08-10 | 2020-04-14 | International Business Machines Corporation | High-density interconnecting adhesive tape |
TW201936376A (zh) * | 2017-12-21 | 2019-09-16 | 美商康寧公司 | 包含低cte玻璃層的多層隔熱玻璃單元 |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
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US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
EP3913662A4 (en) | 2019-03-12 | 2022-11-02 | Absolics Inc. | PACKAGING SUBSTRATE AND METHOD OF MANUFACTURE THEREOF |
EP3916771A4 (en) | 2019-03-12 | 2023-01-11 | Absolics Inc. | PACKAGING SUBSTRATE AND EQUIPPED SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE |
EP3916772A4 (en) | 2019-03-12 | 2023-04-05 | Absolics Inc. | PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE WITH IT |
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WO2021040178A1 (ko) | 2019-08-23 | 2021-03-04 | 에스케이씨 주식회사 | 패키징 기판 및 이를 포함하는 반도체 장치 |
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WO2015116749A1 (en) * | 2014-01-31 | 2015-08-06 | Corning Incorporated | Methods and apparatus for providing an interposer for interconnecting semiconductor chips |
-
2015
- 2015-01-29 WO PCT/US2015/013405 patent/WO2015116749A1/en active Application Filing
- 2015-01-29 EP EP15703412.5A patent/EP3100300A1/en not_active Withdrawn
- 2015-01-29 JP JP2016549259A patent/JP6505726B2/ja not_active Expired - Fee Related
- 2015-01-29 US US14/608,537 patent/US9472479B2/en not_active Expired - Fee Related
- 2015-01-29 KR KR1020167023963A patent/KR20160114710A/ko not_active Application Discontinuation
- 2015-01-29 CN CN201580017695.7A patent/CN106165088B/zh not_active Expired - Fee Related
- 2015-01-30 TW TW104103256A patent/TWI653713B/zh not_active IP Right Cessation
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2016
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Also Published As
Publication number | Publication date |
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US20150221571A1 (en) | 2015-08-06 |
JP2017505998A (ja) | 2017-02-23 |
US20170025341A1 (en) | 2017-01-26 |
WO2015116749A1 (en) | 2015-08-06 |
TWI653713B (zh) | 2019-03-11 |
US9472479B2 (en) | 2016-10-18 |
TW201535622A (zh) | 2015-09-16 |
CN106165088A (zh) | 2016-11-23 |
CN106165088B (zh) | 2019-03-01 |
EP3100300A1 (en) | 2016-12-07 |
KR20160114710A (ko) | 2016-10-05 |
US9917045B2 (en) | 2018-03-13 |
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