JP6503395B2 - 静電放電回路 - Google Patents
静電放電回路 Download PDFInfo
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- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
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- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
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- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Description
Claims (9)
- パッドに接続される静電放電(ESD)回路であって、
p型トランジスタと、n型トランジスタと、制御回路を有し、
前記p型トランジスタの第1ソース/ドレイン端子が前記パッドに接続され、
前記n型トランジスタの第1ソース/ドレイン端子が前記p型トランジスタの第2ソース/ドレイン端子に接続され、かつ、前記n型トランジスタの第2ソース/ドレイン端子は第1ノードに接続され、
前記制御回路は、第1抵抗器と、第2抵抗器と、複数のダイオードを有し、
前記第1抵抗器の第1端子は前記パッドに接続され、かつ、前記第1抵抗器の第2端子は第2ノードに接続され、
前記第2抵抗器の第1端子は前記第1ノードに接続され、かつ、前記第2抵抗器の第2端子は第3ノードに接続され、
前記複数のダイオードは、前記第2ノードと前記第3ノードとの間で直列に接続され、
前記p型トランジスタのゲート端子は前記第2ノードに接続され、かつ、前記n型トランジスタの前記ゲート端子は前記第3ノードに接続され、
前記パッドがESDザッピングを受け取るとき、前記制御回路は、前記p型トランジスタへ第1電圧降下を供し、かつ、前記n型トランジスタへ第2電圧降下を供し、前記p型トランジスタと前記n型トランジスタは、前記第1電圧降下と前記第2電圧降下に応じてターンオンされる、
ESD回路。 - 前記複数のダイオードのうちの最初のダイオードのアノード端子は前記第2ノードに接続され、
前記複数のダイオードのうちの最後のダイオードのカソード端子は前記第3ノードに接続され、
前記複数のダイオードのうちの任意の他のダイオードのアノード端子は、前記任意の他のダイオードの直前のダイオードのカソード端子に接続され、かつ、
前記複数のダイオードのうちの任意の他のダイオードのカソード端子は、前記任意の他のダイオードの直後のダイオードのアノード端子に接続される、
請求項1に記載のESD回路。 - 前記パッドが前記ESDザッピングを受け取るとき、前記制御回路は負荷電流を受け取り、
前記負荷電流が前記第1抵抗器を貫流することで、前記第1電圧降下が生じ、かつ、
前記負荷電流が前記第2抵抗器を貫流することで、前記第2電圧降下が生じる、
請求項1に記載のESD回路。 - 前記パッドと内部回路との間で接続されるスイッチトランジスタをさらに有する請求項1に記載のESD回路であって、
前記スイッチトランジスタの第1ソース/ドレイン端子は前記パッドに接続され、
前記スイッチトランジスタの第2ソース/ドレイン端子は前記内部回路に接続され、かつ、
前記スイッチトランジスタのゲート端子は正常低信号を受け取る、
ESD回路。 - 前記p型トランジスタの主端子が前記パッドに接続され、かつ、
前記n型トランジスタの主端子が前記第1ノードに接続される、
請求項1に記載のESD回路。 - パッドに接続される静電放電(ESD)回路であって、
前記パッドと第1ノードとの間でカスケード状に接続される複数のトランジスタ、
前記パッド、前記第1ノード、及び前記複数のトランジスタのゲート端子に接続される制御回路、を有し、
前記複数のトランジスタの第1部分は複数のp型トランジスタを含み、かつ、前記複数のトランジスタの第2部分は少なくとも1つのn型トランジスタを含み、
前記パッドがESDザッピングを受け取るとき、前記制御回路は前記複数のトランジスタにそれぞれ複数の電圧降下を与え、かつ、前記複数のトランジスタは前記複数の電圧降下に応じてターンオンされる、
ESD回路。 - 前記制御回路が、
第2ノードと第3ノードとの間で直列に接続する複数のダイオード、及び、
複数の抵抗器、
を有し、
前記パッドが前記ESDザッピングを受け取るとき、前記制御回路及び前記複数のダイオードは負荷電流を受け取り、
前記負荷電流が前記複数の抵抗器を流れることで、前記複数の抵抗器に対応する電圧降下が生じる、
請求項6に記載のESD回路。 - 前記複数のダイオードのうちの最初のダイオードのアノード端子は前記第2ノードに接続され、
前記複数のダイオードのうちの最後のダイオードのカソード端子は前記第3ノードに接続され、
前記複数のダイオードのうちの任意の他のダイオードのアノード端子は、前記任意の他のダイオードの直前のダイオードのカソード端子に接続され、かつ、
前記複数のダイオードのうちの任意の他のダイオードのアノード端子は、前記任意の他のダイオードの直後のダイオードのアノード端子に接続される、
請求項7に記載のESD回路。 - 前記パッドと内部回路との間で接続されるスイッチトランジスタをさらに有する請求項6に記載のESD回路であって、
前記スイッチトランジスタの第1ソース/ドレイン端子は前記パッドに接続され、
前記スイッチトランジスタの第2ソース/ドレイン端子は前記内部回路に接続され、かつ、
前記スイッチトランジスタのゲート端子は正常低信号を受け取る、
ESD回路。
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US201662406968P | 2016-10-12 | 2016-10-12 | |
US62/406,968 | 2016-10-12 |
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JP2017055336A Active JP6503395B2 (ja) | 2016-10-12 | 2017-03-22 | 静電放電回路 |
JP2017198062A Active JP6550664B2 (ja) | 2016-10-12 | 2017-10-11 | アンチヒューズ物理的複製不可能関数ユニットおよび関連する制御方法 |
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CN107768373B (zh) * | 2016-08-15 | 2022-05-10 | 华邦电子股份有限公司 | 存储元件及其制造方法 |
JP7114985B2 (ja) | 2018-03-29 | 2022-08-09 | スミダコーポレーション株式会社 | コイル部品、電子機器、金属磁性粉末および支援装置 |
TWI669714B (zh) * | 2018-05-29 | 2019-08-21 | 力旺電子股份有限公司 | 電壓控制裝置及記憶體系統 |
TWI782882B (zh) * | 2018-06-01 | 2022-11-01 | 聯華電子股份有限公司 | 半導體裝置 |
US11282844B2 (en) * | 2018-06-27 | 2022-03-22 | Ememory Technology Inc. | Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate |
US10839872B2 (en) * | 2018-07-03 | 2020-11-17 | Ememory Technology Inc. | Random bit cell using an initial state of a latch to generate a random bit |
US10797064B2 (en) * | 2018-09-19 | 2020-10-06 | Ememory Technology Inc. | Single-poly non-volatile memory cell and operating method thereof |
US11416416B2 (en) * | 2019-01-13 | 2022-08-16 | Ememory Technology Inc. | Random code generator with non-volatile memory |
US10770158B1 (en) * | 2019-05-15 | 2020-09-08 | Western Digital Technologies, Inc. | Detecting a faulty memory block |
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